From: Jan Michel Date: Thu, 28 Sep 2017 15:11:28 +0000 (+0200) Subject: remove Serdes ports X-Git-Tag: v2.3~29 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=730881f281e480eb38979d1233cbf8d759fce413;p=tdc.git remove Serdes ports --- diff --git a/releases/tdc_v2.3/trb3_periph_ADA.vhd b/releases/tdc_v2.3/trb3_periph_ADA.vhd index 8667bfb..a2d2a43 100644 --- a/releases/tdc_v2.3/trb3_periph_ADA.vhd +++ b/releases/tdc_v2.3/trb3_periph_ADA.vhd @@ -25,10 +25,10 @@ entity trb3_periph_ADA is --Serdes CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems - SERDES_INT_TX : out std_logic_vector(3 downto 0); - SERDES_INT_RX : in std_logic_vector(3 downto 0); - SERDES_ADDON_TX : out std_logic_vector(11 downto 0); - SERDES_ADDON_RX : in std_logic_vector(11 downto 0); +-- SERDES_INT_TX : out std_logic_vector(3 downto 0); +-- SERDES_INT_RX : in std_logic_vector(3 downto 0); +-- SERDES_ADDON_TX : out std_logic_vector(11 downto 0); +-- SERDES_ADDON_RX : in std_logic_vector(11 downto 0); --Inter-FPGA Communication FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active @@ -200,7 +200,7 @@ begin --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) --------------------------------------------------------------------------- - THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + THE_MEDIA_UPLINK : entity work.trb_net16_med_ecp3_sfp generic map( SERDES_NUM => 1, --number of serdes in quad EXT_CLOCK => c_NO, --use internal clock @@ -225,10 +225,10 @@ begin MED_READ_IN => '1', REFCLK2CORE_OUT => open, --SFP Connection - SD_RXD_P_IN => SERDES_INT_RX(2), - SD_RXD_N_IN => SERDES_INT_RX(3), - SD_TXD_P_OUT => SERDES_INT_TX(2), - SD_TXD_N_OUT => SERDES_INT_TX(3), +-- SD_RXD_P_IN => SERDES_INT_RX(2), +-- SD_RXD_N_IN => SERDES_INT_RX(3), +-- SD_TXD_P_OUT => SERDES_INT_TX(2), +-- SD_TXD_N_OUT => SERDES_INT_TX(3), SD_REFCLK_P_IN => open, SD_REFCLK_N_IN => open, SD_PRSNT_N_IN => FPGA5_COMM(0),