From: hadeshyp Date: Wed, 28 Nov 2012 13:14:34 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~24 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=73553f7a88007c415166545d53b7087b6442ba20;p=trbnet.git *** empty log message *** --- diff --git a/lattice/ecp2m/fifo/fifo_36x4k_oreg.lpc b/lattice/ecp2m/fifo/fifo_36x4k_oreg.lpc index b3cefb8..f119d82 100644 --- a/lattice/ecp2m/fifo/fifo_36x4k_oreg.lpc +++ b/lattice/ecp2m/fifo/fifo_36x4k_oreg.lpc @@ -2,7 +2,7 @@ Family=latticeecp2m PartType=LFE2M20E PartName=LFE2M20E-5F256C -SpeedGrade=-5 +SpeedGrade=5 Package=FPBGA256 OperatingCondition=COM Status=P @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=FIFO -CoreRevision=4.7 +CoreRevision=4.8 ModuleName=fifo_36x4k_oreg -SourceFormat=Schematic/VHDL +SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/31/2010 -Time=11:36:03 +Date=11/27/2012 +Time=17:30:20 [Parameters] Verilog=0 @@ -42,3 +42,4 @@ PfAssert=508 PfDeassert=506 RDataCount=1 EnECC=0 +EnFWFT=0 diff --git a/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd b/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd index ef9478c..7df5f90 100644 --- a/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd +++ b/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) --- Module Version: 4.7 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 36 -depth 4096 -regout -no_enable -pe -1 -pf 0 -fill -e +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) +-- Module Version: 4.8 +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 36 -depth 4096 -regout -no_enable -pe -1 -pf 0 -fill -e --- Wed Mar 31 11:36:04 2010 +-- Tue Nov 27 17:30:20 2012 library IEEE; use IEEE.std_logic_1164.all; @@ -1504,23 +1504,16 @@ begin -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + port map (D=>rptr_11, SP=>scuba_vhi, CK=>Clock, CD=>scuba_vlo, Q=>rptr_11_ff); --- FF_14: FD1P3DX --- -- synopsys translate_off --- generic map (GSR=> "ENABLED") --- -- synopsys translate_on --- port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, --- Q=>rptr_11_ff2); FF_14: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rptr_11_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo, + port map (D=>rptr_11_ff, SP=>scuba_vhi, CK=>Clock, CD=>scuba_vlo, Q=>rptr_11_ff2); - - + FF_13: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") @@ -1782,7 +1775,6 @@ begin port map (CI=>co5_4, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6_2, NC0=>ircount_12, NC1=>open); ---output mux mux_35: MUX21 port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff2, Z=>Q(0)); @@ -1927,7 +1919,6 @@ begin port map (D0=>mdout1_0_35, D1=>mdout1_1_35, SD=>rptr_11_ff2, Z=>Q(35)); ---wcount - rptr wcnt_0: FSUB2B port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, S1=>wcnt_sub_0); @@ -1957,7 +1948,6 @@ begin B1=>scuba_vlo, BI=>co5_5, BOUT=>co6_3, S0=>wcnt_sub_11, S1=>wcnt_sub_12); ---almost full wcntd: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, CI=>co6_3, COUT=>open, S0=>co6_3d, S1=>open); @@ -2044,4 +2034,4 @@ configuration Structure_CON of fifo_36x4k_oreg is end for; end Structure_CON; --- synopsys translate_on \ No newline at end of file +-- synopsys translate_on diff --git a/lattice/ecp3/fifo/fifo_36x4k_oreg.ipx b/lattice/ecp3/fifo/fifo_36x4k_oreg.ipx index 06f8592..288444c 100644 --- a/lattice/ecp3/fifo/fifo_36x4k_oreg.ipx +++ b/lattice/ecp3/fifo/fifo_36x4k_oreg.ipx @@ -1,9 +1,9 @@ - + - - - - + + + + diff --git a/lattice/ecp3/fifo/fifo_36x4k_oreg.lpc b/lattice/ecp3/fifo/fifo_36x4k_oreg.lpc index 6fba3b0..43996ec 100644 --- a/lattice/ecp3/fifo/fifo_36x4k_oreg.lpc +++ b/lattice/ecp3/fifo/fifo_36x4k_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=4.8 ModuleName=fifo_36x4k_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=09/12/2011 -Time=17:43:23 +Date=11/27/2012 +Time=19:32:53 [Parameters] Verilog=0 diff --git a/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd b/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd index b6d1bb8..fad6047 100644 --- a/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd +++ b/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) +-- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) -- Module Version: 4.8 ---/d/sugar/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 36 -depth 4096 -regout -no_enable -pe -1 -pf 0 -fill -e +--/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 36 -depth 4096 -regout -no_enable -pe -1 -pf 0 -fill -e --- Mon Sep 12 17:43:23 2011 +-- Tue Nov 27 19:32:53 2012 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp3/fifo/fifo_36x4k_oreg_tmpl.vhd b/lattice/ecp3/fifo/fifo_36x4k_oreg_tmpl.vhd index caf683e..0f599d5 100644 --- a/lattice/ecp3/fifo/fifo_36x4k_oreg_tmpl.vhd +++ b/lattice/ecp3/fifo/fifo_36x4k_oreg_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA Diamond_1.3_Production (92) +-- VHDL module instantiation generated by SCUBA Diamond_1.4_Production (87) -- Module Version: 4.8 --- Mon Sep 12 17:43:23 2011 +-- Tue Nov 27 19:32:53 2012 -- parameterized module component declaration component fifo_36x4k_oreg diff --git a/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd b/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd index bad31a7..3323136 100644 --- a/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd +++ b/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd @@ -1638,11 +1638,11 @@ begin Q=>rptr_12_ff); FF_16: FD1P3DX - port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + port map (D=>rptr_11_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo, Q=>rptr_11_ff2); FF_15: FD1P3DX - port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, + port map (D=>rptr_12_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo, Q=>rptr_12_ff2); FF_14: FD1S3DX diff --git a/lattice/ecp3/fifo/tb_fifo_36x4k_oreg_tmpl.vhd b/lattice/ecp3/fifo/tb_fifo_36x4k_oreg_tmpl.vhd index fb8a093..728ee30 100644 --- a/lattice/ecp3/fifo/tb_fifo_36x4k_oreg_tmpl.vhd +++ b/lattice/ecp3/fifo/tb_fifo_36x4k_oreg_tmpl.vhd @@ -1,4 +1,4 @@ --- VHDL testbench template generated by SCUBA Diamond_1.3_Production (92) +-- VHDL testbench template generated by SCUBA Diamond_1.4_Production (87) library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;