From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Fri, 27 Feb 2015 15:03:04 +0000 (+0100)
Subject: DEBUG should be in clk_rd aka ADC clock domain
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=74679c05ac2cb2c6340a05fcc5dd168fc24a3c74;p=trb3.git

DEBUG should be in clk_rd aka ADC clock domain
---

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 26e41f6..488f7ea 100644
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -321,7 +321,7 @@ begin
 
     proc_debug : process
     begin
-      wait until rising_edge(CLK);
+      wait until rising_edge(clk_rd);
       state_q(i)                           <= state(i);
       counter_q(i)                         <= counter(i);
       DEBUG(i * 32 + 31 downto i * 32 + 4) <= std_logic_vector(counter_q(i));