From: Ingo Froehlich Date: Fri, 8 Feb 2019 20:01:14 +0000 (+0100) Subject: added error mask bits X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=74cb6cf9da75d7dedc0897d08d321ff785b07c5b;p=trbnet.git added error mask bits --- diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index aea5657..0eeedec 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -123,6 +123,8 @@ signal tx_force_crc_error : std_logic := '0'; signal tx_force_pak_error : std_logic := '0'; signal send_chksum : std_logic := '0'; signal got_chksum : std_logic; +signal enable_chksum_reg : std_logic_vector(3 downto 0) := "0000"; +signal enable_chksum_comb : std_logic_vector(3 downto 0); begin @@ -226,22 +228,27 @@ PROC_START_TIMER : process begin end if; end process; -PROC_RETRANS_COUNTER : process begin - wait until rising_edge(CLK_SYS); - if request_retr_i = '1' then - request_retr_counter <= std_logic_vector(unsigned(request_retr_counter) + 1); - end if; - if start_retr_i = '1' then - start_retr_counter <= std_logic_vector(unsigned(start_retr_counter) + 1); - end if; +--PROC_RETRANS_COUNTER : process begin +-- wait until rising_edge(CLK_SYS); -- if make_link_reset_real_i = '0' then -- request_retr_counter <= x"0000"; -- start_retr_counter <= x"0000"; -- end if; -end process; +--end process; + +enable_chksum_comb(0) <= MEDIA_INT2MED.ctrl_op(8) and not enable_chksum_reg(0); +enable_chksum_comb(3 downto 1) <= not enable_chksum_reg(3 downto 1); PROC_REG : process begin wait until rising_edge(CLK_SYS); + + if request_retr_i = '1' then + request_retr_counter <= std_logic_vector(unsigned(request_retr_counter) + 1); + end if; + if start_retr_i = '1' then + start_retr_counter <= std_logic_vector(unsigned(start_retr_counter) + 1); + end if; + BUS_TX.data <= x"00000000"; BUS_TX.unknown <= '0'; BUS_TX.ack <= '0'; @@ -252,16 +259,17 @@ PROC_REG : process begin crc_error_delay <= BUS_RX.data(7 downto 4); tx_force_crc_error <= BUS_RX.data(8); tx_force_pak_error <= BUS_RX.data(9); - when "01" => force_crc_error <= '0'; tx_force_crc_error <= '0'; tx_force_pak_error <= '0'; + enable_chksum_reg <= BUS_RX.data(19 downto 16); + when "01" => force_crc_error <= '0'; tx_force_crc_error <= '0'; tx_force_pak_error <= '0'; + request_retr_counter <= x"0000"; start_retr_counter <= x"0000"; when others => BUS_TX.unknown <= '1'; end case; elsif BUS_RX.read = '1' then BUS_TX.ack <= '1'; case BUS_RX.addr(1 downto 0) is - when "00" => BUS_TX.data <= x"00000" & "00" & tx_force_pak_error & tx_force_crc_error & crc_error_delay & "000" & force_crc_error; + when "00" => BUS_TX.data <= x"000" & enable_chksum_reg & x"0" & "00" & tx_force_pak_error & tx_force_crc_error & crc_error_delay & "000" & force_crc_error; when "01" => BUS_TX.data <= request_retr_counter & start_retr_counter; --when "11" => BUS_TX.data <= x"000000" & DEBUG_RX_CONTROL_i(31 downto 24); - when "11" => BUS_TX.data <= x"deadface"; when others => BUS_TX.unknown <= '1'; end case; end if; @@ -359,8 +367,9 @@ THE_RX_CONTROL : rx_control FORCE_CRC_ERROR => force_crc_error, CRC_ERROR_DELAY => crc_error_delay, RESET_RETRANSMIT_IN => MEDIA_INT2MED.ctrl_op(15), - --RESET_RETRANSMIT_IN => '0', - ENABLE_CHKSUM => MEDIA_INT2MED.ctrl_op(8), + --RESET_RETRANSMIT_IN => '0', --SIM + --ENABLE_CHKSUM => MEDIA_INT2MED.ctrl_op(8), + ENABLE_CHKSUM => enable_chksum_comb, GOT_CHKSUM => got_chksum, --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM @@ -380,8 +389,6 @@ THE_RX_CONTROL : rx_control RX_DLM <= rx_dlm_i; MEDIA_MED2INT <= media_med2int_i; - - ------------------------------------------------- -- Generate LED signals ------------------------------------------------- diff --git a/media_interfaces/sync/med_sync_define.vhd b/media_interfaces/sync/med_sync_define.vhd index 6c95195..658282b 100644 --- a/media_interfaces/sync/med_sync_define.vhd +++ b/media_interfaces/sync/med_sync_define.vhd @@ -39,7 +39,7 @@ component rx_control is FORCE_CRC_ERROR : in std_logic := '0'; CRC_ERROR_DELAY : in std_logic_vector(3 downto 0); RESET_RETRANSMIT_IN : in std_logic; - ENABLE_CHKSUM : in std_logic; + ENABLE_CHKSUM : in std_logic_vector(3 downto 0); GOT_CHKSUM : out std_logic; --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index 6acc7c9..cb723b4 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -31,8 +31,8 @@ entity rx_control is FORCE_CRC_ERROR : in std_logic; CRC_ERROR_DELAY : in std_logic_vector(3 downto 0); RESET_RETRANSMIT_IN : in std_logic; - ENABLE_CHKSUM : in std_logic; - GOT_CHKSUM : out std_logic; + ENABLE_CHKSUM : in std_logic_vector(3 downto 0); + GOT_CHKSUM : out std_logic; --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM RX_DLM : out std_logic := '0'; @@ -124,7 +124,7 @@ signal num_crc : unsigned(3 downto 0) := (others => '0'); signal num_pak : unsigned(3 downto 0) := (others => '0'); signal resub_mode : std_logic := '0'; signal reset_retrans : std_logic; -signal enable_chksum_sys : std_logic; +signal enable_chksum_200 : std_logic_vector(3 downto 0); signal force_crc_error_int : std_logic := '0'; signal force_crc_error_200 : std_logic := '0'; signal is_idle_100, is_idle : std_logic := '0'; @@ -151,7 +151,7 @@ last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100); last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100); last_use_crc <= use_crc when rising_edge(CLK_100); reset_retrans <= RESET_RETRANSMIT_IN when rising_edge(CLK_100); -enable_chksum_sys <= ENABLE_CHKSUM when rising_edge(CLK_200); +enable_chksum_200 <= ENABLE_CHKSUM when rising_edge(CLK_200); load_use_crc_sys <= load_use_crc when rising_edge(CLK_100); is_idle_100 <= is_idle when rising_edge(CLK_100); @@ -164,10 +164,10 @@ process begin wait until rising_edge(CLK_100); --switch only when fifo is empty: - if is_idle_100 = '1' and ct_fifo_empty = '1' and load_use_crc_sys = '1' then -- and enable_chksum_sys = '1' then + if is_idle_100 = '1' and ct_fifo_empty = '1' and load_use_crc_sys = '1' then --if ct_fifo_empty = '1' and load_use_crc_sys = '1' then use_crc <= '1'; - elsif (ct_fifo_empty = '1' and load_use_crc_sys = '0') then -- or enable_chksum_sys = '0' then + elsif (ct_fifo_empty = '1' and load_use_crc_sys = '0') then use_crc <= '0'; end if; @@ -372,7 +372,7 @@ PROC_RX_FSM : process begin force_crc_error_int <= '1'; end if; end if; - if use_crc_200 = '1' and num_pakets /= 0 and force_crc_error_int = '0' and enable_chksum_sys = '1' then + if use_crc_200 = '1' and num_pakets /= 0 and force_crc_error_int = '0' and enable_chksum_200(0) = '1' and enable_chksum_200(3) = '1' then -- IDLE only allowed after CRC, must be disabled until explicitly -- switched on rx_state <= FIRST; @@ -403,11 +403,11 @@ PROC_RX_FSM : process begin disable_crc <= '0'; force_crc_error_int <= '0'; else - if (crc_q /= reg_rx_data_in + if ((crc_q /= reg_rx_data_in and enable_chksum_200(1) = '1') or (force_crc_error_200 = '1' and CRC_ERROR_DELAY_cnt = "0000") or waiting_for_retr = '1' - or num_pakets /= 5 - or force_crc_error_int = '1') and disable_crc = '0' then + or (num_pakets /= 5 and enable_chksum_200(2) = '1') + or force_crc_error_int = '1') and disable_crc = '0' and enable_chksum_200(0) = '1' then -- bad --if force_crc_error_int = '1' then --debug -- reg_num_pakets <= reg_num_pakets + 1; diff --git a/media_interfaces/sync/sci_reader.vhd b/media_interfaces/sync/sci_reader.vhd index 61c9e3f..7103161 100644 --- a/media_interfaces/sync/sci_reader.vhd +++ b/media_interfaces/sync/sci_reader.vhd @@ -67,7 +67,7 @@ WA_POS_OUT <= wa_position; -- SCI ------------------------------------------------- --gives access to serdes config port from slow control and reads word alignment every ~ 40 us - BUS_TX.unknown <= '0'; +-- BUS_TX.unknown <= '0'; BUS_TX.rack <= '0'; BUS_TX.wack <= '0'; LOC_BUS_RX.addr <= BUS_RX.addr; @@ -79,7 +79,7 @@ begin wait until rising_edge(CLK); BUS_TX.ack <= '0'; BUS_TX.nack <= '0'; - --BUS_TX.unknown <= '0'; + BUS_TX.unknown <= '0'; --BUS_TX.rack <= '0'; --BUS_TX.wack <= '0'; LOC_BUS_RX.read <= '0'; @@ -121,6 +121,7 @@ begin sci_state <= IDLE; BUS_TX.data <= LOC_BUS_TX.data; BUS_TX.ack <= '1'; + BUS_TX.unknown <= LOC_BUS_TX.unknown; end if; else sci_state <= SCTRL_WAIT;