From: hadeshyp <hadeshyp>
Date: Tue, 14 Dec 2010 17:56:45 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~134
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=766ddcd9cd26f85a17c09f9d935ec0eb8e702b12;p=trbnet.git

*** empty log message ***
---

diff --git a/lattice/scm/fifo/fifo_19x16_obuf.ipx b/lattice/scm/fifo/fifo_19x16_obuf.ipx
new file mode 100644
index 0000000..2a7b558
--- /dev/null
+++ b/lattice/scm/fifo/fifo_19x16_obuf.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_19x16_obuf" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2010 12 08 14:00:19.093" version="4.8" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="fifo_19x16_obuf.lpc" type="lpc" modified="2010 12 08 14:00:12.000"/>
+		<File name="fifo_19x16_obuf.vhd" type="top_level_vhdl" modified="2010 12 08 14:00:12.000"/>
+		<File name="fifo_19x16_obuf_tmpl.vhd" type="template_vhdl" modified="2010 12 08 14:00:12.000"/>
+		<File name="tb_fifo_19x16_obuf_tmpl.vhd" type="testbench_vhdl" modified="2010 12 08 14:00:12.000"/>
+  </Package>
+</DiamondModule>
diff --git a/lattice/scm/lattice_scm_fifo_18x1k.lpc b/lattice/scm/lattice_scm_fifo_18x1k.lpc
index c3cf240..4b5f4dd 100644
--- a/lattice/scm/lattice_scm_fifo_18x1k.lpc
+++ b/lattice/scm/lattice_scm_fifo_18x1k.lpc
@@ -1,8 +1,8 @@
 [Device]
 Family=latticescm
-PartType=LFSCM3GA25EP1
-PartName=LFSCM3GA25EP1-5FF1020CES
-SpeedGrade=-5
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-7FF1020C
+SpeedGrade=7
 Package=FFBGA1020
 OperatingCondition=COM
 Status=P
@@ -11,13 +11,13 @@ Status=P
 VendorName=Lattice Semiconductor Corporation
 CoreType=LPM
 CoreStatus=Demo
-CoreName=FIFO_DC
-CoreRevision=4.2
+CoreName=FIFO
+CoreRevision=4.8
 ModuleName=lattice_scm_fifo_18x1k
-SourceFormat=Schematic/VHDL
+SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=02/08/2008
-Time=13:39:06
+Date=12/13/2010
+Time=11:46:24
 
 [Parameters]
 Verilog=0
@@ -27,22 +27,18 @@ Destination=Synplicity
 Expression=BusA(0 to 7)
 Order=Big Endian [MSB:LSB]
 IO=0
-FIFOImp=EBR Only
-RDepth=1024
-RWidth=18
-WDepth=1024
-WWidth=18
+FIFOImp=EBR Based
+Depth=1024
+Width=18
 regout=0
 CtrlByRdEn=0
-EmpFlg=1
-PeMode=Static - Single Threshold
+EmpFlg=0
+PeMode=Static - Dual Threshold
 PeAssert=10
 PeDeassert=12
-FullFlg=1
-PfMode=Static - Single Threshold
+FullFlg=0
+PfMode=Static - Dual Threshold
 PfAssert=508
 PfDeassert=506
-Reset=Sync
-RDataCount=0
-WDataCount=0
+RDataCount=1
 EnECC=0
diff --git a/lattice/scm/lattice_scm_fifo_18x1k.naf b/lattice/scm/lattice_scm_fifo_18x1k.naf
index 06ed646..230a6e0 100644
--- a/lattice/scm/lattice_scm_fifo_18x1k.naf
+++ b/lattice/scm/lattice_scm_fifo_18x1k.naf
@@ -16,12 +16,10 @@ Data[3]  i
 Data[2]  i
 Data[1]  i
 Data[0]  i
-WrClock  i
-RdClock  i
+Clock  i
 WrEn  i
 RdEn  i
 Reset  i
-RPReset  i
 Q[17]  o
 Q[16]  o
 Q[15]  o
@@ -40,7 +38,16 @@ Q[3]  o
 Q[2]  o
 Q[1]  o
 Q[0]  o
+WCNT[10]  o
+WCNT[9]  o
+WCNT[8]  o
+WCNT[7]  o
+WCNT[6]  o
+WCNT[5]  o
+WCNT[4]  o
+WCNT[3]  o
+WCNT[2]  o
+WCNT[1]  o
+WCNT[0]  o
 Empty  o
 Full  o
-AlmostEmpty  o
-AlmostFull  o
diff --git a/lattice/scm/lattice_scm_fifo_18x1k.srp b/lattice/scm/lattice_scm_fifo_18x1k.srp
index 9e7c3c0..85f93c8 100644
--- a/lattice/scm/lattice_scm_fifo_18x1k.srp
+++ b/lattice/scm/lattice_scm_fifo_18x1k.srp
@@ -1,19 +1,19 @@
-SCUBA, Version ispLever_v70_Prod_Build (55)
-Fri Feb  8 13:39:06 2008
+SCUBA, Version Diamond_1.1_Production (517)
+Mon Dec 13 11:46:24 2010
 
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
 Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.
+Copyright (c) 2002-2010 Lattice Semiconductor Corporation,  All rights reserved.
 
-    Issued command   : /opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -sync_reset -e 
+    Issued command   : /d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 1024 -width 18 -no_enable -pe -1 -pf -1 -fill -e 
     Circuit name     : lattice_scm_fifo_18x1k
-    Module type      : ebfifo
-    Module Version   : 4.2
+    Module type      : fifoblk
+    Module Version   : 4.8
     Ports            : 
-	Inputs       : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
-	Outputs      : Q[17:0], Empty, Full, AlmostEmpty, AlmostFull
+	Inputs       : Data[17:0], Clock, WrEn, RdEn, Reset
+	Outputs      : Q[17:0], WCNT[10:0], Empty, Full
     I/O buffer       : not inserted
     EDIF output      : suppressed
     VHDL output      : lattice_scm_fifo_18x1k.vhd
@@ -23,6 +23,19 @@ Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.
     Bus notation     : big endian
     Report output    : lattice_scm_fifo_18x1k.srp
     Element Usage    :
-       FIFO16KA : 1
+        ROM16X1 : 2
+           AND2 : 3
+           XOR2 : 1
+            INV : 4
+            CU2 : 12
+            CB2 : 6
+          AGEB2 : 6
+          ALEB2 : 6
+        FD1P3DX : 33
+        FD1S3BX : 1
+        FD1S3DX : 1
+        PDP16KA : 1
     Estimated Resource Usage:
+            LUT : 66
             EBR : 1
+            Reg : 35
diff --git a/lattice/scm/lattice_scm_fifo_18x1k.sym b/lattice/scm/lattice_scm_fifo_18x1k.sym
index 7e3e132..2d6c116 100644
Binary files a/lattice/scm/lattice_scm_fifo_18x1k.sym and b/lattice/scm/lattice_scm_fifo_18x1k.sym differ
diff --git a/lattice/scm/lattice_scm_fifo_18x1k.vhd b/lattice/scm/lattice_scm_fifo_18x1k.vhd
index 55b2747..18b9263 100644
--- a/lattice/scm/lattice_scm_fifo_18x1k.vhd
+++ b/lattice/scm/lattice_scm_fifo_18x1k.vhd
@@ -1,8 +1,8 @@
--- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
--- Module  Version: 4.2
---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -sync_reset -e 
+-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
+-- Module  Version: 4.8
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 1024 -width 18 -no_enable -pe -1 -pf -1 -fill -e 
 
--- Fri Feb  8 13:39:06 2008
+-- Mon Dec 13 11:46:24 2010
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -14,44 +14,196 @@ use SCM.COMPONENTS.all;
 entity lattice_scm_fifo_18x1k is
     port (
         Data: in  std_logic_vector(17 downto 0); 
-        WrClock: in  std_logic; 
-        RdClock: in  std_logic; 
+        Clock: in  std_logic; 
         WrEn: in  std_logic; 
         RdEn: in  std_logic; 
         Reset: in  std_logic; 
-        RPReset: in  std_logic; 
         Q: out  std_logic_vector(17 downto 0); 
+        WCNT: out  std_logic_vector(10 downto 0); 
         Empty: out  std_logic; 
-        Full: out  std_logic; 
-        AlmostEmpty: out  std_logic; 
-        AlmostFull: out  std_logic);
+        Full: out  std_logic);
 end lattice_scm_fifo_18x1k;
 
 architecture Structure of lattice_scm_fifo_18x1k is
 
     -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal rden_i_inv: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal co5: std_logic;
+    signal cnt_con: std_logic;
+    signal co4: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal co4_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal wren_i: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal co4_2: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_10: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal iwcount_10: std_logic;
+    signal co5_1: std_logic;
+    signal wcount_10: std_logic;
+    signal co4_3: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
     signal scuba_vhi: std_logic;
-    signal Empty_int: std_logic;
-    signal Full_int: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal co0_4: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal co1_4: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal co2_4: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal co3_4: std_logic;
+    signal ircount_10: std_logic;
+    signal co5_2: std_logic;
+    signal rcount_10: std_logic;
     signal scuba_vlo: std_logic;
+    signal co4_4: std_logic;
 
     -- local component declarations
+    component ROM16X1
+    -- synopsys translate_off
+        generic (initval : in String);
+    -- synopsys translate_on
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
     component VHI
         port (Z: out  std_logic);
     end component;
     component VLO
         port (Z: out  std_logic);
     end component;
-    component FIFO16KA
+    component CU2
+        port (CI: in  std_logic; PC1: in  std_logic; PC0: in  std_logic; 
+            CO: out  std_logic; NC1: out  std_logic; NC0: out  std_logic);
+    end component;
+    component CB2
+        port (CI: in  std_logic; PC1: in  std_logic; PC0: in  std_logic; 
+            CON: in  std_logic; CO: out  std_logic; NC1: out  std_logic; 
+            NC0: out  std_logic);
+    end component;
+    component AGEB2
+        port (A1: in  std_logic; A0: in  std_logic; B1: in  std_logic; 
+            B0: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component ALEB2
+        port (A1: in  std_logic; A0: in  std_logic; B1: in  std_logic; 
+            B0: in  std_logic; CI: in  std_logic; LE: out  std_logic);
+    end component;
+    component FD1P3DX
     -- synopsys translate_off
-        generic (FULLPOINTER1 : in std_logic_vector(14 downto 0); 
-                FULLPOINTER : in std_logic_vector(14 downto 0); 
-                AFPOINTER1 : in std_logic_vector(14 downto 0); 
-                AEPOINTER1 : in std_logic_vector(14 downto 0); 
-                AFPOINTER : in std_logic_vector(14 downto 0); 
-                AEPOINTER : in std_logic_vector(14 downto 0); 
-                CSDECODE_R : in std_logic_vector(1 downto 0); 
-                CSDECODE_W : in std_logic_vector(1 downto 0); 
+        generic (GSR : in String);
+    -- synopsys translate_on
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+    -- synopsys translate_off
+        generic (GSR : in String);
+    -- synopsys translate_on
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+    -- synopsys translate_off
+        generic (GSR : in String);
+    -- synopsys translate_on
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component PDP16KA
+    -- synopsys translate_off
+        generic (GSR : in String; 
+                CSDECODE_R : in std_logic_vector(2 downto 0); 
+                CSDECODE_W : in std_logic_vector(2 downto 0); 
                 RESETMODE : in String; REGMODE : in String; 
                 DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
     -- synopsys translate_on
@@ -71,11 +223,25 @@ architecture Structure of lattice_scm_fifo_18x1k is
             DI30: in  std_logic; DI31: in  std_logic; 
             DI32: in  std_logic; DI33: in  std_logic; 
             DI34: in  std_logic; DI35: in  std_logic; 
-            FULLI: in  std_logic; CSW0: in  std_logic; 
-            CSW1: in  std_logic; EMPTYI: in  std_logic; 
-            CSR0: in  std_logic; CSR1: in  std_logic; WE: in  std_logic; 
-            RE: in  std_logic; CLKW: in  std_logic; CLKR: in  std_logic; 
-            RST: in  std_logic; RPRST: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; ADW9: in  std_logic; 
+            ADW10: in  std_logic; ADW11: in  std_logic; 
+            ADW12: in  std_logic; ADW13: in  std_logic; 
+            CEW: in  std_logic; CLKW: in  std_logic; WE: in  std_logic; 
+            CSW0: in  std_logic; CSW1: in  std_logic; 
+            CSW2: in  std_logic; ADR0: in  std_logic; 
+            ADR1: in  std_logic; ADR2: in  std_logic; 
+            ADR3: in  std_logic; ADR4: in  std_logic; 
+            ADR5: in  std_logic; ADR6: in  std_logic; 
+            ADR7: in  std_logic; ADR8: in  std_logic; 
+            ADR9: in  std_logic; ADR10: in  std_logic; 
+            ADR11: in  std_logic; ADR12: in  std_logic; 
+            ADR13: in  std_logic; CER: in  std_logic; 
+            CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
             DO0: out  std_logic; DO1: out  std_logic; 
             DO2: out  std_logic; DO3: out  std_logic; 
             DO4: out  std_logic; DO5: out  std_logic; 
@@ -93,51 +259,111 @@ architecture Structure of lattice_scm_fifo_18x1k is
             DO28: out  std_logic; DO29: out  std_logic; 
             DO30: out  std_logic; DO31: out  std_logic; 
             DO32: out  std_logic; DO33: out  std_logic; 
-            DO34: out  std_logic; DO35: out  std_logic; 
-            EF: out  std_logic; AEF: out  std_logic; AFF: out  std_logic; 
-            FF: out  std_logic);
+            DO34: out  std_logic; DO35: out  std_logic);
     end component;
-    attribute FULLPOINTER1 : string; 
-    attribute FULLPOINTER : string; 
-    attribute AFPOINTER1 : string; 
-    attribute AFPOINTER : string; 
-    attribute AEPOINTER1 : string; 
-    attribute AEPOINTER : string; 
-    attribute RESETMODE : string; 
-    attribute REGMODE : string; 
+    attribute initval : string; 
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
     attribute CSDECODE_R : string; 
     attribute CSDECODE_W : string; 
+    attribute RESETMODE : string; 
+    attribute REGMODE : string; 
     attribute DATA_WIDTH_R : string; 
     attribute DATA_WIDTH_W : string; 
-    attribute FULLPOINTER1 of lattice_scm_fifo_18x1k_0_0 : label is "0b011111111100001";
-    attribute FULLPOINTER of lattice_scm_fifo_18x1k_0_0 : label is "0b011111111110001";
-    attribute AFPOINTER1 of lattice_scm_fifo_18x1k_0_0 : label is "0b001111110100001";
-    attribute AFPOINTER of lattice_scm_fifo_18x1k_0_0 : label is "0b001111110110001";
-    attribute AEPOINTER1 of lattice_scm_fifo_18x1k_0_0 : label is "0b000000010111111";
-    attribute AEPOINTER of lattice_scm_fifo_18x1k_0_0 : label is "0b000000010101111";
-    attribute RESETMODE of lattice_scm_fifo_18x1k_0_0 : label is "SYNC";
-    attribute REGMODE of lattice_scm_fifo_18x1k_0_0 : label is "NOREG";
-    attribute CSDECODE_R of lattice_scm_fifo_18x1k_0_0 : label is "0b11";
-    attribute CSDECODE_W of lattice_scm_fifo_18x1k_0_0 : label is "0b11";
-    attribute DATA_WIDTH_R of lattice_scm_fifo_18x1k_0_0 : label is "18";
-    attribute DATA_WIDTH_W of lattice_scm_fifo_18x1k_0_0 : label is "18";
+    attribute GSR : string; 
+    attribute initval of LUT4_1 : label is "0x3232";
+    attribute initval of LUT4_0 : label is "0x3232";
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_scm_fifo_18x1k.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000";
+    attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b000";
+    attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+    attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG";
+    attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "18";
+    attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "18";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
     attribute syn_keep : boolean;
 
 begin
     -- component instantiation statements
-    scuba_vhi_inst: VHI
-        port map (Z=>scuba_vhi);
+    AND2_t3: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
 
-    scuba_vlo_inst: VLO
-        port map (Z=>scuba_vlo);
+    INV_3: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t2: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_2: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    AND2_t1: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t0: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_1: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_0: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1
+        -- synopsys translate_off
+        generic map (initval=> "0x3232")
+        -- synopsys translate_on
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1
+        -- synopsys translate_off
+        generic map (initval=> "0x3232")
+        -- synopsys translate_on
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
 
-    lattice_scm_fifo_18x1k_0_0: FIFO16KA
+    pdp_ram_0_0_0: PDP16KA
         -- synopsys translate_off
-        generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001", 
-        AFPOINTER1=> "001111110100001", AFPOINTER=> "001111110110001", 
-        AEPOINTER1=> "000000010111111", AEPOINTER=> "000000010101111", 
-        RESETMODE=> "SYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", 
-        CSDECODE_W=> "11", DATA_WIDTH_R=>  18, DATA_WIDTH_W=>  18)
+        generic map (CSDECODE_R=> "000", CSDECODE_W=> "000", GSR=> "DISABLED", 
+        RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=>  18, 
+        DATA_WIDTH_W=>  18)
         -- synopsys translate_on
         port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
             DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
@@ -150,31 +376,429 @@ begin
             DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, 
             DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, 
             DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
-            FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, 
-            EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, 
-            WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, 
-            RPRST=>RPReset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), 
-            DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), 
-            DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), 
+            ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vlo, 
+            ADW3=>scuba_vlo, ADW4=>wcount_0, ADW5=>wcount_1, 
+            ADW6=>wcount_2, ADW7=>wcount_3, ADW8=>wcount_4, 
+            ADW9=>wcount_5, ADW10=>wcount_6, ADW11=>wcount_7, 
+            ADW12=>wcount_8, ADW13=>wcount_9, CEW=>wren_i, CLKW=>Clock, 
+            WE=>scuba_vhi, CSW0=>scuba_vlo, CSW1=>scuba_vlo, 
+            CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, 
+            ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>rcount_0, 
+            ADR5=>rcount_1, ADR6=>rcount_2, ADR7=>rcount_3, 
+            ADR8=>rcount_4, ADR9=>rcount_5, ADR10=>rcount_6, 
+            ADR11=>rcount_7, ADR12=>rcount_8, ADR13=>rcount_9, 
+            CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
+            CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), 
+            DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), 
+            DO8=>Q(8), DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), 
             DO13=>Q(13), DO14=>Q(14), DO15=>Q(15), DO16=>Q(16), 
             DO17=>Q(17), DO18=>open, DO19=>open, DO20=>open, DO21=>open, 
             DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open, 
             DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open, 
-            DO32=>open, DO33=>open, DO34=>open, DO35=>open, 
-            EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull, 
-            FF=>Full_int);
+            DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+    FF_34: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_33: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_32: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_31: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_30: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_29: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_28: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_27: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_26: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_25: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_24: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_23: FD1S3BX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_22: FD1S3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_21: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_0);
+
+    FF_20: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_19: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_18: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_17: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_16: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_15: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_14: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_13: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_12: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_11: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_10: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_0);
+
+    FF_9: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_8: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_7: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_6: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_5: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_4: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_3: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_2: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_1: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_0: FD1P3DX
+        -- synopsys translate_off
+        generic map (GSR=> "ENABLED")
+        -- synopsys translate_on
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    bdcnt_bctr_0: CB2
+        port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0, 
+            CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+    bdcnt_bctr_1: CB2
+        port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con, 
+            CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+    bdcnt_bctr_2: CB2
+        port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con, 
+            CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+    bdcnt_bctr_3: CB2
+        port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con, 
+            CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+    bdcnt_bctr_4: CB2
+        port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con, 
+            CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+    bdcnt_bctr_5: CB2
+        port map (CI=>co4, PC1=>scuba_vlo, PC0=>fcount_10, CON=>cnt_con, 
+            CO=>co5, NC1=>open, NC0=>ifcount_10);
+
+    e_cmp_0: ALEB2
+        port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i, 
+            CI=>scuba_vhi, LE=>co0_1);
+
+    e_cmp_1: ALEB2
+        port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo, 
+            B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+    e_cmp_2: ALEB2
+        port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo, 
+            B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+    e_cmp_3: ALEB2
+        port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo, 
+            B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+    e_cmp_4: ALEB2
+        port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo, 
+            B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+    e_cmp_5: ALEB2
+        port map (A1=>scuba_vlo, A0=>fcount_10, B1=>scuba_vlo, 
+            B0=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1);
+
+    g_cmp_0: AGEB2
+        port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i, 
+            CI=>scuba_vhi, GE=>co0_2);
+
+    g_cmp_1: AGEB2
+        port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i, 
+            CI=>co0_2, GE=>co1_2);
+
+    g_cmp_2: AGEB2
+        port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i, 
+            CI=>co1_2, GE=>co2_2);
+
+    g_cmp_3: AGEB2
+        port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i, 
+            CI=>co2_2, GE=>co3_2);
+
+    g_cmp_4: AGEB2
+        port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i, 
+            CI=>co3_2, GE=>co4_2);
+
+    g_cmp_5: AGEB2
+        port map (A1=>scuba_vlo, A0=>fcount_10, B1=>scuba_vlo, 
+            B0=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1);
+
+    w_ctr_0: CU2
+        port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3, 
+            NC1=>iwcount_1, NC0=>iwcount_0);
+
+    w_ctr_1: CU2
+        port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3, 
+            NC1=>iwcount_3, NC0=>iwcount_2);
+
+    w_ctr_2: CU2
+        port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3, 
+            NC1=>iwcount_5, NC0=>iwcount_4);
+
+    w_ctr_3: CU2
+        port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3, 
+            NC1=>iwcount_7, NC0=>iwcount_6);
+
+    w_ctr_4: CU2
+        port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3, 
+            NC1=>iwcount_9, NC0=>iwcount_8);
+
+    w_ctr_5: CU2
+        port map (CI=>co4_3, PC1=>scuba_vlo, PC0=>wcount_10, CO=>co5_1, 
+            NC1=>open, NC0=>iwcount_10);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    r_ctr_0: CU2
+        port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4, 
+            NC1=>ircount_1, NC0=>ircount_0);
+
+    r_ctr_1: CU2
+        port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4, 
+            NC1=>ircount_3, NC0=>ircount_2);
+
+    r_ctr_2: CU2
+        port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4, 
+            NC1=>ircount_5, NC0=>ircount_4);
+
+    r_ctr_3: CU2
+        port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4, 
+            NC1=>ircount_7, NC0=>ircount_6);
+
+    r_ctr_4: CU2
+        port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4, 
+            NC1=>ircount_9, NC0=>ircount_8);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    r_ctr_5: CU2
+        port map (CI=>co4_4, PC1=>scuba_vlo, PC0=>rcount_10, CO=>co5_2, 
+            NC1=>open, NC0=>ircount_10);
 
-    Empty <= Empty_int;
-    Full <= Full_int;
+    WCNT(0) <= fcount_0;
+    WCNT(1) <= fcount_1;
+    WCNT(2) <= fcount_2;
+    WCNT(3) <= fcount_3;
+    WCNT(4) <= fcount_4;
+    WCNT(5) <= fcount_5;
+    WCNT(6) <= fcount_6;
+    WCNT(7) <= fcount_7;
+    WCNT(8) <= fcount_8;
+    WCNT(9) <= fcount_9;
+    WCNT(10) <= fcount_10;
+    Empty <= empty_i;
+    Full <= full_i;
 end Structure;
 
 -- synopsys translate_off
 library SCM;
 configuration Structure_CON of lattice_scm_fifo_18x1k is
     for Structure
+        for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+        for all:AND2 use entity SCM.AND2(V); end for;
+        for all:XOR2 use entity SCM.XOR2(V); end for;
+        for all:INV use entity SCM.INV(V); end for;
         for all:VHI use entity SCM.VHI(V); end for;
         for all:VLO use entity SCM.VLO(V); end for;
-        for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+        for all:CU2 use entity SCM.CU2(V); end for;
+        for all:CB2 use entity SCM.CB2(V); end for;
+        for all:AGEB2 use entity SCM.AGEB2(V); end for;
+        for all:ALEB2 use entity SCM.ALEB2(V); end for;
+        for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+        for all:PDP16KA use entity SCM.PDP16KA(V); end for;
     end for;
 end Structure_CON;
 
diff --git a/lattice/scm/pll_in100_out100.ipx b/lattice/scm/pll_in100_out100.ipx
new file mode 100644
index 0000000..e33656c
--- /dev/null
+++ b/lattice/scm/pll_in100_out100.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in100_out100" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2010 12 10 17:18:20.414" version="5.2" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="pll_in100_out100.lpc" type="lpc" modified="2010 12 10 17:18:17.000"/>
+		<File name="pll_in100_out100.vhd" type="top_level_vhdl" modified="2010 12 10 17:18:17.000"/>
+		<File name="pll_in100_out100_tmpl.vhd" type="template_vhdl" modified="2010 12 10 17:18:18.000"/>
+  </Package>
+</DiamondModule>
diff --git a/lattice/scm/pll_in100_out100.lpc b/lattice/scm/pll_in100_out100.lpc
new file mode 100644
index 0000000..2848095
--- /dev/null
+++ b/lattice/scm/pll_in100_out100.lpc
@@ -0,0 +1,58 @@
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-6FF1020C
+SpeedGrade=6
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.2
+ModuleName=pll_in100_out100
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=12/10/2010
+Time=17:18:17
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+Clki_freq=100
+U_OFrq=100
+OP_Tol=0.0
+ClkOP_Freq= 100.000000
+U_SFrq=100
+OS_Tol=0.0
+ClkOS_Freq= 100.000000
+Phase=0
+FineDelay=0
+FeedbackClk=Internal
+Frequency=100
+enSpectrum=0
+smiport=0
+enRSTN=0
+Clki_boosting=DEL0
+Clkfb_boosting=DEL0
+Clki_fine=0
+Clkfb_fine=0
+enSpread=0
+modulation=1
+Desired=30
+Actual=30
+lock=Frequency
+enGSR=0
+VcoRate= 600.000000
+Bandwidth= 5.262395
+enHighBand=0
+enBypassP=0
+enBypassS=0
diff --git a/lattice/scm/pll_in100_out100.vhd b/lattice/scm/pll_in100_out100.vhd
new file mode 100644
index 0000000..6bcc495
--- /dev/null
+++ b/lattice/scm/pll_in100_out100.vhd
@@ -0,0 +1,168 @@
+-- VHDL netlist generated by SCUBA Diamond_1.1_Production (517)
+-- Module  Version: 5.2
+--/d/sugar/lattice/diamond/1.1/ispfpga/bin/lin/scuba -w -n pll_in100_out100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 100 -mfreq 100 -nfreq 100 -tap 0 -clkos_fdel 0 -fb 0 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e 
+
+-- Fri Dec 10 17:18:17 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity pll_in100_out100 is
+    generic (
+        SMI_OFFSET : in String := "0x410"
+    );
+    port (
+        clk: in  std_logic; 
+        clkop: out  std_logic; 
+        clkos: out  std_logic; 
+        lock: out  std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in100_out100 : entity is true;
+end pll_in100_out100;
+
+architecture Structure of pll_in100_out100 is
+
+    -- internal signal declarations
+    signal scuba_vlo: std_logic;
+    signal scuba_vhi: std_logic;
+    signal clkos_t: std_logic;
+    signal fb: std_logic;
+    signal clkop_t: std_logic;
+    signal clk_t: std_logic;
+
+    attribute module_type : string;
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component EHXPLLA
+        generic (SMI_OFFSET : in String
+                -- synopsys translate_off
+                ; GSR : in String; CLKOS_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; CLKOS_FDEL : in Integer; 
+                CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer; 
+                CLKOS_MODE : in String; CLKOP_MODE : in String; 
+                PHASEADJ : in Integer; CLKOS_VCODEL : in Integer
+                -- synopsys translate_on
+                );
+        port (SMIADDR9: in  std_logic; SMIADDR8: in  std_logic; 
+            SMIADDR7: in  std_logic; SMIADDR6: in  std_logic; 
+            SMIADDR5: in  std_logic; SMIADDR4: in  std_logic; 
+            SMIADDR3: in  std_logic; SMIADDR2: in  std_logic; 
+            SMIADDR1: in  std_logic; SMIADDR0: in  std_logic; 
+            SMIRD: in  std_logic; SMIWR: in  std_logic; 
+            SMICLK: in  std_logic; SMIWDATA: in  std_logic; 
+            SMIRSTN: in  std_logic; CLKI: in  std_logic; 
+            CLKFB: in  std_logic; RSTN: in  std_logic; 
+            CLKOS: out  std_logic; CLKOP: out  std_logic; 
+            LOCK: out  std_logic; CLKINTFB: out  std_logic; 
+            SMIRDATA: out  std_logic);
+    end component;
+    attribute module_type of EHXPLLA : component is "EHXPLLA";
+    attribute ip_type : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute VCO_LOWERFREQ : string; 
+    attribute GMCFREQSEL : string; 
+    attribute GSR : string; 
+    attribute SPREAD_DIV2 : string; 
+    attribute SPREAD_DIV1 : string; 
+    attribute SPREAD_DRIFT : string; 
+    attribute SPREAD : string; 
+    attribute CLKFB_FDEL : string; 
+    attribute CLKI_FDEL : string; 
+    attribute CLKFB_PDEL : string; 
+    attribute CLKI_PDEL : string; 
+    attribute LF_RESISTOR : string; 
+    attribute LF_IX5UA : string; 
+    attribute CLKOS_FDEL : string; 
+    attribute CLKOS_VCODEL : string; 
+    attribute PHASEADJ : string; 
+    attribute CLKOS_MODE : string; 
+    attribute CLKOP_MODE : string; 
+    attribute CLKOS_DIV : string; 
+    attribute CLKOP_DIV : string; 
+    attribute CLKFB_DIV : string; 
+    attribute CLKI_DIV : string; 
+    attribute ip_type of pll_in100_out100_0_0 : label is "EHXPLLA";
+    attribute FREQUENCY_PIN_CLKOS of pll_in100_out100_0_0 : label is "100.000000";
+    attribute FREQUENCY_PIN_CLKOP of pll_in100_out100_0_0 : label is "100.000000";
+    attribute FREQUENCY_PIN_CLKI of pll_in100_out100_0_0 : label is "100.000000";
+    attribute VCO_LOWERFREQ of pll_in100_out100_0_0 : label is "DISABLED";
+    attribute GMCFREQSEL of pll_in100_out100_0_0 : label is "HIGH";
+    attribute GSR of pll_in100_out100_0_0 : label is "ENABLED";
+    attribute SPREAD_DIV2 of pll_in100_out100_0_0 : label is "2";
+    attribute SPREAD_DIV1 of pll_in100_out100_0_0 : label is "2";
+    attribute SPREAD_DRIFT of pll_in100_out100_0_0 : label is "1";
+    attribute SPREAD of pll_in100_out100_0_0 : label is "DISABLED";
+    attribute CLKFB_FDEL of pll_in100_out100_0_0 : label is "0";
+    attribute CLKI_FDEL of pll_in100_out100_0_0 : label is "0";
+    attribute CLKFB_PDEL of pll_in100_out100_0_0 : label is "DEL0";
+    attribute CLKI_PDEL of pll_in100_out100_0_0 : label is "DEL0";
+    attribute LF_RESISTOR of pll_in100_out100_0_0 : label is "0b111010";
+    attribute LF_IX5UA of pll_in100_out100_0_0 : label is "31";
+    attribute CLKOS_FDEL of pll_in100_out100_0_0 : label is "0";
+    attribute CLKOS_VCODEL of pll_in100_out100_0_0 : label is "0";
+    attribute PHASEADJ of pll_in100_out100_0_0 : label is "0";
+    attribute CLKOS_MODE of pll_in100_out100_0_0 : label is "DIV";
+    attribute CLKOP_MODE of pll_in100_out100_0_0 : label is "DIV";
+    attribute CLKOS_DIV of pll_in100_out100_0_0 : label is "6";
+    attribute CLKOP_DIV of pll_in100_out100_0_0 : label is "6";
+    attribute CLKFB_DIV of pll_in100_out100_0_0 : label is "6";
+    attribute CLKI_DIV of pll_in100_out100_0_0 : label is "1";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    pll_in100_out100_0_0: EHXPLLA
+        generic map (SMI_OFFSET=>  SMI_OFFSET
+        -- synopsys translate_off
+                     , GSR=> "ENABLED", CLKFB_FDEL=>  0, CLKI_FDEL=>  0, 
+        CLKOS_FDEL=>  0, CLKOS_VCODEL=>  0, PHASEADJ=>  0, CLKOS_MODE=> "DIV", 
+        CLKOP_MODE=> "DIV", CLKOS_DIV=>  6, CLKOP_DIV=>  6, CLKFB_DIV=>  6, 
+        CLKI_DIV=>  1
+        -- synopsys translate_on
+                     )
+        port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo, 
+            SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo, 
+            SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo, 
+            SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo, 
+            SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo, 
+            SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo, 
+            SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>fb, RSTN=>scuba_vhi, 
+            CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, CLKINTFB=>fb, 
+            SMIRDATA=>open);
+
+    clkos <= clkos_t;
+    clkop <= clkop_t;
+    clk_t <= clk;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of pll_in100_out100 is
+    for Structure
+        for all:VHI use entity SCM.VHI(V); end for;
+        for all:VLO use entity SCM.VLO(V); end for;
+        for all:EHXPLLA use entity SCM.EHXPLLA(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/lattice/scm/tb_lattice_scm_fifo_18x1k_tmpl.vhd b/lattice/scm/tb_lattice_scm_fifo_18x1k_tmpl.vhd
index c88111c..ca5e3a8 100644
--- a/lattice/scm/tb_lattice_scm_fifo_18x1k_tmpl.vhd
+++ b/lattice/scm/tb_lattice_scm_fifo_18x1k_tmpl.vhd
@@ -1,4 +1,4 @@
--- VHDL testbench template generated by SCUBA ispLever_v70_Prod_Build (55)
+-- VHDL testbench template generated by SCUBA Diamond_1.1_Production (517)
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.std_logic_unsigned.all;
@@ -11,50 +11,40 @@ architecture test of tb is
 
     component lattice_scm_fifo_18x1k
         port (Data : in std_logic_vector(17 downto 0); 
-        WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; 
-        RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; 
-        Q : out std_logic_vector(17 downto 0); Empty: out std_logic; 
-        Full: out std_logic; AlmostEmpty: out std_logic; 
-        AlmostFull: out std_logic
+        Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; 
+        Reset: in std_logic; Q : out std_logic_vector(17 downto 0); 
+        WCNT : out std_logic_vector(10 downto 0); Empty: out std_logic; 
+        Full: out std_logic
     );
     end component;
 
     signal Data : std_logic_vector(17 downto 0) := (others => '0');
-    signal WrClock: std_logic := '0';
-    signal RdClock: std_logic := '0';
+    signal Clock: std_logic := '0';
     signal WrEn: std_logic := '0';
     signal RdEn: std_logic := '0';
     signal Reset: std_logic := '0';
-    signal RPReset: std_logic := '0';
     signal Q : std_logic_vector(17 downto 0);
+    signal WCNT : std_logic_vector(10 downto 0);
     signal Empty: std_logic;
     signal Full: std_logic;
-    signal AlmostEmpty: std_logic;
-    signal AlmostFull: std_logic;
 begin
     u1 : lattice_scm_fifo_18x1k
-        port map (Data => Data, WrClock => WrClock, RdClock => RdClock, 
-            WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, 
-            Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty, 
-            AlmostFull => AlmostFull
+        port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn, 
+            Reset => Reset, Q => Q, WCNT => WCNT, Empty => Empty, Full => Full
         );
 
     process
 
     begin
       Data <= (others => '0') ;
-      wait for 100 ns;
-      wait until Reset = '0';
-      for i in 0 to 1027 loop
-        wait until WrClock'event and WrClock = '1';
+      for i in 0 to 1028 loop
+        wait until Clock'event and Clock = '1';
         Data <= Data + '1' after 1 ns;
       end loop;
       wait;
     end process;
 
-    WrClock <= not WrClock after 5.00 ns;
-
-    RdClock <= not RdClock after 5.00 ns;
+    Clock <= not Clock after 5.00 ns;
 
     process
 
@@ -62,8 +52,8 @@ begin
       WrEn <= '0' ;
       wait for 100 ns;
       wait until Reset = '0';
-      for i in 0 to 1027 loop
-        wait until WrClock'event and WrClock = '1';
+      for i in 0 to 1028 loop
+        wait until Clock'event and Clock = '1';
         WrEn <= '1' after 1 ns;
       end loop;
       WrEn <= '0' ;
@@ -77,8 +67,8 @@ begin
       wait until Reset = '0';
       wait until WrEn = '1';
       wait until WrEn = '0';
-      for i in 0 to 1027 loop
-        wait until RdClock'event and RdClock = '1';
+      for i in 0 to 1026 loop
+        wait until Clock'event and Clock = '1';
         RdEn <= '1' after 1 ns;
       end loop;
       RdEn <= '0' ;
@@ -94,13 +84,4 @@ begin
       wait;
     end process;
 
-    process
-
-    begin
-      RPReset <= '1' ;
-      wait for 100 ns;
-      RPReset <= '0' ;
-      wait;
-    end process;
-
 end architecture test;
diff --git a/lattice/scm/trb_net16_fifo_arch.vhd b/lattice/scm/trb_net16_fifo_arch.vhd
index 37b4332..ded051e 100644
--- a/lattice/scm/trb_net16_fifo_arch.vhd
+++ b/lattice/scm/trb_net16_fifo_arch.vhd
@@ -7,7 +7,8 @@ use work.trb_net_std.all;
 
 entity trb_net16_fifo is
     generic (
-      USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
+      USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
+			USE_DATA_COUNT   : integer range 0 to 1 := c_NO;			
       DEPTH      : integer := 6       -- Depth of the FIFO, 2^(n+1) 64Bit packets
       );
     port (
@@ -19,7 +20,8 @@ entity trb_net16_fifo is
       WRITE_ENABLE_IN : in  std_logic;
       DATA_OUT        : out std_logic_vector(15 downto 0);  -- Output data
       PACKET_NUM_OUT  : out std_logic_vector(1 downto 0);  -- Input data
-      READ_ENABLE_IN  : in  std_logic;
+      READ_ENABLE_IN  : in  std_logic;
+			DATA_COUNT_OUT  : out std_logic_vector(10 downto 0);			
       FULL_OUT        : out std_logic;    -- Full Flag
       EMPTY_OUT       : out std_logic
       );
@@ -28,18 +30,15 @@ end entity;
 architecture arch_trb_net16_fifo of trb_net16_fifo is
 component lattice_scm_fifo_18x1k is
     port (
-        Data: in  std_logic_vector(17 downto 0);
-        WrClock: in  std_logic;
-        RdClock: in  std_logic;
-        WrEn: in  std_logic;
-        RdEn: in  std_logic;
-        Reset: in  std_logic;
-        RPReset: in  std_logic;
-        Q: out  std_logic_vector(17 downto 0);
-        Empty: out  std_logic;
-        Full: out  std_logic;
-        AlmostEmpty: out  std_logic;
-        AlmostFull: out  std_logic);
+        Data: in  std_logic_vector(17 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        Q: out  std_logic_vector(17 downto 0); 
+        WCNT: out  std_logic_vector(10 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
 end component;
 
 
@@ -98,13 +97,12 @@ begin
     fifo:lattice_scm_fifo_18x1k
       port map (
         Data     => din,
-        WrClock  => CLK,
-        RdClock  => CLK,
+        Clock    => CLK,
         WrEn     => WRITE_ENABLE_IN,
         RdEn     => READ_ENABLE_IN,
         Reset    => RESET,
-        RPReset  => RESET,
-        Q        => dout,
+        Q        => dout,
+				WCNT     => DATA_COUNT_OUT,
         Empty    => EMPTY_OUT,
         Full     => FULL_OUT
         );
diff --git a/media_interfaces/scm_sfp/serdes_100_ext.ipx b/media_interfaces/scm_sfp/serdes_100_ext.ipx
new file mode 100644
index 0000000..7478d2e
--- /dev/null
+++ b/media_interfaces/scm_sfp/serdes_100_ext.ipx
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_100_ext" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2010 12 07 15:33:19.160" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="serdes_100_ext.lpc" type="lpc" modified="2010 12 07 15:33:16.000"/>
+		<File name="serdes_100_ext.pp" type="pp" modified="2010 12 07 15:33:16.000"/>
+		<File name="serdes_100_ext.sym" type="sym" modified="2010 12 07 15:33:16.000"/>
+		<File name="serdes_100_ext.tft" type="tft" modified="2010 12 07 15:33:16.000"/>
+		<File name="serdes_100_ext.txt" type="pcs_module" modified="2010 12 07 15:33:16.000"/>
+		<File name="serdes_100_ext.vhd" type="top_level_vhdl" modified="2010 12 07 15:33:16.000"/>
+  </Package>
+</DiamondModule>
diff --git a/media_interfaces/scm_sfp/serdes_100_ext.lpc b/media_interfaces/scm_sfp/serdes_100_ext.lpc
new file mode 100644
index 0000000..71f1381
--- /dev/null
+++ b/media_interfaces/scm_sfp/serdes_100_ext.lpc
@@ -0,0 +1,61 @@
+[Device]
+Family=latticescm
+PartType=LFSCM3GA25EP1
+PartName=LFSCM3GA25EP1-7FF1020C
+SpeedGrade=7
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.1
+ModuleName=serdes_100_ext
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=12/07/2010
+Time=15:33:16
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+QuadMode=Generic 8b10b
+enChannel0=1
+enChannel1=0
+enChannel2=0
+enChannel3=0
+enAlign0=0
+enAlign1=0
+enAlign2=0
+enControlPorts=1
+enSystemBus=0
+en10gLsm=0
+ClkSelect=Dedicated CML Transmit/Receive Reference Clock
+BitClkRate=2
+RefClkMult=20X
+RefClkRate=100
+BusWidth=16
+IntClkRate=100
+AmpBoost=Disabled
+Bit1=0
+Word1=FF
+Bit2=0
+Word2=7C
+Bit3=0
+Word3=7C
+enQuad=0
+QuadGroup=Group 0
+
+[FilesGenerated]
+serdes_100_ext.pp=pp
+serdes_100_ext.tft=tft
+serdes_100_ext.txt=pcs_module
+serdes_100_ext.sym=sym
diff --git a/media_interfaces/scm_sfp/serdes_100_ext.txt b/media_interfaces/scm_sfp/serdes_100_ext.txt
new file mode 100644
index 0000000..33022e5
--- /dev/null
+++ b/media_interfaces/scm_sfp/serdes_100_ext.txt
@@ -0,0 +1,76 @@
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCS quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCS quad to the final design requirements.
+# channel_0 is in "8b10b" mode
+# channel_1 is in "Disabled" mode
+# channel_2 is in "Disabled" mode
+# channel_3 is in "Disabled" mode
+
+ch0  13 03  # Powerup Channel 0 TX/RX
+ch0  00 01  # link state machine enabled
+quad 00 00  # some standard settings?
+quad 01 E4  # RX clock select
+quad 28 40  # Reference clock multiplier
+quad 29 01  # JM101203 core clock as reference # set to 01
+#quad 30 04  # JM101203 TX sync enable   #check these settings!
+quad 02 00  # ref_pclk source is ch0, rxa_pclk is ch0, rxb_pclk is ch0
+quad 04 00  # MCA enable 4 channels
+
+#Here default values are used by SM
+quad 14 FF  # Word Alignment Mask [7:0]
+quad 15 83  # +ve K [7:0] -> COMMA_A = 11_0000_0101 - its inverted (see register convention in datasheet)!
+quad 16 7c  # -ve K [7:0] -> COMMA_B = 00_1111_1010 - its inverted !
+quad 17 36  # upper bits of CA,CB,CM
+
+
+quad 0D 97  # Watermark level on CTC: 9 high, 7 low
+quad 0E 08  # JM101203 was 0B # insertion/deletion control of CTC: two char matching
+quad 11 BC  # /I2/ pattern for CTC match (K28.5)
+quad 12 50  # (D16.2)
+quad 13 04  # (use comma)
+
+quad 19 8C  # Disable word_align_en port, FPGA bus width is 16-bit/20-bit
+ch0  14 90  # 16% pre-emphasis
+ch0  15 10  # JM101203 was 10 # +6dB equalization
+
+# These lines must appear last in the autoconfig file.  These lines apply the correct
+# reset sequence to the PCS block upon bitstream configuration
+quad 41 00  # de-assert serdes_rst
+quad 40 ff  # assert datapath reset for all channels
+quad 40 00  # de-assert datapath reset for all channels
+
+
+
+# Original file
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCS quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCS quad to the final design requirements.
+# channel_0 is in "8b10b" mode
+# channel_1 is in "Disabled" mode
+# channel_2 is in "Disabled" mode
+# channel_3 is in "Disabled" mode
+# ch0 13 03  # Powerup Channel
+# ch0 00 00
+# quad 00 00
+# quad 01 E4
+# quad 28 40  # Reference clock multiplier
+# quad 29 01  # set to 01
+# quad 02 00  # ref_pclk source is ch0
+# quad 04 00  # MCA enable 4 channels
+#
+# quad 18 10  # 8b10b Mode
+# # quad 14 7F  # Word Alignment Mask
+# # quad 15 03  # +ve K
+# # quad 16 7C  # -ve K
+# quad 19 8C  # Enable word_align_en port, FPGA bus width is 16-bit/20-bit
+# ch0 14 90  # 16% pre-emphasis
+# ch0 15 10  # +6dB equalization
+#
+# # These lines must appear last in the autoconfig file.  These lines apply the correct
+# # reset sequence to the PCS block upon bitstream configuration
+# quad 41 00  # de-assert serdes_rst
+# quad 40 ff  # assert datapath reset for all channels
+# quad 40 00  # de-assert datapath reset for all channels
diff --git a/media_interfaces/scm_sfp/serdes_100_ext.vhd b/media_interfaces/scm_sfp/serdes_100_ext.vhd
new file mode 100644
index 0000000..b92eed8
--- /dev/null
+++ b/media_interfaces/scm_sfp/serdes_100_ext.vhd
@@ -0,0 +1,2392 @@
+
+
+-- channel_0 is in "8b10b" mode
+-- channel_1 is in "Disabled" mode
+-- channel_2 is in "Disabled" mode
+-- channel_3 is in "Disabled" mode
+
+--synopsys translate_off
+
+library pcsa_work;
+use pcsa_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSA is
+GENERIC(
+  CONFIG_FILE : String  := "serdes_100_ext.txt"
+  );
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+
+end PCSA;
+
+architecture PCSA_arch of PCSA is
+
+component PCSA_sim
+GENERIC(
+  CONFIG_FILE : String
+  );
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+end component;
+
+begin
+
+PCSA_sim_inst : PCSA_sim 
+generic map (
+  CONFIG_FILE => CONFIG_FILE)
+port map (
+  HDINP0 => HDINP0,
+  HDINN0 => HDINN0,
+  HDINP1 => HDINP1,
+  HDINN1 => HDINN1,
+  HDINP2 => HDINP2,
+  HDINN2 => HDINN2,
+  HDINP3 => HDINP3,
+  HDINN3 => HDINN3,
+  HDOUTP0 => HDOUTP0,
+  HDOUTN0 => HDOUTN0,
+  HDOUTP1 => HDOUTP1,
+  HDOUTN1 => HDOUTN1,
+  HDOUTP2 => HDOUTP2,
+  HDOUTN2 => HDOUTN2,
+  HDOUTP3 => HDOUTP3,
+  HDOUTN3 => HDOUTN3,
+  REFCLKP => REFCLKP,
+  REFCLKN => REFCLKN,
+  RXREFCLKP => RXREFCLKP,
+  RXREFCLKN => RXREFCLKN,
+  FFC_QUAD_RST => FFC_QUAD_RST,
+  FFC_MACRO_RST => FFC_MACRO_RST,
+  FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0,
+  FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1,
+  FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2,
+  FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3,
+  FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0,
+  FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1,
+  FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2,
+  FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3,
+  FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0,
+  FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1,
+  FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2,
+  FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3,
+  FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+  FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+  FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+  FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+  FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+  FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+  FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+  FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+  FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+  FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+  FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+  FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+  FFC_PCIE_TX_0 => FFC_PCIE_TX_0,
+  FFC_PCIE_TX_1 => FFC_PCIE_TX_1,
+  FFC_PCIE_TX_2 => FFC_PCIE_TX_2,
+  FFC_PCIE_TX_3 => FFC_PCIE_TX_3,
+  FFC_PCIE_RX_0 => FFC_PCIE_RX_0,
+  FFC_PCIE_RX_1 => FFC_PCIE_RX_1,
+  FFC_PCIE_RX_2 => FFC_PCIE_RX_2,
+  FFC_PCIE_RX_3 => FFC_PCIE_RX_3,
+  FFC_SD_0 => FFC_SD_0,
+  FFC_SD_1 => FFC_SD_1,
+  FFC_SD_2 => FFC_SD_2,
+  FFC_SD_3 => FFC_SD_3,
+  FFC_EN_CGA_0 => FFC_EN_CGA_0,
+  FFC_EN_CGA_1 => FFC_EN_CGA_1,
+  FFC_EN_CGA_2 => FFC_EN_CGA_2,
+  FFC_EN_CGA_3 => FFC_EN_CGA_3,
+  FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0,
+  FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1,
+  FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2,
+  FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3,
+  FFC_AB_RESET => FFC_AB_RESET,
+  FFC_CD_RESET => FFC_CD_RESET,
+  FFS_LS_STATUS_0 => FFS_LS_STATUS_0,
+  FFS_LS_STATUS_1 => FFS_LS_STATUS_1,
+  FFS_LS_STATUS_2 => FFS_LS_STATUS_2,
+  FFS_LS_STATUS_3 => FFS_LS_STATUS_3,
+  FFS_AB_STATUS => FFS_AB_STATUS,
+  FFS_CD_STATUS => FFS_CD_STATUS,
+  FFS_AB_ALIGNED => FFS_AB_ALIGNED,
+  FFS_CD_ALIGNED => FFS_CD_ALIGNED,
+  FFS_AB_FAILED => FFS_AB_FAILED,
+  FFS_CD_FAILED => FFS_CD_FAILED,
+  FFS_RLOS_LO0 => FFS_RLOS_LO0,
+  FFS_RLOS_LO1 => FFS_RLOS_LO1,
+  FFS_RLOS_LO2 => FFS_RLOS_LO2,
+  FFS_RLOS_LO3 => FFS_RLOS_LO3,
+  FFC_FB_LB_0 => FFC_FB_LB_0,
+  FFC_FB_LB_1 => FFC_FB_LB_1,
+  FFC_FB_LB_2 => FFC_FB_LB_2,
+  FFC_FB_LB_3 => FFC_FB_LB_3,
+  FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+  FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+  FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+  FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+  FFS_CC_ORUN_0 => FFS_CC_ORUN_0,
+  FFS_CC_ORUN_1 => FFS_CC_ORUN_1,
+  FFS_CC_ORUN_2 => FFS_CC_ORUN_2,
+  FFS_CC_ORUN_3 => FFS_CC_ORUN_3,
+  FFS_CC_URUN_0 => FFS_CC_URUN_0,
+  FFS_CC_URUN_1 => FFS_CC_URUN_1,
+  FFS_CC_URUN_2 => FFS_CC_URUN_2,
+  FFS_CC_URUN_3 => FFS_CC_URUN_3,
+  FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+  FFC_CK_CORE_RX => FFC_CK_CORE_RX,
+  BS4PAD_0 => BS4PAD_0,
+  BS4PAD_1 => BS4PAD_1,
+  BS4PAD_2 => BS4PAD_2,
+  BS4PAD_3 => BS4PAD_3,
+  RDATAO_7 => RDATAO_7,
+  RDATAO_6 => RDATAO_6,
+  RDATAO_5 => RDATAO_5,
+  RDATAO_4 => RDATAO_4,
+  RDATAO_3 => RDATAO_3,
+  RDATAO_2 => RDATAO_2,
+  RDATAO_1 => RDATAO_1,
+  RDATAO_0 => RDATAO_0,
+  INTO => INTO,
+  ADDRI_7 => ADDRI_7,
+  ADDRI_6 => ADDRI_6,
+  ADDRI_5 => ADDRI_5,
+  ADDRI_4 => ADDRI_4,
+  ADDRI_3 => ADDRI_3,
+  ADDRI_2 => ADDRI_2,
+  ADDRI_1 => ADDRI_1,
+  ADDRI_0 => ADDRI_0,
+  WDATAI_7 => WDATAI_7,
+  WDATAI_6 => WDATAI_6,
+  WDATAI_5 => WDATAI_5,
+  WDATAI_4 => WDATAI_4,
+  WDATAI_3 => WDATAI_3,
+  WDATAI_2 => WDATAI_2,
+  WDATAI_1 => WDATAI_1,
+  WDATAI_0 => WDATAI_0,
+  RDI => RDI,
+  WSTBI => WSTBI,
+  CS_CHIF_0 => CS_CHIF_0,
+  CS_CHIF_1 => CS_CHIF_1,
+  CS_CHIF_2 => CS_CHIF_2,
+  CS_CHIF_3 => CS_CHIF_3,
+  CS_QIF => CS_QIF,
+  QUAD_ID_1 => QUAD_ID_1,
+  QUAD_ID_0 => QUAD_ID_0,
+  FF_SYSCLK_P1 => FF_SYSCLK_P1,
+  FF_SYSCLK0 => FF_SYSCLK0,
+  FF_SYSCLK1 => FF_SYSCLK1,
+  FF_SYSCLK2 => FF_SYSCLK2,
+  FF_SYSCLK3 => FF_SYSCLK3,
+  FF_RXCLK_P1 => FF_RXCLK_P1,
+  FF_RXCLK_P2 => FF_RXCLK_P2,
+  FF_RXCLK0 => FF_RXCLK0,
+  FF_RXCLK1 => FF_RXCLK1,
+  FF_RXCLK2 => FF_RXCLK2,
+  FF_RXCLK3 => FF_RXCLK3,
+  QUAD_CLK => QUAD_CLK,
+  GRP_CLK_P1_3 => GRP_CLK_P1_3,
+  GRP_CLK_P1_2 => GRP_CLK_P1_2,
+  GRP_CLK_P1_1 => GRP_CLK_P1_1,
+  GRP_CLK_P1_0 => GRP_CLK_P1_0,
+  GRP_CLK_P2_3 => GRP_CLK_P2_3,
+  GRP_CLK_P2_2 => GRP_CLK_P2_2,
+  GRP_CLK_P2_1 => GRP_CLK_P2_1,
+  GRP_CLK_P2_0 => GRP_CLK_P2_0,
+  GRP_START_3 => GRP_START_3,
+  GRP_START_2 => GRP_START_2,
+  GRP_START_1 => GRP_START_1,
+  GRP_START_0 => GRP_START_0,
+  GRP_DONE_3 => GRP_DONE_3,
+  GRP_DONE_2 => GRP_DONE_2,
+  GRP_DONE_1 => GRP_DONE_1,
+  GRP_DONE_0 => GRP_DONE_0,
+  GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3,
+  GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2,
+  GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1,
+  GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0,
+  IQA_START_LS => IQA_START_LS,
+  IQA_DONE_LS => IQA_DONE_LS,
+  IQA_AND_FP1_LS => IQA_AND_FP1_LS,
+  IQA_AND_FP0_LS => IQA_AND_FP0_LS,
+  IQA_OR_FP1_LS => IQA_OR_FP1_LS,
+  IQA_OR_FP0_LS => IQA_OR_FP0_LS,
+  IQA_RST_N => IQA_RST_N,
+  FF_TCLK0 => FF_TCLK0,
+  FF_TCLK1 => FF_TCLK1,
+  FF_TCLK2 => FF_TCLK2,
+  FF_TCLK3 => FF_TCLK3,
+  FF_RCLK0 => FF_RCLK0,
+  FF_RCLK1 => FF_RCLK1,
+  FF_RCLK2 => FF_RCLK2,
+  FF_RCLK3 => FF_RCLK3,
+  TCK_FMACP => TCK_FMACP,
+  FF_TXD_0_23 => FF_TXD_0_23,
+  FF_TXD_0_22 => FF_TXD_0_22,
+  FF_TXD_0_21 => FF_TXD_0_21,
+  FF_TXD_0_20 => FF_TXD_0_20,
+  FF_TXD_0_19 => FF_TXD_0_19,
+  FF_TXD_0_18 => FF_TXD_0_18,
+  FF_TXD_0_17 => FF_TXD_0_17,
+  FF_TXD_0_16 => FF_TXD_0_16,
+  FF_TXD_0_15 => FF_TXD_0_15,
+  FF_TXD_0_14 => FF_TXD_0_14,
+  FF_TXD_0_13 => FF_TXD_0_13,
+  FF_TXD_0_12 => FF_TXD_0_12,
+  FF_TXD_0_11 => FF_TXD_0_11,
+  FF_TXD_0_10 => FF_TXD_0_10,
+  FF_TXD_0_9 => FF_TXD_0_9,
+  FF_TXD_0_8 => FF_TXD_0_8,
+  FF_TXD_0_7 => FF_TXD_0_7,
+  FF_TXD_0_6 => FF_TXD_0_6,
+  FF_TXD_0_5 => FF_TXD_0_5,
+  FF_TXD_0_4 => FF_TXD_0_4,
+  FF_TXD_0_3 => FF_TXD_0_3,
+  FF_TXD_0_2 => FF_TXD_0_2,
+  FF_TXD_0_1 => FF_TXD_0_1,
+  FF_TXD_0_0 => FF_TXD_0_0,
+  FB_RXD_0_23 => FB_RXD_0_23,
+  FB_RXD_0_22 => FB_RXD_0_22,
+  FB_RXD_0_21 => FB_RXD_0_21,
+  FB_RXD_0_20 => FB_RXD_0_20,
+  FB_RXD_0_19 => FB_RXD_0_19,
+  FB_RXD_0_18 => FB_RXD_0_18,
+  FB_RXD_0_17 => FB_RXD_0_17,
+  FB_RXD_0_16 => FB_RXD_0_16,
+  FB_RXD_0_15 => FB_RXD_0_15,
+  FB_RXD_0_14 => FB_RXD_0_14,
+  FB_RXD_0_13 => FB_RXD_0_13,
+  FB_RXD_0_12 => FB_RXD_0_12,
+  FB_RXD_0_11 => FB_RXD_0_11,
+  FB_RXD_0_10 => FB_RXD_0_10,
+  FB_RXD_0_9 => FB_RXD_0_9,
+  FB_RXD_0_8 => FB_RXD_0_8,
+  FB_RXD_0_7 => FB_RXD_0_7,
+  FB_RXD_0_6 => FB_RXD_0_6,
+  FB_RXD_0_5 => FB_RXD_0_5,
+  FB_RXD_0_4 => FB_RXD_0_4,
+  FB_RXD_0_3 => FB_RXD_0_3,
+  FB_RXD_0_2 => FB_RXD_0_2,
+  FB_RXD_0_1 => FB_RXD_0_1,
+  FB_RXD_0_0 => FB_RXD_0_0,
+  FF_TXD_1_23 => FF_TXD_1_23,
+  FF_TXD_1_22 => FF_TXD_1_22,
+  FF_TXD_1_21 => FF_TXD_1_21,
+  FF_TXD_1_20 => FF_TXD_1_20,
+  FF_TXD_1_19 => FF_TXD_1_19,
+  FF_TXD_1_18 => FF_TXD_1_18,
+  FF_TXD_1_17 => FF_TXD_1_17,
+  FF_TXD_1_16 => FF_TXD_1_16,
+  FF_TXD_1_15 => FF_TXD_1_15,
+  FF_TXD_1_14 => FF_TXD_1_14,
+  FF_TXD_1_13 => FF_TXD_1_13,
+  FF_TXD_1_12 => FF_TXD_1_12,
+  FF_TXD_1_11 => FF_TXD_1_11,
+  FF_TXD_1_10 => FF_TXD_1_10,
+  FF_TXD_1_9 => FF_TXD_1_9,
+  FF_TXD_1_8 => FF_TXD_1_8,
+  FF_TXD_1_7 => FF_TXD_1_7,
+  FF_TXD_1_6 => FF_TXD_1_6,
+  FF_TXD_1_5 => FF_TXD_1_5,
+  FF_TXD_1_4 => FF_TXD_1_4,
+  FF_TXD_1_3 => FF_TXD_1_3,
+  FF_TXD_1_2 => FF_TXD_1_2,
+  FF_TXD_1_1 => FF_TXD_1_1,
+  FF_TXD_1_0 => FF_TXD_1_0,
+  FB_RXD_1_23 => FB_RXD_1_23,
+  FB_RXD_1_22 => FB_RXD_1_22,
+  FB_RXD_1_21 => FB_RXD_1_21,
+  FB_RXD_1_20 => FB_RXD_1_20,
+  FB_RXD_1_19 => FB_RXD_1_19,
+  FB_RXD_1_18 => FB_RXD_1_18,
+  FB_RXD_1_17 => FB_RXD_1_17,
+  FB_RXD_1_16 => FB_RXD_1_16,
+  FB_RXD_1_15 => FB_RXD_1_15,
+  FB_RXD_1_14 => FB_RXD_1_14,
+  FB_RXD_1_13 => FB_RXD_1_13,
+  FB_RXD_1_12 => FB_RXD_1_12,
+  FB_RXD_1_11 => FB_RXD_1_11,
+  FB_RXD_1_10 => FB_RXD_1_10,
+  FB_RXD_1_9 => FB_RXD_1_9,
+  FB_RXD_1_8 => FB_RXD_1_8,
+  FB_RXD_1_7 => FB_RXD_1_7,
+  FB_RXD_1_6 => FB_RXD_1_6,
+  FB_RXD_1_5 => FB_RXD_1_5,
+  FB_RXD_1_4 => FB_RXD_1_4,
+  FB_RXD_1_3 => FB_RXD_1_3,
+  FB_RXD_1_2 => FB_RXD_1_2,
+  FB_RXD_1_1 => FB_RXD_1_1,
+  FB_RXD_1_0 => FB_RXD_1_0,
+  FF_TXD_2_23 => FF_TXD_2_23,
+  FF_TXD_2_22 => FF_TXD_2_22,
+  FF_TXD_2_21 => FF_TXD_2_21,
+  FF_TXD_2_20 => FF_TXD_2_20,
+  FF_TXD_2_19 => FF_TXD_2_19,
+  FF_TXD_2_18 => FF_TXD_2_18,
+  FF_TXD_2_17 => FF_TXD_2_17,
+  FF_TXD_2_16 => FF_TXD_2_16,
+  FF_TXD_2_15 => FF_TXD_2_15,
+  FF_TXD_2_14 => FF_TXD_2_14,
+  FF_TXD_2_13 => FF_TXD_2_13,
+  FF_TXD_2_12 => FF_TXD_2_12,
+  FF_TXD_2_11 => FF_TXD_2_11,
+  FF_TXD_2_10 => FF_TXD_2_10,
+  FF_TXD_2_9 => FF_TXD_2_9,
+  FF_TXD_2_8 => FF_TXD_2_8,
+  FF_TXD_2_7 => FF_TXD_2_7,
+  FF_TXD_2_6 => FF_TXD_2_6,
+  FF_TXD_2_5 => FF_TXD_2_5,
+  FF_TXD_2_4 => FF_TXD_2_4,
+  FF_TXD_2_3 => FF_TXD_2_3,
+  FF_TXD_2_2 => FF_TXD_2_2,
+  FF_TXD_2_1 => FF_TXD_2_1,
+  FF_TXD_2_0 => FF_TXD_2_0,
+  FB_RXD_2_23 => FB_RXD_2_23,
+  FB_RXD_2_22 => FB_RXD_2_22,
+  FB_RXD_2_21 => FB_RXD_2_21,
+  FB_RXD_2_20 => FB_RXD_2_20,
+  FB_RXD_2_19 => FB_RXD_2_19,
+  FB_RXD_2_18 => FB_RXD_2_18,
+  FB_RXD_2_17 => FB_RXD_2_17,
+  FB_RXD_2_16 => FB_RXD_2_16,
+  FB_RXD_2_15 => FB_RXD_2_15,
+  FB_RXD_2_14 => FB_RXD_2_14,
+  FB_RXD_2_13 => FB_RXD_2_13,
+  FB_RXD_2_12 => FB_RXD_2_12,
+  FB_RXD_2_11 => FB_RXD_2_11,
+  FB_RXD_2_10 => FB_RXD_2_10,
+  FB_RXD_2_9 => FB_RXD_2_9,
+  FB_RXD_2_8 => FB_RXD_2_8,
+  FB_RXD_2_7 => FB_RXD_2_7,
+  FB_RXD_2_6 => FB_RXD_2_6,
+  FB_RXD_2_5 => FB_RXD_2_5,
+  FB_RXD_2_4 => FB_RXD_2_4,
+  FB_RXD_2_3 => FB_RXD_2_3,
+  FB_RXD_2_2 => FB_RXD_2_2,
+  FB_RXD_2_1 => FB_RXD_2_1,
+  FB_RXD_2_0 => FB_RXD_2_0,
+  FF_TXD_3_23 => FF_TXD_3_23,
+  FF_TXD_3_22 => FF_TXD_3_22,
+  FF_TXD_3_21 => FF_TXD_3_21,
+  FF_TXD_3_20 => FF_TXD_3_20,
+  FF_TXD_3_19 => FF_TXD_3_19,
+  FF_TXD_3_18 => FF_TXD_3_18,
+  FF_TXD_3_17 => FF_TXD_3_17,
+  FF_TXD_3_16 => FF_TXD_3_16,
+  FF_TXD_3_15 => FF_TXD_3_15,
+  FF_TXD_3_14 => FF_TXD_3_14,
+  FF_TXD_3_13 => FF_TXD_3_13,
+  FF_TXD_3_12 => FF_TXD_3_12,
+  FF_TXD_3_11 => FF_TXD_3_11,
+  FF_TXD_3_10 => FF_TXD_3_10,
+  FF_TXD_3_9 => FF_TXD_3_9,
+  FF_TXD_3_8 => FF_TXD_3_8,
+  FF_TXD_3_7 => FF_TXD_3_7,
+  FF_TXD_3_6 => FF_TXD_3_6,
+  FF_TXD_3_5 => FF_TXD_3_5,
+  FF_TXD_3_4 => FF_TXD_3_4,
+  FF_TXD_3_3 => FF_TXD_3_3,
+  FF_TXD_3_2 => FF_TXD_3_2,
+  FF_TXD_3_1 => FF_TXD_3_1,
+  FF_TXD_3_0 => FF_TXD_3_0,
+  FB_RXD_3_23 => FB_RXD_3_23,
+  FB_RXD_3_22 => FB_RXD_3_22,
+  FB_RXD_3_21 => FB_RXD_3_21,
+  FB_RXD_3_20 => FB_RXD_3_20,
+  FB_RXD_3_19 => FB_RXD_3_19,
+  FB_RXD_3_18 => FB_RXD_3_18,
+  FB_RXD_3_17 => FB_RXD_3_17,
+  FB_RXD_3_16 => FB_RXD_3_16,
+  FB_RXD_3_15 => FB_RXD_3_15,
+  FB_RXD_3_14 => FB_RXD_3_14,
+  FB_RXD_3_13 => FB_RXD_3_13,
+  FB_RXD_3_12 => FB_RXD_3_12,
+  FB_RXD_3_11 => FB_RXD_3_11,
+  FB_RXD_3_10 => FB_RXD_3_10,
+  FB_RXD_3_9 => FB_RXD_3_9,
+  FB_RXD_3_8 => FB_RXD_3_8,
+  FB_RXD_3_7 => FB_RXD_3_7,
+  FB_RXD_3_6 => FB_RXD_3_6,
+  FB_RXD_3_5 => FB_RXD_3_5,
+  FB_RXD_3_4 => FB_RXD_3_4,
+  FB_RXD_3_3 => FB_RXD_3_3,
+  FB_RXD_3_2 => FB_RXD_3_2,
+  FB_RXD_3_1 => FB_RXD_3_1,
+  FB_RXD_3_0 => FB_RXD_3_0,
+  TCK_FMAC => TCK_FMAC,
+  COUT_21 => COUT_21,
+  COUT_20 => COUT_20,
+  COUT_19 => COUT_19,
+  COUT_18 => COUT_18,
+  COUT_17 => COUT_17,
+  COUT_16 => COUT_16,
+  COUT_15 => COUT_15,
+  COUT_14 => COUT_14,
+  COUT_13 => COUT_13,
+  COUT_12 => COUT_12,
+  COUT_11 => COUT_11,
+  COUT_10 => COUT_10,
+  COUT_9 => COUT_9,
+  COUT_8 => COUT_8,
+  COUT_7 => COUT_7,
+  COUT_6 => COUT_6,
+  COUT_5 => COUT_5,
+  COUT_4 => COUT_4,
+  COUT_3 => COUT_3,
+  COUT_2 => COUT_2,
+  COUT_1 => COUT_1,
+  COUT_0 => COUT_0,
+  CIN_12 => CIN_12,
+  CIN_11 => CIN_11,
+  CIN_10 => CIN_10,
+  CIN_9 => CIN_9,
+  CIN_8 => CIN_8,
+  CIN_7 => CIN_7,
+  CIN_6 => CIN_6,
+  CIN_5 => CIN_5,
+  CIN_4 => CIN_4,
+  CIN_3 => CIN_3,
+  CIN_2 => CIN_2,
+  CIN_1 => CIN_1,
+  CIN_0 => CIN_0,
+  TESTCLK_MACO => TESTCLK_MACO
+);
+
+end PCSA_arch;
+
+--synopsys translate_on
+
+--synopsys translate_off
+library SC;
+use SC.components.all;
+--synopsys translate_on
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+
+entity serdes_100_ext is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_100_ext.txt");
+ port (
+-- serdes clk pins --
+  refclkp, refclkn : in std_logic;
+  rxa_pclk, rxb_pclk : out std_logic;
+  hdinp_0, hdinn_0 : in std_logic;
+  hdoutp_0, hdoutn_0 : out std_logic;
+  tclk_0, rclk_0 : in std_logic;
+  tx_rst_0, rx_rst_0 : in std_logic;
+  ref_0_sclk, rx_0_sclk : out std_logic;
+  txd_0 : in std_logic_vector (15 downto 0);
+  tx_k_0, tx_force_disp_0, tx_disp_sel_0 : in std_logic_vector (1 downto 0);
+  rxd_0 : out std_logic_vector (15 downto 0);
+  rx_k_0, rx_disp_err_detect_0, rx_cv_detect_0 : out std_logic_vector (1 downto 0);
+  tx_crc_init_0 : in std_logic_vector (1 downto 0);
+  rx_crc_eop_0 : out std_logic_vector (1 downto 0);
+  word_align_en_0, mca_align_en_0, felb_0 : in std_logic;
+  lsm_en_0  : in std_logic;
+  lsm_status_0  : out std_logic;
+
+
+
+  mca_resync_01 : in std_logic;
+  quad_rst, serdes_rst : in std_logic;
+  ref_pclk : out std_logic);
+
+end serdes_100_ext;
+
+architecture serdes_100_ext_arch of serdes_100_ext is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+
+component PCSA
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String
+  );
+--synopsys translate_on
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+end component;
+   attribute IS_ASB: string;
+   attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd";
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE;
+   attribute CH0_RX_MAXRATE: string;
+   attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH1_RX_MAXRATE: string;
+   attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH2_RX_MAXRATE: string;
+   attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH3_RX_MAXRATE: string;
+   attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH0_TX_MAXRATE: string;
+   attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH1_TX_MAXRATE: string;
+   attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH2_TX_MAXRATE: string;
+   attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH3_TX_MAXRATE: string;
+   attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute AMP_BOOST: string;
+   attribute AMP_BOOST of PCSA_INST : label is "DISABLED";
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN";
+
+signal fpsc_vlo : std_logic := '0';
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+
+-- pcs_quad instance
+PCSA_INST : PCSA
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE)
+--synopsys translate_on
+port map  ( 
+  REFCLKP => refclkp,
+  REFCLKN => refclkn,
+  RXREFCLKP => fpsc_vlo,
+  RXREFCLKN => fpsc_vlo,
+  FFC_CK_CORE_RX => fpsc_vlo,
+  FFC_CK_CORE_TX => fpsc_vlo,
+  CS_CHIF_0 => fpsc_vlo,
+  CS_CHIF_1 => fpsc_vlo,
+  CS_CHIF_2 => fpsc_vlo,
+  CS_CHIF_3 => fpsc_vlo,
+  CS_QIF => fpsc_vlo,
+  QUAD_ID_0 => fpsc_vlo,
+  QUAD_ID_1 => fpsc_vlo,
+  ADDRI_0 => fpsc_vlo,
+  ADDRI_1 => fpsc_vlo,
+  ADDRI_2 => fpsc_vlo,
+  ADDRI_3 => fpsc_vlo,
+  ADDRI_4 => fpsc_vlo,
+  ADDRI_5 => fpsc_vlo,
+  ADDRI_6 => fpsc_vlo,
+  ADDRI_7 => fpsc_vlo,
+  WDATAI_0 => fpsc_vlo,
+  WDATAI_1 => fpsc_vlo,
+  WDATAI_2 => fpsc_vlo,
+  WDATAI_3 => fpsc_vlo,
+  WDATAI_4 => fpsc_vlo,
+  WDATAI_5 => fpsc_vlo,
+  WDATAI_6 => fpsc_vlo,
+  WDATAI_7 => fpsc_vlo,
+  RDI => fpsc_vlo,
+  WSTBI => fpsc_vlo,
+  GRP_CLK_P1_0 => fpsc_vlo,
+  GRP_CLK_P1_1 => fpsc_vlo,
+  GRP_CLK_P1_2 => fpsc_vlo,
+  GRP_CLK_P1_3 => fpsc_vlo,
+  GRP_CLK_P2_0 => fpsc_vlo,
+  GRP_CLK_P2_1 => fpsc_vlo,
+  GRP_CLK_P2_2 => fpsc_vlo,
+  GRP_CLK_P2_3 => fpsc_vlo,
+  GRP_START_0 => fpsc_vlo,
+  GRP_START_1 => fpsc_vlo,
+  GRP_START_2 => fpsc_vlo,
+  GRP_START_3 => fpsc_vlo,
+  GRP_DONE_0 => fpsc_vlo,
+  GRP_DONE_1 => fpsc_vlo,
+  GRP_DONE_2 => fpsc_vlo,
+  GRP_DONE_3 => fpsc_vlo,
+  GRP_DESKEW_ERROR_0 => fpsc_vlo,
+  GRP_DESKEW_ERROR_1 => fpsc_vlo,
+  GRP_DESKEW_ERROR_2 => fpsc_vlo,
+  GRP_DESKEW_ERROR_3 => fpsc_vlo,
+-- to sysbusa
+  RDATAO_0 => open,
+  RDATAO_1 => open,
+  RDATAO_2 => open,
+  RDATAO_3 => open,
+  RDATAO_4 => open,
+  RDATAO_5 => open,
+  RDATAO_6 => open,
+  RDATAO_7 => open,
+  INTO => open,
+  QUAD_CLK => open,
+  IQA_START_LS => open,
+  IQA_DONE_LS => open,
+  IQA_AND_FP1_LS => open,
+  IQA_AND_FP0_LS => open,
+  IQA_OR_FP1_LS => open,
+  IQA_OR_FP0_LS => open,
+  IQA_RST_N => open,
+
+  FF_TXD_0_19 => txd_0(15),
+  FF_TXD_0_18 => txd_0(14),
+  FF_TXD_0_17 => txd_0(13),
+  FF_TXD_0_16 => txd_0(12),
+  FF_TXD_0_15 => txd_0(11),
+  FF_TXD_0_14 => txd_0(10),
+  FF_TXD_0_13 => txd_0(9),
+  FF_TXD_0_12 => txd_0(8),
+  FF_TXD_0_7 => txd_0(7),
+  FF_TXD_0_6 => txd_0(6),
+  FF_TXD_0_5 => txd_0(5),
+  FF_TXD_0_4 => txd_0(4),
+  FF_TXD_0_3 => txd_0(3),
+  FF_TXD_0_2 => txd_0(2),
+  FF_TXD_0_1 => txd_0(1),
+  FF_TXD_0_0 => txd_0(0),
+  FB_RXD_0_19 => rxd_0(15),
+  FB_RXD_0_18 => rxd_0(14),
+  FB_RXD_0_17 => rxd_0(13),
+  FB_RXD_0_16 => rxd_0(12),
+  FB_RXD_0_15 => rxd_0(11),
+  FB_RXD_0_14 => rxd_0(10),
+  FB_RXD_0_13 => rxd_0(9),
+  FB_RXD_0_12 => rxd_0(8),
+  FB_RXD_0_7 => rxd_0(7),
+  FB_RXD_0_6 => rxd_0(6),
+  FB_RXD_0_5 => rxd_0(5),
+  FB_RXD_0_4 => rxd_0(4),
+  FB_RXD_0_3 => rxd_0(3),
+  FB_RXD_0_2 => rxd_0(2),
+  FB_RXD_0_1 => rxd_0(1),
+  FB_RXD_0_0 => rxd_0(0),
+
+  FF_TXD_0_20 => tx_k_0(1),
+  FF_TXD_0_8 => tx_k_0(0),
+  FB_RXD_0_20 => rx_k_0(1),
+  FB_RXD_0_8 => rx_k_0(0),
+
+  FF_TXD_0_21 => tx_force_disp_0(1),
+  FF_TXD_0_9 => tx_force_disp_0(0),
+
+  FF_TXD_0_22 => tx_disp_sel_0(1),
+  FF_TXD_0_10 => tx_disp_sel_0(0),
+
+  FF_TXD_0_23 => tx_crc_init_0(1),
+  FF_TXD_0_11 => tx_crc_init_0(0),
+
+  FB_RXD_0_21 => rx_disp_err_detect_0(1),
+  FB_RXD_0_9 => rx_disp_err_detect_0(0),
+
+  FB_RXD_0_22 => rx_cv_detect_0(1),
+  FB_RXD_0_10 => rx_cv_detect_0(0),
+
+  FB_RXD_0_23 => rx_crc_eop_0(1),
+  FB_RXD_0_11 => rx_crc_eop_0(0),
+
+  FF_TXD_1_19 => fpsc_vlo,
+  FF_TXD_1_18 => fpsc_vlo,
+  FF_TXD_1_17 => fpsc_vlo,
+  FF_TXD_1_16 => fpsc_vlo,
+  FF_TXD_1_15 => fpsc_vlo,
+  FF_TXD_1_14 => fpsc_vlo,
+  FF_TXD_1_13 => fpsc_vlo,
+  FF_TXD_1_12 => fpsc_vlo,
+  FF_TXD_1_7 => fpsc_vlo,
+  FF_TXD_1_6 => fpsc_vlo,
+  FF_TXD_1_5 => fpsc_vlo,
+  FF_TXD_1_4 => fpsc_vlo,
+  FF_TXD_1_3 => fpsc_vlo,
+  FF_TXD_1_2 => fpsc_vlo,
+  FF_TXD_1_1 => fpsc_vlo,
+  FF_TXD_1_0 => fpsc_vlo,
+  FB_RXD_1_19 => open,
+  FB_RXD_1_18 => open,
+  FB_RXD_1_17 => open,
+  FB_RXD_1_16 => open,
+  FB_RXD_1_15 => open,
+  FB_RXD_1_14 => open,
+  FB_RXD_1_13 => open,
+  FB_RXD_1_12 => open,
+  FB_RXD_1_7 => open,
+  FB_RXD_1_6 => open,
+  FB_RXD_1_5 => open,
+  FB_RXD_1_4 => open,
+  FB_RXD_1_3 => open,
+  FB_RXD_1_2 => open,
+  FB_RXD_1_1 => open,
+  FB_RXD_1_0 => open,
+
+  FF_TXD_1_20 => fpsc_vlo,
+  FF_TXD_1_8 => fpsc_vlo,
+  FB_RXD_1_20 => open,
+  FB_RXD_1_8 => open,
+
+  FF_TXD_1_21 => fpsc_vlo,
+  FF_TXD_1_9 => fpsc_vlo,
+
+  FF_TXD_1_22 => fpsc_vlo,
+  FF_TXD_1_10 => fpsc_vlo,
+  FF_TXD_1_23 => fpsc_vlo,
+  FF_TXD_1_11 => fpsc_vlo,
+
+  FB_RXD_1_21 => open,
+  FB_RXD_1_9 => open,
+
+  FB_RXD_1_22 => open,
+  FB_RXD_1_10 => open,
+
+  FB_RXD_1_23 => open,
+  FB_RXD_1_11 => open,
+
+  FF_TXD_2_19 => fpsc_vlo,
+  FF_TXD_2_18 => fpsc_vlo,
+  FF_TXD_2_17 => fpsc_vlo,
+  FF_TXD_2_16 => fpsc_vlo,
+  FF_TXD_2_15 => fpsc_vlo,
+  FF_TXD_2_14 => fpsc_vlo,
+  FF_TXD_2_13 => fpsc_vlo,
+  FF_TXD_2_12 => fpsc_vlo,
+  FF_TXD_2_7 => fpsc_vlo,
+  FF_TXD_2_6 => fpsc_vlo,
+  FF_TXD_2_5 => fpsc_vlo,
+  FF_TXD_2_4 => fpsc_vlo,
+  FF_TXD_2_3 => fpsc_vlo,
+  FF_TXD_2_2 => fpsc_vlo,
+  FF_TXD_2_1 => fpsc_vlo,
+  FF_TXD_2_0 => fpsc_vlo,
+  FB_RXD_2_19 => open,
+  FB_RXD_2_18 => open,
+  FB_RXD_2_17 => open,
+  FB_RXD_2_16 => open,
+  FB_RXD_2_15 => open,
+  FB_RXD_2_14 => open,
+  FB_RXD_2_13 => open,
+  FB_RXD_2_12 => open,
+  FB_RXD_2_7 => open,
+  FB_RXD_2_6 => open,
+  FB_RXD_2_5 => open,
+  FB_RXD_2_4 => open,
+  FB_RXD_2_3 => open,
+  FB_RXD_2_2 => open,
+  FB_RXD_2_1 => open,
+  FB_RXD_2_0 => open,
+
+  FF_TXD_2_20 => fpsc_vlo,
+  FF_TXD_2_8 => fpsc_vlo,
+  FB_RXD_2_20 => open,
+  FB_RXD_2_8 => open,
+
+  FF_TXD_2_21 => fpsc_vlo,
+  FF_TXD_2_9 => fpsc_vlo,
+
+  FF_TXD_2_22 => fpsc_vlo,
+  FF_TXD_2_10 => fpsc_vlo,
+  FF_TXD_2_23 => fpsc_vlo,
+  FF_TXD_2_11 => fpsc_vlo,
+
+  FB_RXD_2_21 => open,
+  FB_RXD_2_9 => open,
+
+  FB_RXD_2_22 => open,
+  FB_RXD_2_10 => open,
+
+  FB_RXD_2_23 => open,
+  FB_RXD_2_11 => open,
+
+  FF_TXD_3_19 => fpsc_vlo,
+  FF_TXD_3_18 => fpsc_vlo,
+  FF_TXD_3_17 => fpsc_vlo,
+  FF_TXD_3_16 => fpsc_vlo,
+  FF_TXD_3_15 => fpsc_vlo,
+  FF_TXD_3_14 => fpsc_vlo,
+  FF_TXD_3_13 => fpsc_vlo,
+  FF_TXD_3_12 => fpsc_vlo,
+  FF_TXD_3_7 => fpsc_vlo,
+  FF_TXD_3_6 => fpsc_vlo,
+  FF_TXD_3_5 => fpsc_vlo,
+  FF_TXD_3_4 => fpsc_vlo,
+  FF_TXD_3_3 => fpsc_vlo,
+  FF_TXD_3_2 => fpsc_vlo,
+  FF_TXD_3_1 => fpsc_vlo,
+  FF_TXD_3_0 => fpsc_vlo,
+  FB_RXD_3_19 => open,
+  FB_RXD_3_18 => open,
+  FB_RXD_3_17 => open,
+  FB_RXD_3_16 => open,
+  FB_RXD_3_15 => open,
+  FB_RXD_3_14 => open,
+  FB_RXD_3_13 => open,
+  FB_RXD_3_12 => open,
+  FB_RXD_3_7 => open,
+  FB_RXD_3_6 => open,
+  FB_RXD_3_5 => open,
+  FB_RXD_3_4 => open,
+  FB_RXD_3_3 => open,
+  FB_RXD_3_2 => open,
+  FB_RXD_3_1 => open,
+  FB_RXD_3_0 => open,
+
+  FF_TXD_3_20 => fpsc_vlo,
+  FF_TXD_3_8 => fpsc_vlo,
+  FB_RXD_3_20 => open,
+  FB_RXD_3_8 => open,
+
+  FF_TXD_3_21 => fpsc_vlo,
+  FF_TXD_3_9 => fpsc_vlo,
+
+  FF_TXD_3_22 => fpsc_vlo,
+  FF_TXD_3_10 => fpsc_vlo,
+  FF_TXD_3_23 => fpsc_vlo,
+  FF_TXD_3_11 => fpsc_vlo,
+
+  FB_RXD_3_21 => open,
+  FB_RXD_3_9 => open,
+
+  FB_RXD_3_22 => open,
+  FB_RXD_3_10 => open,
+
+  FB_RXD_3_23 => open,
+  FB_RXD_3_11 => open,
+
+  HDINP0 => hdinp_0,
+  HDINN0 => hdinn_0,
+  HDOUTP0 => hdoutp_0,
+  HDOUTN0 => hdoutn_0,
+  FF_SYSCLK0 => ref_0_sclk,
+  FF_RXCLK0 => rx_0_sclk,
+  FFC_LANE_TX_RST0 => tx_rst_0,
+  FFC_LANE_RX_RST0 => rx_rst_0,
+  FF_TCLK0 => tclk_0,
+  FF_RCLK0 => rclk_0,
+  HDINP1 => fpsc_vlo,
+  HDINN1 => fpsc_vlo,
+  HDOUTP1 => open,
+  HDOUTN1 => open,
+  FF_SYSCLK1 => open,
+  FF_RXCLK1 => open,
+  FFC_LANE_TX_RST1 => fpsc_vlo,
+  FFC_LANE_RX_RST1 => fpsc_vlo,
+  FF_TCLK1 => fpsc_vlo,
+  FF_RCLK1 => fpsc_vlo,
+  HDINP2 => fpsc_vlo,
+  HDINN2 => fpsc_vlo,
+  HDOUTP2 => open,
+  HDOUTN2 => open,
+  FF_SYSCLK2 => open,
+  FF_RXCLK2 => open,
+  FFC_LANE_TX_RST2 => fpsc_vlo,
+  FFC_LANE_RX_RST2 => fpsc_vlo,
+  FF_TCLK2 => fpsc_vlo,
+  FF_RCLK2 => fpsc_vlo,
+  HDINP3 => fpsc_vlo,
+  HDINN3 => fpsc_vlo,
+  HDOUTP3 => open,
+  HDOUTN3 => open,
+  FF_SYSCLK3 => open,
+  FF_RXCLK3 => open,
+  FFC_LANE_TX_RST3 => fpsc_vlo,
+  FFC_LANE_RX_RST3 => fpsc_vlo,
+  FF_TCLK3 => fpsc_vlo,
+  FF_RCLK3 => fpsc_vlo,
+
+  FFC_PCIE_EI_EN_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCIE_TX_0 => fpsc_vlo,
+  FFC_PCIE_RX_0 => fpsc_vlo,
+  FFS_PCIE_CON_0 => open,
+  FFS_PCIE_DONE_0 => open,
+  FFC_PCIE_EI_EN_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCIE_TX_1 => fpsc_vlo,
+  FFC_PCIE_RX_1 => fpsc_vlo,
+  FFS_PCIE_CON_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFC_PCIE_EI_EN_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCIE_TX_2 => fpsc_vlo,
+  FFC_PCIE_RX_2 => fpsc_vlo,
+  FFS_PCIE_CON_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFC_PCIE_EI_EN_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCIE_TX_3 => fpsc_vlo,
+  FFC_PCIE_RX_3 => fpsc_vlo,
+  FFS_PCIE_CON_3 => open,
+  FFS_PCIE_DONE_3 => open,
+
+  FFC_SD_0 => lsm_en_0,
+  FFC_SD_1 => fpsc_vlo,
+  FFC_SD_2 => fpsc_vlo,
+  FFC_SD_3 => fpsc_vlo,
+
+  FFC_EN_CGA_0 => word_align_en_0,
+  FFC_EN_CGA_1 => fpsc_vlo,
+  FFC_EN_CGA_2 => fpsc_vlo,
+  FFC_EN_CGA_3 => fpsc_vlo,
+
+  FFC_ALIGN_EN_0 => mca_align_en_0,
+  FFC_ALIGN_EN_1 => fpsc_vlo,
+  FFC_ALIGN_EN_2 => fpsc_vlo,
+  FFC_ALIGN_EN_3 => fpsc_vlo,
+
+  FFC_FB_LB_0 => felb_0,
+  FFC_FB_LB_1 => fpsc_vlo,
+  FFC_FB_LB_2 => fpsc_vlo,
+  FFC_FB_LB_3 => fpsc_vlo,
+
+  FFS_LS_STATUS_0 => lsm_status_0,
+  FFS_LS_STATUS_1 => open,
+  FFS_LS_STATUS_2 => open,
+  FFS_LS_STATUS_3 => open,
+
+  FFS_CC_ORUN_0 => open,
+  FFS_CC_URUN_0 => open,
+  FFS_CC_ORUN_1 => open,
+  FFS_CC_URUN_1 => open,
+  FFS_CC_ORUN_2 => open,
+  FFS_CC_URUN_2 => open,
+  FFS_CC_ORUN_3 => open,
+  FFS_CC_URUN_3 => open,
+
+  FFC_AB_RESET => mca_resync_01,
+
+  FFS_AB_STATUS => open,
+  FFS_AB_ALIGNED => open,
+  FFS_AB_FAILED => open,
+
+  FFC_CD_RESET => fpsc_vlo,
+  FFS_CD_STATUS => open,
+
+  FFS_CD_ALIGNED => open,
+  FFS_CD_FAILED => open,
+  BS4PAD_0 => open,
+  BS4PAD_1 => open,
+  BS4PAD_2 => open,
+  BS4PAD_3 => open,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  TCK_FMAC => open,
+  TCK_FMACP => fpsc_vlo,
+  FF_SYSCLK_P1 => ref_pclk,
+  FF_RXCLK_P1 => rxa_pclk,
+  FF_RXCLK_P2 => rxb_pclk,
+  FFC_QUAD_RST => quad_rst,
+  FFS_RLOS_LO0 => open,
+  FFS_RLOS_LO1 => open,
+  FFS_RLOS_LO2 => open,
+  FFS_RLOS_LO3 => open,
+  COUT_21 => open,
+  COUT_20 => open,
+  COUT_19 => open,
+  COUT_18 => open,
+  COUT_17 => open,
+  COUT_16 => open,
+  COUT_15 => open,
+  COUT_14 => open,
+  COUT_13 => open,
+  COUT_12 => open,
+  COUT_11 => open,
+  COUT_10 => open,
+  COUT_9 => open,
+  COUT_8 => open,
+  COUT_7 => open,
+  COUT_6 => open,
+  COUT_5 => open,
+  COUT_4 => open,
+  COUT_3 => open,
+  COUT_2 => open,
+  COUT_1 => open,
+  COUT_0 => open,
+  CIN_12 => fpsc_vlo,
+  CIN_11 => fpsc_vlo,
+  CIN_10 => fpsc_vlo,
+  CIN_9 => fpsc_vlo,
+  CIN_8 => fpsc_vlo,
+  CIN_7 => fpsc_vlo,
+  CIN_6 => fpsc_vlo,
+  CIN_5 => fpsc_vlo,
+  CIN_4 => fpsc_vlo,
+  CIN_3 => fpsc_vlo,
+  CIN_2 => fpsc_vlo,
+  CIN_1 => fpsc_vlo,
+  CIN_0 => fpsc_vlo,
+  TESTCLK_MACO => fpsc_vlo,
+  FFC_MACRO_RST => serdes_rst);
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+  
+end serdes_100_ext_arch ;
diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_100.ipx b/media_interfaces/scm_sfp/serdes_gbe_0_100.ipx
new file mode 100644
index 0000000..aad20e0
--- /dev/null
+++ b/media_interfaces/scm_sfp/serdes_gbe_0_100.ipx
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_gbe_0_100" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2010 12 10 17:12:12.460" version="8.1" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="serdes_gbe_0_100.lpc" type="lpc" modified="2010 12 10 17:12:08.000"/>
+		<File name="serdes_gbe_0_100.pp" type="pp" modified="2010 12 10 17:12:08.000"/>
+		<File name="serdes_gbe_0_100.sym" type="sym" modified="2010 12 10 17:12:09.000"/>
+		<File name="serdes_gbe_0_100.tft" type="tft" modified="2010 12 10 17:12:08.000"/>
+		<File name="serdes_gbe_0_100.txt" type="pcs_module" modified="2010 12 10 17:12:08.000"/>
+		<File name="serdes_gbe_0_100.vhd" type="top_level_vhdl" modified="2010 12 10 17:12:08.000"/>
+  </Package>
+</DiamondModule>
diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_100.lpc b/media_interfaces/scm_sfp/serdes_gbe_0_100.lpc
new file mode 100755
index 0000000..0b52156
--- /dev/null
+++ b/media_interfaces/scm_sfp/serdes_gbe_0_100.lpc
@@ -0,0 +1,61 @@
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-7FF1020C
+SpeedGrade=7
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=8.1
+ModuleName=serdes_gbe_0_100
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=12/10/2010
+Time=17:12:08
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+QuadMode=Generic 8b10b
+enChannel0=1
+enChannel1=0
+enChannel2=0
+enChannel3=0
+enAlign0=0
+enAlign1=0
+enAlign2=0
+enControlPorts=1
+enSystemBus=0
+en10gLsm=0
+ClkSelect=All Reference Clocks
+BitClkRate=2
+RefClkMult=20X
+RefClkRate=100
+BusWidth=16
+IntClkRate=100
+AmpBoost=Disabled
+Bit1=0
+Word1=FF
+Bit2=0
+Word2=7C
+Bit3=0
+Word3=7C
+enQuad=0
+QuadGroup=Group 0
+
+[FilesGenerated]
+serdes_gbe_0_100.pp=pp
+serdes_gbe_0_100.tft=tft
+serdes_gbe_0_100.txt=pcs_module
+serdes_gbe_0_100.sym=sym
diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_100.txt b/media_interfaces/scm_sfp/serdes_gbe_0_100.txt
new file mode 100644
index 0000000..0aece59
--- /dev/null
+++ b/media_interfaces/scm_sfp/serdes_gbe_0_100.txt
@@ -0,0 +1,79 @@
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCS quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCS quad to the final design requirements.
+# channel_0 is in "8b10b" mode
+# channel_1 is in "Disabled" mode
+# channel_2 is in "Disabled" mode
+# channel_3 is in "Disabled" mode
+
+ch0  13 03  # Powerup Channel 0 TX/RX
+ch0  00 01  # link state machine enabled
+quad 00 00  # some standard settings?
+quad 01 E4  # RX clock select
+quad 28 40  # Reference clock multiplier
+quad 29 11  # JM101203 core clock as reference # set to 01
+quad 30 04  # JM101203 TX sync enable   #sync TX clock from all channels
+quad 02 00  # ref_pclk source is ch0, rxa_pclk is ch0, rxb_pclk is ch0
+quad 04 00  # MCA enable 4 channels
+
+quad 18 10  # 8b10b Mode
+
+#Here default values are used by SM
+# quad 14 FF  # Word Alignment Mask [7:0]
+# quad 15 83  # +ve K [7:0] -> COMMA_A = 11_0000_0101 - its inverted (see register convention in datasheet)!
+# quad 16 7c  # -ve K [7:0] -> COMMA_B = 00_1111_1010 - its inverted !
+# quad 17 36  # upper bits of CA,CB,CM
+
+
+# quad 0D 97  # Watermark level on CTC: 9 high, 7 low
+# quad 0E 08  # JM101203 was 0B # insertion/deletion control of CTC: two char matching
+# quad 11 BC  # /I2/ pattern for CTC match (K28.5)
+# quad 12 50  # (D16.2)
+# quad 13 04  # (use comma)
+
+quad 19 0C  # Disable word_align_en port, FPGA bus width is 16-bit/20-bit
+ch0  14 90  # 16% pre-emphasis
+ch0  15 18  # JM101203 was 10 # +6dB equalization
+
+# These lines must appear last in the autoconfig file.  These lines apply the correct
+# reset sequence to the PCS block upon bitstream configuration
+quad 41 00  # de-assert serdes_rst
+quad 40 ff  # assert datapath reset for all channels
+quad 40 00  # de-assert datapath reset for all channels
+
+# # This file is used by the simulation model as well as the ispLEVER bitstream
+# # generation process to automatically initialize the PCS quad to the mode
+# # selected in the IPexpress. This file is expected to be modified by the
+# # end user to adjust the PCS quad to the final design requirements.
+# # channel_0 is in "8b10b" mode
+# # channel_1 is in "Disabled" mode
+# # channel_2 is in "Disabled" mode
+# # channel_3 is in "Disabled" mode
+#
+# ch0 13 03  # Powerup Channel
+# ch0 00 00
+# quad 00 00
+# quad 01 E4
+# quad 28 40  # Reference clock multiplier
+# quad 29 01  # set to 01
+# quad 02 00  # ref_pclk source is ch0
+# quad 04 00  # MCA enable 4 channels
+#
+# quad 18 10  # 8b10b Mode
+# # quad 14 7F  # Word Alignment Mask
+# # quad 15 03  # +ve K
+# # quad 16 7C  # -ve K
+# quad 19 8C  # Enable word_align_en port, FPGA bus width is 16-bit/20-bit
+# ch0 14 90  # 16% pre-emphasis
+# ch0 15 10  # +6dB equalization
+#
+# # These lines must appear last in the autoconfig file.  These lines apply the correct
+# # reset sequence to the PCS block upon bitstream configuration
+# quad 41 00  # de-assert serdes_rst
+# quad 40 ff  # assert datapath reset for all channels
+# quad 40 00  # de-assert datapath reset for all channels
+#
+#
+#
diff --git a/media_interfaces/scm_sfp/serdes_gbe_0_100.vhd b/media_interfaces/scm_sfp/serdes_gbe_0_100.vhd
new file mode 100644
index 0000000..0bc3ae1
--- /dev/null
+++ b/media_interfaces/scm_sfp/serdes_gbe_0_100.vhd
@@ -0,0 +1,2393 @@
+
+
+-- channel_0 is in "8b10b" mode
+-- channel_1 is in "Disabled" mode
+-- channel_2 is in "Disabled" mode
+-- channel_3 is in "Disabled" mode
+
+--synopsys translate_off
+
+library pcsa_work;
+use pcsa_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSA is
+GENERIC(
+  CONFIG_FILE : String  := "serdes_gbe_0_100.txt"
+  );
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+
+end PCSA;
+
+architecture PCSA_arch of PCSA is
+
+component PCSA_sim
+GENERIC(
+  CONFIG_FILE : String
+  );
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+end component;
+
+begin
+
+PCSA_sim_inst : PCSA_sim 
+generic map (
+  CONFIG_FILE => CONFIG_FILE)
+port map (
+  HDINP0 => HDINP0,
+  HDINN0 => HDINN0,
+  HDINP1 => HDINP1,
+  HDINN1 => HDINN1,
+  HDINP2 => HDINP2,
+  HDINN2 => HDINN2,
+  HDINP3 => HDINP3,
+  HDINN3 => HDINN3,
+  HDOUTP0 => HDOUTP0,
+  HDOUTN0 => HDOUTN0,
+  HDOUTP1 => HDOUTP1,
+  HDOUTN1 => HDOUTN1,
+  HDOUTP2 => HDOUTP2,
+  HDOUTN2 => HDOUTN2,
+  HDOUTP3 => HDOUTP3,
+  HDOUTN3 => HDOUTN3,
+  REFCLKP => REFCLKP,
+  REFCLKN => REFCLKN,
+  RXREFCLKP => RXREFCLKP,
+  RXREFCLKN => RXREFCLKN,
+  FFC_QUAD_RST => FFC_QUAD_RST,
+  FFC_MACRO_RST => FFC_MACRO_RST,
+  FFC_LANE_TX_RST0 => FFC_LANE_TX_RST0,
+  FFC_LANE_TX_RST1 => FFC_LANE_TX_RST1,
+  FFC_LANE_TX_RST2 => FFC_LANE_TX_RST2,
+  FFC_LANE_TX_RST3 => FFC_LANE_TX_RST3,
+  FFC_LANE_RX_RST0 => FFC_LANE_RX_RST0,
+  FFC_LANE_RX_RST1 => FFC_LANE_RX_RST1,
+  FFC_LANE_RX_RST2 => FFC_LANE_RX_RST2,
+  FFC_LANE_RX_RST3 => FFC_LANE_RX_RST3,
+  FFC_PCIE_EI_EN_0 => FFC_PCIE_EI_EN_0,
+  FFC_PCIE_EI_EN_1 => FFC_PCIE_EI_EN_1,
+  FFC_PCIE_EI_EN_2 => FFC_PCIE_EI_EN_2,
+  FFC_PCIE_EI_EN_3 => FFC_PCIE_EI_EN_3,
+  FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+  FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+  FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+  FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+  FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+  FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+  FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+  FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+  FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+  FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+  FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+  FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+  FFC_PCIE_TX_0 => FFC_PCIE_TX_0,
+  FFC_PCIE_TX_1 => FFC_PCIE_TX_1,
+  FFC_PCIE_TX_2 => FFC_PCIE_TX_2,
+  FFC_PCIE_TX_3 => FFC_PCIE_TX_3,
+  FFC_PCIE_RX_0 => FFC_PCIE_RX_0,
+  FFC_PCIE_RX_1 => FFC_PCIE_RX_1,
+  FFC_PCIE_RX_2 => FFC_PCIE_RX_2,
+  FFC_PCIE_RX_3 => FFC_PCIE_RX_3,
+  FFC_SD_0 => FFC_SD_0,
+  FFC_SD_1 => FFC_SD_1,
+  FFC_SD_2 => FFC_SD_2,
+  FFC_SD_3 => FFC_SD_3,
+  FFC_EN_CGA_0 => FFC_EN_CGA_0,
+  FFC_EN_CGA_1 => FFC_EN_CGA_1,
+  FFC_EN_CGA_2 => FFC_EN_CGA_2,
+  FFC_EN_CGA_3 => FFC_EN_CGA_3,
+  FFC_ALIGN_EN_0 => FFC_ALIGN_EN_0,
+  FFC_ALIGN_EN_1 => FFC_ALIGN_EN_1,
+  FFC_ALIGN_EN_2 => FFC_ALIGN_EN_2,
+  FFC_ALIGN_EN_3 => FFC_ALIGN_EN_3,
+  FFC_AB_RESET => FFC_AB_RESET,
+  FFC_CD_RESET => FFC_CD_RESET,
+  FFS_LS_STATUS_0 => FFS_LS_STATUS_0,
+  FFS_LS_STATUS_1 => FFS_LS_STATUS_1,
+  FFS_LS_STATUS_2 => FFS_LS_STATUS_2,
+  FFS_LS_STATUS_3 => FFS_LS_STATUS_3,
+  FFS_AB_STATUS => FFS_AB_STATUS,
+  FFS_CD_STATUS => FFS_CD_STATUS,
+  FFS_AB_ALIGNED => FFS_AB_ALIGNED,
+  FFS_CD_ALIGNED => FFS_CD_ALIGNED,
+  FFS_AB_FAILED => FFS_AB_FAILED,
+  FFS_CD_FAILED => FFS_CD_FAILED,
+  FFS_RLOS_LO0 => FFS_RLOS_LO0,
+  FFS_RLOS_LO1 => FFS_RLOS_LO1,
+  FFS_RLOS_LO2 => FFS_RLOS_LO2,
+  FFS_RLOS_LO3 => FFS_RLOS_LO3,
+  FFC_FB_LB_0 => FFC_FB_LB_0,
+  FFC_FB_LB_1 => FFC_FB_LB_1,
+  FFC_FB_LB_2 => FFC_FB_LB_2,
+  FFC_FB_LB_3 => FFC_FB_LB_3,
+  FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+  FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+  FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+  FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+  FFS_CC_ORUN_0 => FFS_CC_ORUN_0,
+  FFS_CC_ORUN_1 => FFS_CC_ORUN_1,
+  FFS_CC_ORUN_2 => FFS_CC_ORUN_2,
+  FFS_CC_ORUN_3 => FFS_CC_ORUN_3,
+  FFS_CC_URUN_0 => FFS_CC_URUN_0,
+  FFS_CC_URUN_1 => FFS_CC_URUN_1,
+  FFS_CC_URUN_2 => FFS_CC_URUN_2,
+  FFS_CC_URUN_3 => FFS_CC_URUN_3,
+  FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+  FFC_CK_CORE_RX => FFC_CK_CORE_RX,
+  BS4PAD_0 => BS4PAD_0,
+  BS4PAD_1 => BS4PAD_1,
+  BS4PAD_2 => BS4PAD_2,
+  BS4PAD_3 => BS4PAD_3,
+  RDATAO_7 => RDATAO_7,
+  RDATAO_6 => RDATAO_6,
+  RDATAO_5 => RDATAO_5,
+  RDATAO_4 => RDATAO_4,
+  RDATAO_3 => RDATAO_3,
+  RDATAO_2 => RDATAO_2,
+  RDATAO_1 => RDATAO_1,
+  RDATAO_0 => RDATAO_0,
+  INTO => INTO,
+  ADDRI_7 => ADDRI_7,
+  ADDRI_6 => ADDRI_6,
+  ADDRI_5 => ADDRI_5,
+  ADDRI_4 => ADDRI_4,
+  ADDRI_3 => ADDRI_3,
+  ADDRI_2 => ADDRI_2,
+  ADDRI_1 => ADDRI_1,
+  ADDRI_0 => ADDRI_0,
+  WDATAI_7 => WDATAI_7,
+  WDATAI_6 => WDATAI_6,
+  WDATAI_5 => WDATAI_5,
+  WDATAI_4 => WDATAI_4,
+  WDATAI_3 => WDATAI_3,
+  WDATAI_2 => WDATAI_2,
+  WDATAI_1 => WDATAI_1,
+  WDATAI_0 => WDATAI_0,
+  RDI => RDI,
+  WSTBI => WSTBI,
+  CS_CHIF_0 => CS_CHIF_0,
+  CS_CHIF_1 => CS_CHIF_1,
+  CS_CHIF_2 => CS_CHIF_2,
+  CS_CHIF_3 => CS_CHIF_3,
+  CS_QIF => CS_QIF,
+  QUAD_ID_1 => QUAD_ID_1,
+  QUAD_ID_0 => QUAD_ID_0,
+  FF_SYSCLK_P1 => FF_SYSCLK_P1,
+  FF_SYSCLK0 => FF_SYSCLK0,
+  FF_SYSCLK1 => FF_SYSCLK1,
+  FF_SYSCLK2 => FF_SYSCLK2,
+  FF_SYSCLK3 => FF_SYSCLK3,
+  FF_RXCLK_P1 => FF_RXCLK_P1,
+  FF_RXCLK_P2 => FF_RXCLK_P2,
+  FF_RXCLK0 => FF_RXCLK0,
+  FF_RXCLK1 => FF_RXCLK1,
+  FF_RXCLK2 => FF_RXCLK2,
+  FF_RXCLK3 => FF_RXCLK3,
+  QUAD_CLK => QUAD_CLK,
+  GRP_CLK_P1_3 => GRP_CLK_P1_3,
+  GRP_CLK_P1_2 => GRP_CLK_P1_2,
+  GRP_CLK_P1_1 => GRP_CLK_P1_1,
+  GRP_CLK_P1_0 => GRP_CLK_P1_0,
+  GRP_CLK_P2_3 => GRP_CLK_P2_3,
+  GRP_CLK_P2_2 => GRP_CLK_P2_2,
+  GRP_CLK_P2_1 => GRP_CLK_P2_1,
+  GRP_CLK_P2_0 => GRP_CLK_P2_0,
+  GRP_START_3 => GRP_START_3,
+  GRP_START_2 => GRP_START_2,
+  GRP_START_1 => GRP_START_1,
+  GRP_START_0 => GRP_START_0,
+  GRP_DONE_3 => GRP_DONE_3,
+  GRP_DONE_2 => GRP_DONE_2,
+  GRP_DONE_1 => GRP_DONE_1,
+  GRP_DONE_0 => GRP_DONE_0,
+  GRP_DESKEW_ERROR_3 => GRP_DESKEW_ERROR_3,
+  GRP_DESKEW_ERROR_2 => GRP_DESKEW_ERROR_2,
+  GRP_DESKEW_ERROR_1 => GRP_DESKEW_ERROR_1,
+  GRP_DESKEW_ERROR_0 => GRP_DESKEW_ERROR_0,
+  IQA_START_LS => IQA_START_LS,
+  IQA_DONE_LS => IQA_DONE_LS,
+  IQA_AND_FP1_LS => IQA_AND_FP1_LS,
+  IQA_AND_FP0_LS => IQA_AND_FP0_LS,
+  IQA_OR_FP1_LS => IQA_OR_FP1_LS,
+  IQA_OR_FP0_LS => IQA_OR_FP0_LS,
+  IQA_RST_N => IQA_RST_N,
+  FF_TCLK0 => FF_TCLK0,
+  FF_TCLK1 => FF_TCLK1,
+  FF_TCLK2 => FF_TCLK2,
+  FF_TCLK3 => FF_TCLK3,
+  FF_RCLK0 => FF_RCLK0,
+  FF_RCLK1 => FF_RCLK1,
+  FF_RCLK2 => FF_RCLK2,
+  FF_RCLK3 => FF_RCLK3,
+  TCK_FMACP => TCK_FMACP,
+  FF_TXD_0_23 => FF_TXD_0_23,
+  FF_TXD_0_22 => FF_TXD_0_22,
+  FF_TXD_0_21 => FF_TXD_0_21,
+  FF_TXD_0_20 => FF_TXD_0_20,
+  FF_TXD_0_19 => FF_TXD_0_19,
+  FF_TXD_0_18 => FF_TXD_0_18,
+  FF_TXD_0_17 => FF_TXD_0_17,
+  FF_TXD_0_16 => FF_TXD_0_16,
+  FF_TXD_0_15 => FF_TXD_0_15,
+  FF_TXD_0_14 => FF_TXD_0_14,
+  FF_TXD_0_13 => FF_TXD_0_13,
+  FF_TXD_0_12 => FF_TXD_0_12,
+  FF_TXD_0_11 => FF_TXD_0_11,
+  FF_TXD_0_10 => FF_TXD_0_10,
+  FF_TXD_0_9 => FF_TXD_0_9,
+  FF_TXD_0_8 => FF_TXD_0_8,
+  FF_TXD_0_7 => FF_TXD_0_7,
+  FF_TXD_0_6 => FF_TXD_0_6,
+  FF_TXD_0_5 => FF_TXD_0_5,
+  FF_TXD_0_4 => FF_TXD_0_4,
+  FF_TXD_0_3 => FF_TXD_0_3,
+  FF_TXD_0_2 => FF_TXD_0_2,
+  FF_TXD_0_1 => FF_TXD_0_1,
+  FF_TXD_0_0 => FF_TXD_0_0,
+  FB_RXD_0_23 => FB_RXD_0_23,
+  FB_RXD_0_22 => FB_RXD_0_22,
+  FB_RXD_0_21 => FB_RXD_0_21,
+  FB_RXD_0_20 => FB_RXD_0_20,
+  FB_RXD_0_19 => FB_RXD_0_19,
+  FB_RXD_0_18 => FB_RXD_0_18,
+  FB_RXD_0_17 => FB_RXD_0_17,
+  FB_RXD_0_16 => FB_RXD_0_16,
+  FB_RXD_0_15 => FB_RXD_0_15,
+  FB_RXD_0_14 => FB_RXD_0_14,
+  FB_RXD_0_13 => FB_RXD_0_13,
+  FB_RXD_0_12 => FB_RXD_0_12,
+  FB_RXD_0_11 => FB_RXD_0_11,
+  FB_RXD_0_10 => FB_RXD_0_10,
+  FB_RXD_0_9 => FB_RXD_0_9,
+  FB_RXD_0_8 => FB_RXD_0_8,
+  FB_RXD_0_7 => FB_RXD_0_7,
+  FB_RXD_0_6 => FB_RXD_0_6,
+  FB_RXD_0_5 => FB_RXD_0_5,
+  FB_RXD_0_4 => FB_RXD_0_4,
+  FB_RXD_0_3 => FB_RXD_0_3,
+  FB_RXD_0_2 => FB_RXD_0_2,
+  FB_RXD_0_1 => FB_RXD_0_1,
+  FB_RXD_0_0 => FB_RXD_0_0,
+  FF_TXD_1_23 => FF_TXD_1_23,
+  FF_TXD_1_22 => FF_TXD_1_22,
+  FF_TXD_1_21 => FF_TXD_1_21,
+  FF_TXD_1_20 => FF_TXD_1_20,
+  FF_TXD_1_19 => FF_TXD_1_19,
+  FF_TXD_1_18 => FF_TXD_1_18,
+  FF_TXD_1_17 => FF_TXD_1_17,
+  FF_TXD_1_16 => FF_TXD_1_16,
+  FF_TXD_1_15 => FF_TXD_1_15,
+  FF_TXD_1_14 => FF_TXD_1_14,
+  FF_TXD_1_13 => FF_TXD_1_13,
+  FF_TXD_1_12 => FF_TXD_1_12,
+  FF_TXD_1_11 => FF_TXD_1_11,
+  FF_TXD_1_10 => FF_TXD_1_10,
+  FF_TXD_1_9 => FF_TXD_1_9,
+  FF_TXD_1_8 => FF_TXD_1_8,
+  FF_TXD_1_7 => FF_TXD_1_7,
+  FF_TXD_1_6 => FF_TXD_1_6,
+  FF_TXD_1_5 => FF_TXD_1_5,
+  FF_TXD_1_4 => FF_TXD_1_4,
+  FF_TXD_1_3 => FF_TXD_1_3,
+  FF_TXD_1_2 => FF_TXD_1_2,
+  FF_TXD_1_1 => FF_TXD_1_1,
+  FF_TXD_1_0 => FF_TXD_1_0,
+  FB_RXD_1_23 => FB_RXD_1_23,
+  FB_RXD_1_22 => FB_RXD_1_22,
+  FB_RXD_1_21 => FB_RXD_1_21,
+  FB_RXD_1_20 => FB_RXD_1_20,
+  FB_RXD_1_19 => FB_RXD_1_19,
+  FB_RXD_1_18 => FB_RXD_1_18,
+  FB_RXD_1_17 => FB_RXD_1_17,
+  FB_RXD_1_16 => FB_RXD_1_16,
+  FB_RXD_1_15 => FB_RXD_1_15,
+  FB_RXD_1_14 => FB_RXD_1_14,
+  FB_RXD_1_13 => FB_RXD_1_13,
+  FB_RXD_1_12 => FB_RXD_1_12,
+  FB_RXD_1_11 => FB_RXD_1_11,
+  FB_RXD_1_10 => FB_RXD_1_10,
+  FB_RXD_1_9 => FB_RXD_1_9,
+  FB_RXD_1_8 => FB_RXD_1_8,
+  FB_RXD_1_7 => FB_RXD_1_7,
+  FB_RXD_1_6 => FB_RXD_1_6,
+  FB_RXD_1_5 => FB_RXD_1_5,
+  FB_RXD_1_4 => FB_RXD_1_4,
+  FB_RXD_1_3 => FB_RXD_1_3,
+  FB_RXD_1_2 => FB_RXD_1_2,
+  FB_RXD_1_1 => FB_RXD_1_1,
+  FB_RXD_1_0 => FB_RXD_1_0,
+  FF_TXD_2_23 => FF_TXD_2_23,
+  FF_TXD_2_22 => FF_TXD_2_22,
+  FF_TXD_2_21 => FF_TXD_2_21,
+  FF_TXD_2_20 => FF_TXD_2_20,
+  FF_TXD_2_19 => FF_TXD_2_19,
+  FF_TXD_2_18 => FF_TXD_2_18,
+  FF_TXD_2_17 => FF_TXD_2_17,
+  FF_TXD_2_16 => FF_TXD_2_16,
+  FF_TXD_2_15 => FF_TXD_2_15,
+  FF_TXD_2_14 => FF_TXD_2_14,
+  FF_TXD_2_13 => FF_TXD_2_13,
+  FF_TXD_2_12 => FF_TXD_2_12,
+  FF_TXD_2_11 => FF_TXD_2_11,
+  FF_TXD_2_10 => FF_TXD_2_10,
+  FF_TXD_2_9 => FF_TXD_2_9,
+  FF_TXD_2_8 => FF_TXD_2_8,
+  FF_TXD_2_7 => FF_TXD_2_7,
+  FF_TXD_2_6 => FF_TXD_2_6,
+  FF_TXD_2_5 => FF_TXD_2_5,
+  FF_TXD_2_4 => FF_TXD_2_4,
+  FF_TXD_2_3 => FF_TXD_2_3,
+  FF_TXD_2_2 => FF_TXD_2_2,
+  FF_TXD_2_1 => FF_TXD_2_1,
+  FF_TXD_2_0 => FF_TXD_2_0,
+  FB_RXD_2_23 => FB_RXD_2_23,
+  FB_RXD_2_22 => FB_RXD_2_22,
+  FB_RXD_2_21 => FB_RXD_2_21,
+  FB_RXD_2_20 => FB_RXD_2_20,
+  FB_RXD_2_19 => FB_RXD_2_19,
+  FB_RXD_2_18 => FB_RXD_2_18,
+  FB_RXD_2_17 => FB_RXD_2_17,
+  FB_RXD_2_16 => FB_RXD_2_16,
+  FB_RXD_2_15 => FB_RXD_2_15,
+  FB_RXD_2_14 => FB_RXD_2_14,
+  FB_RXD_2_13 => FB_RXD_2_13,
+  FB_RXD_2_12 => FB_RXD_2_12,
+  FB_RXD_2_11 => FB_RXD_2_11,
+  FB_RXD_2_10 => FB_RXD_2_10,
+  FB_RXD_2_9 => FB_RXD_2_9,
+  FB_RXD_2_8 => FB_RXD_2_8,
+  FB_RXD_2_7 => FB_RXD_2_7,
+  FB_RXD_2_6 => FB_RXD_2_6,
+  FB_RXD_2_5 => FB_RXD_2_5,
+  FB_RXD_2_4 => FB_RXD_2_4,
+  FB_RXD_2_3 => FB_RXD_2_3,
+  FB_RXD_2_2 => FB_RXD_2_2,
+  FB_RXD_2_1 => FB_RXD_2_1,
+  FB_RXD_2_0 => FB_RXD_2_0,
+  FF_TXD_3_23 => FF_TXD_3_23,
+  FF_TXD_3_22 => FF_TXD_3_22,
+  FF_TXD_3_21 => FF_TXD_3_21,
+  FF_TXD_3_20 => FF_TXD_3_20,
+  FF_TXD_3_19 => FF_TXD_3_19,
+  FF_TXD_3_18 => FF_TXD_3_18,
+  FF_TXD_3_17 => FF_TXD_3_17,
+  FF_TXD_3_16 => FF_TXD_3_16,
+  FF_TXD_3_15 => FF_TXD_3_15,
+  FF_TXD_3_14 => FF_TXD_3_14,
+  FF_TXD_3_13 => FF_TXD_3_13,
+  FF_TXD_3_12 => FF_TXD_3_12,
+  FF_TXD_3_11 => FF_TXD_3_11,
+  FF_TXD_3_10 => FF_TXD_3_10,
+  FF_TXD_3_9 => FF_TXD_3_9,
+  FF_TXD_3_8 => FF_TXD_3_8,
+  FF_TXD_3_7 => FF_TXD_3_7,
+  FF_TXD_3_6 => FF_TXD_3_6,
+  FF_TXD_3_5 => FF_TXD_3_5,
+  FF_TXD_3_4 => FF_TXD_3_4,
+  FF_TXD_3_3 => FF_TXD_3_3,
+  FF_TXD_3_2 => FF_TXD_3_2,
+  FF_TXD_3_1 => FF_TXD_3_1,
+  FF_TXD_3_0 => FF_TXD_3_0,
+  FB_RXD_3_23 => FB_RXD_3_23,
+  FB_RXD_3_22 => FB_RXD_3_22,
+  FB_RXD_3_21 => FB_RXD_3_21,
+  FB_RXD_3_20 => FB_RXD_3_20,
+  FB_RXD_3_19 => FB_RXD_3_19,
+  FB_RXD_3_18 => FB_RXD_3_18,
+  FB_RXD_3_17 => FB_RXD_3_17,
+  FB_RXD_3_16 => FB_RXD_3_16,
+  FB_RXD_3_15 => FB_RXD_3_15,
+  FB_RXD_3_14 => FB_RXD_3_14,
+  FB_RXD_3_13 => FB_RXD_3_13,
+  FB_RXD_3_12 => FB_RXD_3_12,
+  FB_RXD_3_11 => FB_RXD_3_11,
+  FB_RXD_3_10 => FB_RXD_3_10,
+  FB_RXD_3_9 => FB_RXD_3_9,
+  FB_RXD_3_8 => FB_RXD_3_8,
+  FB_RXD_3_7 => FB_RXD_3_7,
+  FB_RXD_3_6 => FB_RXD_3_6,
+  FB_RXD_3_5 => FB_RXD_3_5,
+  FB_RXD_3_4 => FB_RXD_3_4,
+  FB_RXD_3_3 => FB_RXD_3_3,
+  FB_RXD_3_2 => FB_RXD_3_2,
+  FB_RXD_3_1 => FB_RXD_3_1,
+  FB_RXD_3_0 => FB_RXD_3_0,
+  TCK_FMAC => TCK_FMAC,
+  COUT_21 => COUT_21,
+  COUT_20 => COUT_20,
+  COUT_19 => COUT_19,
+  COUT_18 => COUT_18,
+  COUT_17 => COUT_17,
+  COUT_16 => COUT_16,
+  COUT_15 => COUT_15,
+  COUT_14 => COUT_14,
+  COUT_13 => COUT_13,
+  COUT_12 => COUT_12,
+  COUT_11 => COUT_11,
+  COUT_10 => COUT_10,
+  COUT_9 => COUT_9,
+  COUT_8 => COUT_8,
+  COUT_7 => COUT_7,
+  COUT_6 => COUT_6,
+  COUT_5 => COUT_5,
+  COUT_4 => COUT_4,
+  COUT_3 => COUT_3,
+  COUT_2 => COUT_2,
+  COUT_1 => COUT_1,
+  COUT_0 => COUT_0,
+  CIN_12 => CIN_12,
+  CIN_11 => CIN_11,
+  CIN_10 => CIN_10,
+  CIN_9 => CIN_9,
+  CIN_8 => CIN_8,
+  CIN_7 => CIN_7,
+  CIN_6 => CIN_6,
+  CIN_5 => CIN_5,
+  CIN_4 => CIN_4,
+  CIN_3 => CIN_3,
+  CIN_2 => CIN_2,
+  CIN_1 => CIN_1,
+  CIN_0 => CIN_0,
+  TESTCLK_MACO => TESTCLK_MACO
+);
+
+end PCSA_arch;
+
+--synopsys translate_on
+
+--synopsys translate_off
+library SC;
+use SC.components.all;
+--synopsys translate_on
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+
+entity serdes_gbe_0_100 is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_gbe_0_100.txt");
+ port (
+-- serdes clk pins --
+  refclkp, refclkn : in std_logic;
+  rxrefclk, refclk : in std_logic;
+  rxa_pclk, rxb_pclk : out std_logic;
+  hdinp_0, hdinn_0 : in std_logic;
+  hdoutp_0, hdoutn_0 : out std_logic;
+  tclk_0, rclk_0 : in std_logic;
+  tx_rst_0, rx_rst_0 : in std_logic;
+  ref_0_sclk, rx_0_sclk : out std_logic;
+  txd_0 : in std_logic_vector (15 downto 0);
+  tx_k_0, tx_force_disp_0, tx_disp_sel_0 : in std_logic_vector (1 downto 0);
+  rxd_0 : out std_logic_vector (15 downto 0);
+  rx_k_0, rx_disp_err_detect_0, rx_cv_detect_0 : out std_logic_vector (1 downto 0);
+  tx_crc_init_0 : in std_logic_vector (1 downto 0);
+  rx_crc_eop_0 : out std_logic_vector (1 downto 0);
+  word_align_en_0, mca_align_en_0, felb_0 : in std_logic;
+  lsm_en_0  : in std_logic;
+  lsm_status_0  : out std_logic;
+
+
+
+  mca_resync_01 : in std_logic;
+  quad_rst, serdes_rst : in std_logic;
+  ref_pclk : out std_logic);
+
+end serdes_gbe_0_100;
+
+architecture serdes_gbe_0_100_arch of serdes_gbe_0_100 is
+
+component VLO
+port (
+   Z : out std_logic);
+end component;
+
+component VHI
+port (
+   Z : out std_logic);
+end component;
+
+component PCSA
+--synopsys translate_off
+GENERIC(
+  CONFIG_FILE : String
+  );
+--synopsys translate_on
+port (
+  HDINP0            : in std_logic;
+  HDINN0            : in std_logic;
+  HDINP1            : in std_logic;
+  HDINN1            : in std_logic;
+  HDINP2            : in std_logic;
+  HDINN2            : in std_logic;
+  HDINP3            : in std_logic;
+  HDINN3            : in std_logic;
+  HDOUTP0           : out std_logic;
+  HDOUTN0           : out std_logic;
+  HDOUTP1           : out std_logic;
+  HDOUTN1           : out std_logic;
+  HDOUTP2           : out std_logic;
+  HDOUTN2           : out std_logic;
+  HDOUTP3           : out std_logic;
+  HDOUTN3           : out std_logic;
+  REFCLKP           : in std_logic;
+  REFCLKN           : in std_logic;
+  RXREFCLKP         : in std_logic;
+  RXREFCLKN         : in std_logic;
+  FFC_QUAD_RST      : in std_logic;
+  FFC_MACRO_RST     : in std_logic;
+
+  FFC_LANE_TX_RST0  : in std_logic;
+  FFC_LANE_TX_RST1  : in std_logic;
+  FFC_LANE_TX_RST2  : in std_logic;
+  FFC_LANE_TX_RST3  : in std_logic;
+
+  FFC_LANE_RX_RST0  : in std_logic;
+  FFC_LANE_RX_RST1  : in std_logic;
+  FFC_LANE_RX_RST2  : in std_logic;
+  FFC_LANE_RX_RST3  : in std_logic;
+
+  FFC_PCIE_EI_EN_0  : in std_logic;
+  FFC_PCIE_EI_EN_1  : in std_logic;
+  FFC_PCIE_EI_EN_2  : in std_logic;
+  FFC_PCIE_EI_EN_3  : in std_logic;
+
+  FFC_PCIE_CT_0     : in std_logic;
+  FFC_PCIE_CT_1     : in std_logic;
+  FFC_PCIE_CT_2     : in std_logic;
+  FFC_PCIE_CT_3     : in std_logic;
+
+  FFS_PCIE_CON_0    : out std_logic;
+  FFS_PCIE_CON_1    : out std_logic;
+  FFS_PCIE_CON_2    : out std_logic;
+  FFS_PCIE_CON_3    : out std_logic;
+
+  FFS_PCIE_DONE_0   : out std_logic;
+  FFS_PCIE_DONE_1   : out std_logic;
+  FFS_PCIE_DONE_2   : out std_logic;
+  FFS_PCIE_DONE_3   : out std_logic;
+
+  FFC_PCIE_TX_0     : in std_logic;
+  FFC_PCIE_TX_1     : in std_logic;
+  FFC_PCIE_TX_2     : in std_logic;
+  FFC_PCIE_TX_3     : in std_logic;
+
+  FFC_PCIE_RX_0     : in std_logic;
+  FFC_PCIE_RX_1     : in std_logic;
+  FFC_PCIE_RX_2     : in std_logic;
+  FFC_PCIE_RX_3     : in std_logic;
+
+  FFC_SD_0          : in std_logic;
+  FFC_SD_1          : in std_logic;
+  FFC_SD_2          : in std_logic;
+  FFC_SD_3          : in std_logic;
+
+  FFC_EN_CGA_0      : in std_logic;
+  FFC_EN_CGA_1      : in std_logic;
+  FFC_EN_CGA_2      : in std_logic;
+  FFC_EN_CGA_3      : in std_logic;
+
+  FFC_ALIGN_EN_0    : in std_logic;
+  FFC_ALIGN_EN_1    : in std_logic;
+  FFC_ALIGN_EN_2    : in std_logic;
+  FFC_ALIGN_EN_3    : in std_logic;
+
+  FFC_AB_RESET      : in std_logic;
+  FFC_CD_RESET      : in std_logic;
+
+  FFS_LS_STATUS_0   : out std_logic;
+  FFS_LS_STATUS_1   : out std_logic;
+  FFS_LS_STATUS_2   : out std_logic;
+  FFS_LS_STATUS_3   : out std_logic;
+
+  FFS_AB_STATUS     : out std_logic;
+  FFS_CD_STATUS     : out std_logic;
+
+  FFS_AB_ALIGNED    : out std_logic;
+  FFS_CD_ALIGNED    : out std_logic;
+
+  FFS_AB_FAILED     : out std_logic;
+  FFS_CD_FAILED     : out std_logic;
+
+  FFS_RLOS_LO0      : out std_logic;
+  FFS_RLOS_LO1      : out std_logic;
+  FFS_RLOS_LO2      : out std_logic;
+  FFS_RLOS_LO3      : out std_logic;
+
+  FFC_FB_LB_0       : in std_logic;
+  FFC_FB_LB_1       : in std_logic;
+  FFC_FB_LB_2       : in std_logic;
+  FFC_FB_LB_3       : in std_logic;
+
+  FFC_SB_INV_RX_0   : in std_logic;
+  FFC_SB_INV_RX_1   : in std_logic;
+  FFC_SB_INV_RX_2   : in std_logic;
+  FFC_SB_INV_RX_3   : in std_logic;
+
+  FFS_CC_ORUN_0     : out std_logic;
+  FFS_CC_ORUN_1     : out std_logic;
+  FFS_CC_ORUN_2     : out std_logic;
+  FFS_CC_ORUN_3     : out std_logic;
+
+  FFS_CC_URUN_0     : out std_logic;
+  FFS_CC_URUN_1     : out std_logic;
+  FFS_CC_URUN_2     : out std_logic;
+  FFS_CC_URUN_3     : out std_logic;
+
+  FFC_CK_CORE_TX    : in std_logic;
+  FFC_CK_CORE_RX    : in std_logic;
+  RDATAO_7          : out std_logic;
+  RDATAO_6          : out std_logic;
+  RDATAO_5          : out std_logic;
+  RDATAO_4          : out std_logic;
+  RDATAO_3          : out std_logic;
+  RDATAO_2          : out std_logic;
+  RDATAO_1          : out std_logic;
+  RDATAO_0          : out std_logic;
+  INTO              : out std_logic;
+
+  ADDRI_7           : in std_logic;
+  ADDRI_6           : in std_logic;
+  ADDRI_5           : in std_logic;
+  ADDRI_4           : in std_logic;
+  ADDRI_3           : in std_logic;
+  ADDRI_2           : in std_logic;
+  ADDRI_1           : in std_logic;
+  ADDRI_0           : in std_logic;
+  WDATAI_7          : in std_logic;
+  WDATAI_6          : in std_logic;
+  WDATAI_5          : in std_logic;
+  WDATAI_4          : in std_logic;
+  WDATAI_3          : in std_logic;
+  WDATAI_2          : in std_logic;
+  WDATAI_1          : in std_logic;
+  WDATAI_0          : in std_logic;
+  RDI               : in std_logic;
+  WSTBI             : in std_logic;
+
+  CS_CHIF_0         : in std_logic;
+  CS_CHIF_1         : in std_logic;
+  CS_CHIF_2         : in std_logic;
+  CS_CHIF_3         : in std_logic;
+  CS_QIF            : in std_logic;
+
+  QUAD_ID_1         : in std_logic;
+  QUAD_ID_0         : in std_logic;
+
+  FF_SYSCLK_P1      : out std_logic;
+
+  FF_SYSCLK0        : out std_logic;
+  FF_SYSCLK1        : out std_logic;
+  FF_SYSCLK2        : out std_logic;
+  FF_SYSCLK3        : out std_logic;
+
+  FF_RXCLK_P1       : out std_logic;
+  FF_RXCLK_P2       : out std_logic;
+
+  FF_RXCLK0         : out std_logic;
+  FF_RXCLK1         : out std_logic;
+  FF_RXCLK2         : out std_logic;
+  FF_RXCLK3         : out std_logic;
+
+  QUAD_CLK          : out std_logic;
+
+  GRP_CLK_P1_3      : in std_logic;
+  GRP_CLK_P1_2      : in std_logic;
+  GRP_CLK_P1_1      : in std_logic;
+  GRP_CLK_P1_0      : in std_logic;
+
+  GRP_CLK_P2_3      : in std_logic;
+  GRP_CLK_P2_2      : in std_logic;
+  GRP_CLK_P2_1      : in std_logic;
+  GRP_CLK_P2_0      : in std_logic;
+
+  GRP_START_3      : in std_logic;
+  GRP_START_2      : in std_logic;
+  GRP_START_1      : in std_logic;
+  GRP_START_0      : in std_logic;
+
+  GRP_DONE_3      : in std_logic;
+  GRP_DONE_2      : in std_logic;
+  GRP_DONE_1      : in std_logic;
+  GRP_DONE_0      : in std_logic;
+
+  GRP_DESKEW_ERROR_3      : in std_logic;
+  GRP_DESKEW_ERROR_2      : in std_logic;
+  GRP_DESKEW_ERROR_1      : in std_logic;
+  GRP_DESKEW_ERROR_0      : in std_logic;
+
+  IQA_START_LS      : out std_logic;
+  IQA_DONE_LS       : out std_logic;
+  IQA_AND_FP1_LS    : out std_logic;
+  IQA_AND_FP0_LS    : out std_logic;
+  IQA_OR_FP1_LS     : out std_logic;
+  IQA_OR_FP0_LS     : out std_logic;
+  IQA_RST_N         : out std_logic;
+
+  FF_TCLK0          : in std_logic;
+  FF_TCLK1          : in std_logic;
+  FF_TCLK2          : in std_logic;
+  FF_TCLK3          : in std_logic;
+
+  FF_RCLK0          : in std_logic;
+  FF_RCLK1          : in std_logic;
+  FF_RCLK2          : in std_logic;
+  FF_RCLK3          : in std_logic;
+  TCK_FMACP         : in std_logic;
+
+  FF_TXD_0_23       : in std_logic;
+  FF_TXD_0_22       : in std_logic;
+  FF_TXD_0_21       : in std_logic;
+  FF_TXD_0_20       : in std_logic;
+  FF_TXD_0_19       : in std_logic;
+  FF_TXD_0_18       : in std_logic;
+  FF_TXD_0_17       : in std_logic;
+  FF_TXD_0_16       : in std_logic;
+  FF_TXD_0_15       : in std_logic;
+  FF_TXD_0_14       : in std_logic;
+  FF_TXD_0_13       : in std_logic;
+  FF_TXD_0_12       : in std_logic;
+  FF_TXD_0_11       : in std_logic;
+  FF_TXD_0_10       : in std_logic;
+  FF_TXD_0_9       : in std_logic;
+  FF_TXD_0_8       : in std_logic;
+  FF_TXD_0_7       : in std_logic;
+  FF_TXD_0_6       : in std_logic;
+  FF_TXD_0_5       : in std_logic;
+  FF_TXD_0_4       : in std_logic;
+  FF_TXD_0_3       : in std_logic;
+  FF_TXD_0_2       : in std_logic;
+  FF_TXD_0_1       : in std_logic;
+  FF_TXD_0_0       : in std_logic;
+  FB_RXD_0_23       : out std_logic;
+  FB_RXD_0_22       : out std_logic;
+  FB_RXD_0_21       : out std_logic;
+  FB_RXD_0_20       : out std_logic;
+  FB_RXD_0_19       : out std_logic;
+  FB_RXD_0_18       : out std_logic;
+  FB_RXD_0_17       : out std_logic;
+  FB_RXD_0_16       : out std_logic;
+  FB_RXD_0_15       : out std_logic;
+  FB_RXD_0_14       : out std_logic;
+  FB_RXD_0_13       : out std_logic;
+  FB_RXD_0_12       : out std_logic;
+  FB_RXD_0_11       : out std_logic;
+  FB_RXD_0_10       : out std_logic;
+  FB_RXD_0_9       : out std_logic;
+  FB_RXD_0_8       : out std_logic;
+  FB_RXD_0_7       : out std_logic;
+  FB_RXD_0_6       : out std_logic;
+  FB_RXD_0_5       : out std_logic;
+  FB_RXD_0_4       : out std_logic;
+  FB_RXD_0_3       : out std_logic;
+  FB_RXD_0_2       : out std_logic;
+  FB_RXD_0_1       : out std_logic;
+  FB_RXD_0_0       : out std_logic;
+  FF_TXD_1_23       : in std_logic;
+  FF_TXD_1_22       : in std_logic;
+  FF_TXD_1_21       : in std_logic;
+  FF_TXD_1_20       : in std_logic;
+  FF_TXD_1_19       : in std_logic;
+  FF_TXD_1_18       : in std_logic;
+  FF_TXD_1_17       : in std_logic;
+  FF_TXD_1_16       : in std_logic;
+  FF_TXD_1_15       : in std_logic;
+  FF_TXD_1_14       : in std_logic;
+  FF_TXD_1_13       : in std_logic;
+  FF_TXD_1_12       : in std_logic;
+  FF_TXD_1_11       : in std_logic;
+  FF_TXD_1_10       : in std_logic;
+  FF_TXD_1_9       : in std_logic;
+  FF_TXD_1_8       : in std_logic;
+  FF_TXD_1_7       : in std_logic;
+  FF_TXD_1_6       : in std_logic;
+  FF_TXD_1_5       : in std_logic;
+  FF_TXD_1_4       : in std_logic;
+  FF_TXD_1_3       : in std_logic;
+  FF_TXD_1_2       : in std_logic;
+  FF_TXD_1_1       : in std_logic;
+  FF_TXD_1_0       : in std_logic;
+  FB_RXD_1_23       : out std_logic;
+  FB_RXD_1_22       : out std_logic;
+  FB_RXD_1_21       : out std_logic;
+  FB_RXD_1_20       : out std_logic;
+  FB_RXD_1_19       : out std_logic;
+  FB_RXD_1_18       : out std_logic;
+  FB_RXD_1_17       : out std_logic;
+  FB_RXD_1_16       : out std_logic;
+  FB_RXD_1_15       : out std_logic;
+  FB_RXD_1_14       : out std_logic;
+  FB_RXD_1_13       : out std_logic;
+  FB_RXD_1_12       : out std_logic;
+  FB_RXD_1_11       : out std_logic;
+  FB_RXD_1_10       : out std_logic;
+  FB_RXD_1_9       : out std_logic;
+  FB_RXD_1_8       : out std_logic;
+  FB_RXD_1_7       : out std_logic;
+  FB_RXD_1_6       : out std_logic;
+  FB_RXD_1_5       : out std_logic;
+  FB_RXD_1_4       : out std_logic;
+  FB_RXD_1_3       : out std_logic;
+  FB_RXD_1_2       : out std_logic;
+  FB_RXD_1_1       : out std_logic;
+  FB_RXD_1_0       : out std_logic;
+  FF_TXD_2_23       : in std_logic;
+  FF_TXD_2_22       : in std_logic;
+  FF_TXD_2_21       : in std_logic;
+  FF_TXD_2_20       : in std_logic;
+  FF_TXD_2_19       : in std_logic;
+  FF_TXD_2_18       : in std_logic;
+  FF_TXD_2_17       : in std_logic;
+  FF_TXD_2_16       : in std_logic;
+  FF_TXD_2_15       : in std_logic;
+  FF_TXD_2_14       : in std_logic;
+  FF_TXD_2_13       : in std_logic;
+  FF_TXD_2_12       : in std_logic;
+  FF_TXD_2_11       : in std_logic;
+  FF_TXD_2_10       : in std_logic;
+  FF_TXD_2_9       : in std_logic;
+  FF_TXD_2_8       : in std_logic;
+  FF_TXD_2_7       : in std_logic;
+  FF_TXD_2_6       : in std_logic;
+  FF_TXD_2_5       : in std_logic;
+  FF_TXD_2_4       : in std_logic;
+  FF_TXD_2_3       : in std_logic;
+  FF_TXD_2_2       : in std_logic;
+  FF_TXD_2_1       : in std_logic;
+  FF_TXD_2_0       : in std_logic;
+  FB_RXD_2_23       : out std_logic;
+  FB_RXD_2_22       : out std_logic;
+  FB_RXD_2_21       : out std_logic;
+  FB_RXD_2_20       : out std_logic;
+  FB_RXD_2_19       : out std_logic;
+  FB_RXD_2_18       : out std_logic;
+  FB_RXD_2_17       : out std_logic;
+  FB_RXD_2_16       : out std_logic;
+  FB_RXD_2_15       : out std_logic;
+  FB_RXD_2_14       : out std_logic;
+  FB_RXD_2_13       : out std_logic;
+  FB_RXD_2_12       : out std_logic;
+  FB_RXD_2_11       : out std_logic;
+  FB_RXD_2_10       : out std_logic;
+  FB_RXD_2_9       : out std_logic;
+  FB_RXD_2_8       : out std_logic;
+  FB_RXD_2_7       : out std_logic;
+  FB_RXD_2_6       : out std_logic;
+  FB_RXD_2_5       : out std_logic;
+  FB_RXD_2_4       : out std_logic;
+  FB_RXD_2_3       : out std_logic;
+  FB_RXD_2_2       : out std_logic;
+  FB_RXD_2_1       : out std_logic;
+  FB_RXD_2_0       : out std_logic;
+  FF_TXD_3_23       : in std_logic;
+  FF_TXD_3_22       : in std_logic;
+  FF_TXD_3_21       : in std_logic;
+  FF_TXD_3_20       : in std_logic;
+  FF_TXD_3_19       : in std_logic;
+  FF_TXD_3_18       : in std_logic;
+  FF_TXD_3_17       : in std_logic;
+  FF_TXD_3_16       : in std_logic;
+  FF_TXD_3_15       : in std_logic;
+  FF_TXD_3_14       : in std_logic;
+  FF_TXD_3_13       : in std_logic;
+  FF_TXD_3_12       : in std_logic;
+  FF_TXD_3_11       : in std_logic;
+  FF_TXD_3_10       : in std_logic;
+  FF_TXD_3_9       : in std_logic;
+  FF_TXD_3_8       : in std_logic;
+  FF_TXD_3_7       : in std_logic;
+  FF_TXD_3_6       : in std_logic;
+  FF_TXD_3_5       : in std_logic;
+  FF_TXD_3_4       : in std_logic;
+  FF_TXD_3_3       : in std_logic;
+  FF_TXD_3_2       : in std_logic;
+  FF_TXD_3_1       : in std_logic;
+  FF_TXD_3_0       : in std_logic;
+  FB_RXD_3_23       : out std_logic;
+  FB_RXD_3_22       : out std_logic;
+  FB_RXD_3_21       : out std_logic;
+  FB_RXD_3_20       : out std_logic;
+  FB_RXD_3_19       : out std_logic;
+  FB_RXD_3_18       : out std_logic;
+  FB_RXD_3_17       : out std_logic;
+  FB_RXD_3_16       : out std_logic;
+  FB_RXD_3_15       : out std_logic;
+  FB_RXD_3_14       : out std_logic;
+  FB_RXD_3_13       : out std_logic;
+  FB_RXD_3_12       : out std_logic;
+  FB_RXD_3_11       : out std_logic;
+  FB_RXD_3_10       : out std_logic;
+  FB_RXD_3_9       : out std_logic;
+  FB_RXD_3_8       : out std_logic;
+  FB_RXD_3_7       : out std_logic;
+  FB_RXD_3_6       : out std_logic;
+  FB_RXD_3_5       : out std_logic;
+  FB_RXD_3_4       : out std_logic;
+  FB_RXD_3_3       : out std_logic;
+  FB_RXD_3_2       : out std_logic;
+  FB_RXD_3_1       : out std_logic;
+  FB_RXD_3_0       : out std_logic;
+  TCK_FMAC         : out std_logic;
+  BS4PAD_0         : out std_logic;
+  BS4PAD_1         : out std_logic;
+  BS4PAD_2         : out std_logic;
+  BS4PAD_3         : out std_logic;
+  COUT_21          : out std_logic;
+  COUT_20          : out std_logic;
+  COUT_19          : out std_logic;
+  COUT_18          : out std_logic;
+  COUT_17          : out std_logic;
+  COUT_16          : out std_logic;
+  COUT_15          : out std_logic;
+  COUT_14          : out std_logic;
+  COUT_13          : out std_logic;
+  COUT_12          : out std_logic;
+  COUT_11          : out std_logic;
+  COUT_10          : out std_logic;
+  COUT_9           : out std_logic;
+  COUT_8           : out std_logic;
+  COUT_7           : out std_logic;
+  COUT_6           : out std_logic;
+  COUT_5           : out std_logic;
+  COUT_4           : out std_logic;
+  COUT_3           : out std_logic;
+  COUT_2           : out std_logic;
+  COUT_1           : out std_logic;
+  COUT_0           : out std_logic;
+  CIN_12          : in std_logic;
+  CIN_11          : in std_logic;
+  CIN_10          : in std_logic;
+  CIN_9           : in std_logic;
+  CIN_8           : in std_logic;
+  CIN_7           : in std_logic;
+  CIN_6           : in std_logic;
+  CIN_5           : in std_logic;
+  CIN_4           : in std_logic;
+  CIN_3           : in std_logic;
+  CIN_2           : in std_logic;
+  CIN_1           : in std_logic;
+  CIN_0           : in std_logic;
+  TESTCLK_MACO     : in std_logic
+);
+end component;
+   attribute IS_ASB: string;
+   attribute IS_ASB of PCSA_INST : label is "or5s00/data/or5s00.acd";
+   attribute CONFIG_FILE: string;
+   attribute CONFIG_FILE of PCSA_INST : label is USER_CONFIG_FILE;
+   attribute CH0_RX_MAXRATE: string;
+   attribute CH0_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH1_RX_MAXRATE: string;
+   attribute CH1_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH2_RX_MAXRATE: string;
+   attribute CH2_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH3_RX_MAXRATE: string;
+   attribute CH3_RX_MAXRATE of PCSA_INST : label is "RXF3";
+   attribute CH0_TX_MAXRATE: string;
+   attribute CH0_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH1_TX_MAXRATE: string;
+   attribute CH1_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH2_TX_MAXRATE: string;
+   attribute CH2_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute CH3_TX_MAXRATE: string;
+   attribute CH3_TX_MAXRATE of PCSA_INST : label is "TXF2";
+   attribute AMP_BOOST: string;
+   attribute AMP_BOOST of PCSA_INST : label is "DISABLED";
+   attribute black_box_pad_pin: string;
+   attribute black_box_pad_pin of PCSA : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN, RXREFCLKP, RXREFCLKN";
+
+signal fpsc_vlo : std_logic := '0';
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+
+-- pcs_quad instance
+PCSA_INST : PCSA
+--synopsys translate_off
+  generic map (CONFIG_FILE => USER_CONFIG_FILE)
+--synopsys translate_on
+port map  ( 
+  REFCLKP => refclkp,
+  REFCLKN => refclkn,
+  RXREFCLKP => fpsc_vlo,
+  RXREFCLKN => fpsc_vlo,
+  FFC_CK_CORE_RX => rxrefclk,
+  FFC_CK_CORE_TX => refclk,
+  CS_CHIF_0 => fpsc_vlo,
+  CS_CHIF_1 => fpsc_vlo,
+  CS_CHIF_2 => fpsc_vlo,
+  CS_CHIF_3 => fpsc_vlo,
+  CS_QIF => fpsc_vlo,
+  QUAD_ID_0 => fpsc_vlo,
+  QUAD_ID_1 => fpsc_vlo,
+  ADDRI_0 => fpsc_vlo,
+  ADDRI_1 => fpsc_vlo,
+  ADDRI_2 => fpsc_vlo,
+  ADDRI_3 => fpsc_vlo,
+  ADDRI_4 => fpsc_vlo,
+  ADDRI_5 => fpsc_vlo,
+  ADDRI_6 => fpsc_vlo,
+  ADDRI_7 => fpsc_vlo,
+  WDATAI_0 => fpsc_vlo,
+  WDATAI_1 => fpsc_vlo,
+  WDATAI_2 => fpsc_vlo,
+  WDATAI_3 => fpsc_vlo,
+  WDATAI_4 => fpsc_vlo,
+  WDATAI_5 => fpsc_vlo,
+  WDATAI_6 => fpsc_vlo,
+  WDATAI_7 => fpsc_vlo,
+  RDI => fpsc_vlo,
+  WSTBI => fpsc_vlo,
+  GRP_CLK_P1_0 => fpsc_vlo,
+  GRP_CLK_P1_1 => fpsc_vlo,
+  GRP_CLK_P1_2 => fpsc_vlo,
+  GRP_CLK_P1_3 => fpsc_vlo,
+  GRP_CLK_P2_0 => fpsc_vlo,
+  GRP_CLK_P2_1 => fpsc_vlo,
+  GRP_CLK_P2_2 => fpsc_vlo,
+  GRP_CLK_P2_3 => fpsc_vlo,
+  GRP_START_0 => fpsc_vlo,
+  GRP_START_1 => fpsc_vlo,
+  GRP_START_2 => fpsc_vlo,
+  GRP_START_3 => fpsc_vlo,
+  GRP_DONE_0 => fpsc_vlo,
+  GRP_DONE_1 => fpsc_vlo,
+  GRP_DONE_2 => fpsc_vlo,
+  GRP_DONE_3 => fpsc_vlo,
+  GRP_DESKEW_ERROR_0 => fpsc_vlo,
+  GRP_DESKEW_ERROR_1 => fpsc_vlo,
+  GRP_DESKEW_ERROR_2 => fpsc_vlo,
+  GRP_DESKEW_ERROR_3 => fpsc_vlo,
+-- to sysbusa
+  RDATAO_0 => open,
+  RDATAO_1 => open,
+  RDATAO_2 => open,
+  RDATAO_3 => open,
+  RDATAO_4 => open,
+  RDATAO_5 => open,
+  RDATAO_6 => open,
+  RDATAO_7 => open,
+  INTO => open,
+  QUAD_CLK => open,
+  IQA_START_LS => open,
+  IQA_DONE_LS => open,
+  IQA_AND_FP1_LS => open,
+  IQA_AND_FP0_LS => open,
+  IQA_OR_FP1_LS => open,
+  IQA_OR_FP0_LS => open,
+  IQA_RST_N => open,
+
+  FF_TXD_0_19 => txd_0(15),
+  FF_TXD_0_18 => txd_0(14),
+  FF_TXD_0_17 => txd_0(13),
+  FF_TXD_0_16 => txd_0(12),
+  FF_TXD_0_15 => txd_0(11),
+  FF_TXD_0_14 => txd_0(10),
+  FF_TXD_0_13 => txd_0(9),
+  FF_TXD_0_12 => txd_0(8),
+  FF_TXD_0_7 => txd_0(7),
+  FF_TXD_0_6 => txd_0(6),
+  FF_TXD_0_5 => txd_0(5),
+  FF_TXD_0_4 => txd_0(4),
+  FF_TXD_0_3 => txd_0(3),
+  FF_TXD_0_2 => txd_0(2),
+  FF_TXD_0_1 => txd_0(1),
+  FF_TXD_0_0 => txd_0(0),
+  FB_RXD_0_19 => rxd_0(15),
+  FB_RXD_0_18 => rxd_0(14),
+  FB_RXD_0_17 => rxd_0(13),
+  FB_RXD_0_16 => rxd_0(12),
+  FB_RXD_0_15 => rxd_0(11),
+  FB_RXD_0_14 => rxd_0(10),
+  FB_RXD_0_13 => rxd_0(9),
+  FB_RXD_0_12 => rxd_0(8),
+  FB_RXD_0_7 => rxd_0(7),
+  FB_RXD_0_6 => rxd_0(6),
+  FB_RXD_0_5 => rxd_0(5),
+  FB_RXD_0_4 => rxd_0(4),
+  FB_RXD_0_3 => rxd_0(3),
+  FB_RXD_0_2 => rxd_0(2),
+  FB_RXD_0_1 => rxd_0(1),
+  FB_RXD_0_0 => rxd_0(0),
+
+  FF_TXD_0_20 => tx_k_0(1),
+  FF_TXD_0_8 => tx_k_0(0),
+  FB_RXD_0_20 => rx_k_0(1),
+  FB_RXD_0_8 => rx_k_0(0),
+
+  FF_TXD_0_21 => tx_force_disp_0(1),
+  FF_TXD_0_9 => tx_force_disp_0(0),
+
+  FF_TXD_0_22 => tx_disp_sel_0(1),
+  FF_TXD_0_10 => tx_disp_sel_0(0),
+
+  FF_TXD_0_23 => tx_crc_init_0(1),
+  FF_TXD_0_11 => tx_crc_init_0(0),
+
+  FB_RXD_0_21 => rx_disp_err_detect_0(1),
+  FB_RXD_0_9 => rx_disp_err_detect_0(0),
+
+  FB_RXD_0_22 => rx_cv_detect_0(1),
+  FB_RXD_0_10 => rx_cv_detect_0(0),
+
+  FB_RXD_0_23 => rx_crc_eop_0(1),
+  FB_RXD_0_11 => rx_crc_eop_0(0),
+
+  FF_TXD_1_19 => fpsc_vlo,
+  FF_TXD_1_18 => fpsc_vlo,
+  FF_TXD_1_17 => fpsc_vlo,
+  FF_TXD_1_16 => fpsc_vlo,
+  FF_TXD_1_15 => fpsc_vlo,
+  FF_TXD_1_14 => fpsc_vlo,
+  FF_TXD_1_13 => fpsc_vlo,
+  FF_TXD_1_12 => fpsc_vlo,
+  FF_TXD_1_7 => fpsc_vlo,
+  FF_TXD_1_6 => fpsc_vlo,
+  FF_TXD_1_5 => fpsc_vlo,
+  FF_TXD_1_4 => fpsc_vlo,
+  FF_TXD_1_3 => fpsc_vlo,
+  FF_TXD_1_2 => fpsc_vlo,
+  FF_TXD_1_1 => fpsc_vlo,
+  FF_TXD_1_0 => fpsc_vlo,
+  FB_RXD_1_19 => open,
+  FB_RXD_1_18 => open,
+  FB_RXD_1_17 => open,
+  FB_RXD_1_16 => open,
+  FB_RXD_1_15 => open,
+  FB_RXD_1_14 => open,
+  FB_RXD_1_13 => open,
+  FB_RXD_1_12 => open,
+  FB_RXD_1_7 => open,
+  FB_RXD_1_6 => open,
+  FB_RXD_1_5 => open,
+  FB_RXD_1_4 => open,
+  FB_RXD_1_3 => open,
+  FB_RXD_1_2 => open,
+  FB_RXD_1_1 => open,
+  FB_RXD_1_0 => open,
+
+  FF_TXD_1_20 => fpsc_vlo,
+  FF_TXD_1_8 => fpsc_vlo,
+  FB_RXD_1_20 => open,
+  FB_RXD_1_8 => open,
+
+  FF_TXD_1_21 => fpsc_vlo,
+  FF_TXD_1_9 => fpsc_vlo,
+
+  FF_TXD_1_22 => fpsc_vlo,
+  FF_TXD_1_10 => fpsc_vlo,
+  FF_TXD_1_23 => fpsc_vlo,
+  FF_TXD_1_11 => fpsc_vlo,
+
+  FB_RXD_1_21 => open,
+  FB_RXD_1_9 => open,
+
+  FB_RXD_1_22 => open,
+  FB_RXD_1_10 => open,
+
+  FB_RXD_1_23 => open,
+  FB_RXD_1_11 => open,
+
+  FF_TXD_2_19 => fpsc_vlo,
+  FF_TXD_2_18 => fpsc_vlo,
+  FF_TXD_2_17 => fpsc_vlo,
+  FF_TXD_2_16 => fpsc_vlo,
+  FF_TXD_2_15 => fpsc_vlo,
+  FF_TXD_2_14 => fpsc_vlo,
+  FF_TXD_2_13 => fpsc_vlo,
+  FF_TXD_2_12 => fpsc_vlo,
+  FF_TXD_2_7 => fpsc_vlo,
+  FF_TXD_2_6 => fpsc_vlo,
+  FF_TXD_2_5 => fpsc_vlo,
+  FF_TXD_2_4 => fpsc_vlo,
+  FF_TXD_2_3 => fpsc_vlo,
+  FF_TXD_2_2 => fpsc_vlo,
+  FF_TXD_2_1 => fpsc_vlo,
+  FF_TXD_2_0 => fpsc_vlo,
+  FB_RXD_2_19 => open,
+  FB_RXD_2_18 => open,
+  FB_RXD_2_17 => open,
+  FB_RXD_2_16 => open,
+  FB_RXD_2_15 => open,
+  FB_RXD_2_14 => open,
+  FB_RXD_2_13 => open,
+  FB_RXD_2_12 => open,
+  FB_RXD_2_7 => open,
+  FB_RXD_2_6 => open,
+  FB_RXD_2_5 => open,
+  FB_RXD_2_4 => open,
+  FB_RXD_2_3 => open,
+  FB_RXD_2_2 => open,
+  FB_RXD_2_1 => open,
+  FB_RXD_2_0 => open,
+
+  FF_TXD_2_20 => fpsc_vlo,
+  FF_TXD_2_8 => fpsc_vlo,
+  FB_RXD_2_20 => open,
+  FB_RXD_2_8 => open,
+
+  FF_TXD_2_21 => fpsc_vlo,
+  FF_TXD_2_9 => fpsc_vlo,
+
+  FF_TXD_2_22 => fpsc_vlo,
+  FF_TXD_2_10 => fpsc_vlo,
+  FF_TXD_2_23 => fpsc_vlo,
+  FF_TXD_2_11 => fpsc_vlo,
+
+  FB_RXD_2_21 => open,
+  FB_RXD_2_9 => open,
+
+  FB_RXD_2_22 => open,
+  FB_RXD_2_10 => open,
+
+  FB_RXD_2_23 => open,
+  FB_RXD_2_11 => open,
+
+  FF_TXD_3_19 => fpsc_vlo,
+  FF_TXD_3_18 => fpsc_vlo,
+  FF_TXD_3_17 => fpsc_vlo,
+  FF_TXD_3_16 => fpsc_vlo,
+  FF_TXD_3_15 => fpsc_vlo,
+  FF_TXD_3_14 => fpsc_vlo,
+  FF_TXD_3_13 => fpsc_vlo,
+  FF_TXD_3_12 => fpsc_vlo,
+  FF_TXD_3_7 => fpsc_vlo,
+  FF_TXD_3_6 => fpsc_vlo,
+  FF_TXD_3_5 => fpsc_vlo,
+  FF_TXD_3_4 => fpsc_vlo,
+  FF_TXD_3_3 => fpsc_vlo,
+  FF_TXD_3_2 => fpsc_vlo,
+  FF_TXD_3_1 => fpsc_vlo,
+  FF_TXD_3_0 => fpsc_vlo,
+  FB_RXD_3_19 => open,
+  FB_RXD_3_18 => open,
+  FB_RXD_3_17 => open,
+  FB_RXD_3_16 => open,
+  FB_RXD_3_15 => open,
+  FB_RXD_3_14 => open,
+  FB_RXD_3_13 => open,
+  FB_RXD_3_12 => open,
+  FB_RXD_3_7 => open,
+  FB_RXD_3_6 => open,
+  FB_RXD_3_5 => open,
+  FB_RXD_3_4 => open,
+  FB_RXD_3_3 => open,
+  FB_RXD_3_2 => open,
+  FB_RXD_3_1 => open,
+  FB_RXD_3_0 => open,
+
+  FF_TXD_3_20 => fpsc_vlo,
+  FF_TXD_3_8 => fpsc_vlo,
+  FB_RXD_3_20 => open,
+  FB_RXD_3_8 => open,
+
+  FF_TXD_3_21 => fpsc_vlo,
+  FF_TXD_3_9 => fpsc_vlo,
+
+  FF_TXD_3_22 => fpsc_vlo,
+  FF_TXD_3_10 => fpsc_vlo,
+  FF_TXD_3_23 => fpsc_vlo,
+  FF_TXD_3_11 => fpsc_vlo,
+
+  FB_RXD_3_21 => open,
+  FB_RXD_3_9 => open,
+
+  FB_RXD_3_22 => open,
+  FB_RXD_3_10 => open,
+
+  FB_RXD_3_23 => open,
+  FB_RXD_3_11 => open,
+
+  HDINP0 => hdinp_0,
+  HDINN0 => hdinn_0,
+  HDOUTP0 => hdoutp_0,
+  HDOUTN0 => hdoutn_0,
+  FF_SYSCLK0 => ref_0_sclk,
+  FF_RXCLK0 => rx_0_sclk,
+  FFC_LANE_TX_RST0 => tx_rst_0,
+  FFC_LANE_RX_RST0 => rx_rst_0,
+  FF_TCLK0 => tclk_0,
+  FF_RCLK0 => rclk_0,
+  HDINP1 => fpsc_vlo,
+  HDINN1 => fpsc_vlo,
+  HDOUTP1 => open,
+  HDOUTN1 => open,
+  FF_SYSCLK1 => open,
+  FF_RXCLK1 => open,
+  FFC_LANE_TX_RST1 => fpsc_vlo,
+  FFC_LANE_RX_RST1 => fpsc_vlo,
+  FF_TCLK1 => fpsc_vlo,
+  FF_RCLK1 => fpsc_vlo,
+  HDINP2 => fpsc_vlo,
+  HDINN2 => fpsc_vlo,
+  HDOUTP2 => open,
+  HDOUTN2 => open,
+  FF_SYSCLK2 => open,
+  FF_RXCLK2 => open,
+  FFC_LANE_TX_RST2 => fpsc_vlo,
+  FFC_LANE_RX_RST2 => fpsc_vlo,
+  FF_TCLK2 => fpsc_vlo,
+  FF_RCLK2 => fpsc_vlo,
+  HDINP3 => fpsc_vlo,
+  HDINN3 => fpsc_vlo,
+  HDOUTP3 => open,
+  HDOUTN3 => open,
+  FF_SYSCLK3 => open,
+  FF_RXCLK3 => open,
+  FFC_LANE_TX_RST3 => fpsc_vlo,
+  FFC_LANE_RX_RST3 => fpsc_vlo,
+  FF_TCLK3 => fpsc_vlo,
+  FF_RCLK3 => fpsc_vlo,
+
+  FFC_PCIE_EI_EN_0 => fpsc_vlo,
+  FFC_PCIE_CT_0 => fpsc_vlo,
+  FFC_PCIE_TX_0 => fpsc_vlo,
+  FFC_PCIE_RX_0 => fpsc_vlo,
+  FFS_PCIE_CON_0 => open,
+  FFS_PCIE_DONE_0 => open,
+  FFC_PCIE_EI_EN_1 => fpsc_vlo,
+  FFC_PCIE_CT_1 => fpsc_vlo,
+  FFC_PCIE_TX_1 => fpsc_vlo,
+  FFC_PCIE_RX_1 => fpsc_vlo,
+  FFS_PCIE_CON_1 => open,
+  FFS_PCIE_DONE_1 => open,
+  FFC_PCIE_EI_EN_2 => fpsc_vlo,
+  FFC_PCIE_CT_2 => fpsc_vlo,
+  FFC_PCIE_TX_2 => fpsc_vlo,
+  FFC_PCIE_RX_2 => fpsc_vlo,
+  FFS_PCIE_CON_2 => open,
+  FFS_PCIE_DONE_2 => open,
+  FFC_PCIE_EI_EN_3 => fpsc_vlo,
+  FFC_PCIE_CT_3 => fpsc_vlo,
+  FFC_PCIE_TX_3 => fpsc_vlo,
+  FFC_PCIE_RX_3 => fpsc_vlo,
+  FFS_PCIE_CON_3 => open,
+  FFS_PCIE_DONE_3 => open,
+
+  FFC_SD_0 => lsm_en_0,
+  FFC_SD_1 => fpsc_vlo,
+  FFC_SD_2 => fpsc_vlo,
+  FFC_SD_3 => fpsc_vlo,
+
+  FFC_EN_CGA_0 => word_align_en_0,
+  FFC_EN_CGA_1 => fpsc_vlo,
+  FFC_EN_CGA_2 => fpsc_vlo,
+  FFC_EN_CGA_3 => fpsc_vlo,
+
+  FFC_ALIGN_EN_0 => mca_align_en_0,
+  FFC_ALIGN_EN_1 => fpsc_vlo,
+  FFC_ALIGN_EN_2 => fpsc_vlo,
+  FFC_ALIGN_EN_3 => fpsc_vlo,
+
+  FFC_FB_LB_0 => felb_0,
+  FFC_FB_LB_1 => fpsc_vlo,
+  FFC_FB_LB_2 => fpsc_vlo,
+  FFC_FB_LB_3 => fpsc_vlo,
+
+  FFS_LS_STATUS_0 => lsm_status_0,
+  FFS_LS_STATUS_1 => open,
+  FFS_LS_STATUS_2 => open,
+  FFS_LS_STATUS_3 => open,
+
+  FFS_CC_ORUN_0 => open,
+  FFS_CC_URUN_0 => open,
+  FFS_CC_ORUN_1 => open,
+  FFS_CC_URUN_1 => open,
+  FFS_CC_ORUN_2 => open,
+  FFS_CC_URUN_2 => open,
+  FFS_CC_ORUN_3 => open,
+  FFS_CC_URUN_3 => open,
+
+  FFC_AB_RESET => mca_resync_01,
+
+  FFS_AB_STATUS => open,
+  FFS_AB_ALIGNED => open,
+  FFS_AB_FAILED => open,
+
+  FFC_CD_RESET => fpsc_vlo,
+  FFS_CD_STATUS => open,
+
+  FFS_CD_ALIGNED => open,
+  FFS_CD_FAILED => open,
+  BS4PAD_0 => open,
+  BS4PAD_1 => open,
+  BS4PAD_2 => open,
+  BS4PAD_3 => open,
+  FFC_SB_INV_RX_0 => fpsc_vlo,
+  FFC_SB_INV_RX_1 => fpsc_vlo,
+  FFC_SB_INV_RX_2 => fpsc_vlo,
+  FFC_SB_INV_RX_3 => fpsc_vlo,
+  TCK_FMAC => open,
+  TCK_FMACP => fpsc_vlo,
+  FF_SYSCLK_P1 => ref_pclk,
+  FF_RXCLK_P1 => rxa_pclk,
+  FF_RXCLK_P2 => rxb_pclk,
+  FFC_QUAD_RST => quad_rst,
+  FFS_RLOS_LO0 => open,
+  FFS_RLOS_LO1 => open,
+  FFS_RLOS_LO2 => open,
+  FFS_RLOS_LO3 => open,
+  COUT_21 => open,
+  COUT_20 => open,
+  COUT_19 => open,
+  COUT_18 => open,
+  COUT_17 => open,
+  COUT_16 => open,
+  COUT_15 => open,
+  COUT_14 => open,
+  COUT_13 => open,
+  COUT_12 => open,
+  COUT_11 => open,
+  COUT_10 => open,
+  COUT_9 => open,
+  COUT_8 => open,
+  COUT_7 => open,
+  COUT_6 => open,
+  COUT_5 => open,
+  COUT_4 => open,
+  COUT_3 => open,
+  COUT_2 => open,
+  COUT_1 => open,
+  COUT_0 => open,
+  CIN_12 => fpsc_vlo,
+  CIN_11 => fpsc_vlo,
+  CIN_10 => fpsc_vlo,
+  CIN_9 => fpsc_vlo,
+  CIN_8 => fpsc_vlo,
+  CIN_7 => fpsc_vlo,
+  CIN_6 => fpsc_vlo,
+  CIN_5 => fpsc_vlo,
+  CIN_4 => fpsc_vlo,
+  CIN_3 => fpsc_vlo,
+  CIN_2 => fpsc_vlo,
+  CIN_1 => fpsc_vlo,
+  CIN_0 => fpsc_vlo,
+  TESTCLK_MACO => fpsc_vlo,
+  FFC_MACRO_RST => serdes_rst);
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+   IF (open_status = name_error) THEN
+      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
+      severity ERROR;
+   END IF;
+   wait;
+END PROCESS;
+--synopsys translate_on
+  
+end serdes_gbe_0_100_arch ;
diff --git a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
index 9182a0e..91e0f75 100755
--- a/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
+++ b/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd
@@ -60,6 +60,49 @@ attribute syn_sharing of med_scm_sfp : architecture is "off";
 
 -- Components
 
+component serdes_gbe_0_100 is
+generic(
+  USER_CONFIG_FILE    :  String := "serdes_gbe_0_100.txt"
+);
+port(
+  refclkp              : in  std_logic;
+  refclkn              : in  std_logic;
+  rxrefclk             : in  std_logic;
+  refclk               : in  std_logic;
+  rxa_pclk             : out std_logic;
+  rxb_pclk             : out std_logic;
+  hdinp_0              : in  std_logic;
+  hdinn_0              : in  std_logic;
+  hdoutp_0             : out std_logic;
+  hdoutn_0             : out std_logic;
+  tclk_0               : in  std_logic;
+  rclk_0               : in  std_logic;
+  tx_rst_0             : in  std_logic;
+  rx_rst_0             : in  std_logic;
+  ref_0_sclk           : out std_logic;
+  rx_0_sclk            : out std_logic;
+  txd_0                : in  std_logic_vector(15 downto 0);
+  tx_k_0               : in  std_logic_vector(1 downto 0);
+  tx_force_disp_0      : in  std_logic_vector(1 downto 0);
+  tx_disp_sel_0        : in  std_logic_vector(1 downto 0);
+  rxd_0                : out std_logic_vector(15 downto 0);
+  rx_k_0               : out std_logic_vector(1 downto 0);
+  rx_disp_err_detect_0 : out std_logic_vector(1 downto 0);
+  rx_cv_detect_0       : out std_logic_vector(1 downto 0);
+  tx_crc_init_0        : in  std_logic_vector(1 downto 0);
+  rx_crc_eop_0         : out std_logic_vector(1 downto 0);
+  word_align_en_0      : in  std_logic;
+  mca_align_en_0       : in  std_logic;
+  felb_0               : in  std_logic;
+  lsm_en_0             : in  std_logic;
+  lsm_status_0         : out std_logic;
+  mca_resync_01        : in  std_logic;
+  quad_rst             : in  std_logic;
+  serdes_rst           : in  std_logic;
+  ref_pclk             : out std_logic
+);
+end component serdes_gbe_0_100;
+
 component serdes_gbe_0_200 is
 generic(
 	USER_CONFIG_FILE    :  String := "serdes_gbe_0_200.txt"
@@ -379,6 +422,47 @@ REFCLK2CORE_OUT <= tx_halfclk;
 -------------------------------------------------------------------------
 -------------------------------------------------------------------------
 
+gen_serdes_0_100 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO generate
+  THE_SERDES: serdes_gbe_0_100
+  port map(
+    refclkp              => SD_REFCLK_P_IN, -- not used here
+    refclkn              => SD_REFCLK_N_IN, -- not used here
+    rxrefclk             => CLK, -- raw 200MHz clock
+    refclk               => CLK, -- raw 200MHz clock
+    rxa_pclk             => open, --rx_halfclk, -- clock multiplier set by data bus width
+    rxb_pclk             => open,
+    hdinp_0              => SD_RXD_P_IN, -- SerDes I/O
+    hdinn_0              => SD_RXD_N_IN, -- SerDes I/O
+    hdoutp_0             => SD_TXD_P_OUT, -- SerDes I/O
+    hdoutn_0             => SD_TXD_N_OUT, -- SerDes I/O
+    tclk_0               => tx_halfclk, -- 100MHz
+    rclk_0               => rx_halfclk, -- 100MHz
+    tx_rst_0             => '0', --JM101206 lane_rst, -- async reset
+    rx_rst_0             => '0', --lane_rst, -- async reset  --reset when sd_los=0 and disp_err=1 or cv=1
+    ref_0_sclk           => tx_halfclk,
+    rx_0_sclk            => rx_halfclk,
+    txd_0                => tx_data,
+    tx_k_0               => tx_k,
+    tx_force_disp_0      => b"00", -- BUGBUG
+    tx_disp_sel_0        => b"00", -- BUGBUG
+    rxd_0                => rx_data,
+    rx_k_0               => rx_k,
+    rx_disp_err_detect_0 => open,
+    rx_cv_detect_0       => link_error(7 downto 6),
+    tx_crc_init_0        => b"00", -- CRC init (not needed)
+    rx_crc_eop_0         => open, -- (not needed)
+    word_align_en_0      => '1', -- word alignment
+    mca_align_en_0       => '0', -- (not needed)
+    felb_0               => '0', -- far end loopback disable
+    lsm_en_0             => '1', -- enable LinkStateMachine
+    lsm_status_0         => link_ok(0), -- link synchronisation successfull
+    mca_resync_01        => '0', -- not needed
+    quad_rst             => '0', -- hands off - kills registers!
+    serdes_rst           => '0', --JM101203 quad_rst, -- unknown if will work
+    ref_pclk             => open --tx_halfclk -- clock multiplier set by data bus width
+  );
+end generate;
+
 gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES generate
 	THE_SERDES: serdes_gbe_0_200
 	port map(
diff --git a/pinout/pexor.lpf b/pinout/pexor.lpf
new file mode 100644
index 0000000..e49dd03
--- /dev/null
+++ b/pinout/pexor.lpf
@@ -0,0 +1,322 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Clock / Reset
+#################################################################
+LOCATE COMP "CLK_100" SITE "L32"; #"K25" ;
+LOCATE COMP "CLK_125" SITE "K8" ;
+#LOCATE COMP "CLK_FPGA"   SITE "L32" ;
+LOCATE COMP "PE_RFCK"    SITE "M10" ;
+
+IOBUF PORT "CLK_100" IO_TYPE=LVDS DIFFRESISTOR=120 ;
+IOBUF PORT "CLK_125" IO_TYPE=LVDS DIFFRESISTOR=120 ;
+#IOBUF PORT "CLK_FPGA"   IO_TYPE=LVDS ;
+IOBUF PORT "PE_RFCK"    IO_TYPE=LVDS DIFFRESISTOR=120 ;
+
+LOCATE COMP "NRES"       SITE "AM3" ;
+IOBUF  PORT "NRES" IO_TYPE=LVTTL33 ;
+
+
+#################################################################
+# SFP Control
+#################################################################
+LOCATE COMP "SFP1_LOS" SITE "AH23" ;
+LOCATE COMP "SFP1_TX_DIS" SITE "AH24" ;
+LOCATE COMP "SFP1_TX_FAULT" SITE "AL22" ;
+LOCATE COMP "SFP2_LOS" SITE "AH25" ;
+LOCATE COMP "SFP2_TX_DIS" SITE "AH26" ;
+LOCATE COMP "SFP2_TX_FAULT" SITE "AM22" ;
+LOCATE COMP "SFP3_LOS" SITE "AD18" ;
+LOCATE COMP "SFP3_TX_DIS" SITE "AE18" ;
+LOCATE COMP "SFP3_TX_FAULT" SITE "AK19" ;
+LOCATE COMP "SFP4_LOS" SITE "AH19" ;
+LOCATE COMP "SFP4_TX_DIS" SITE "AH18" ;
+LOCATE COMP "SFP4_TX_FAULT" SITE "AK18" ;
+
+LOCATE COMP "SFP1_MOD_0" SITE "AG22" ;
+LOCATE COMP "SFP1_MOD_1" SITE "AH22" ;
+LOCATE COMP "SFP1_MOD_2" SITE "AL23" ;
+LOCATE COMP "SFP2_MOD_0" SITE "AE19" ;
+LOCATE COMP "SFP2_MOD_1" SITE "AF19" ;
+LOCATE COMP "SFP2_MOD_2" SITE "AM23" ;
+LOCATE COMP "SFP3_MOD_0" SITE "AG20" ;
+LOCATE COMP "SFP3_MOD_1" SITE "AG19" ;
+LOCATE COMP "SFP3_MOD_2" SITE "AJ19" ;
+LOCATE COMP "SFP4_MOD_0" SITE "AH21" ;
+LOCATE COMP "SFP4_MOD_1" SITE "AH20" ;
+LOCATE COMP "SFP4_MOD_2" SITE "AJ18" ;
+
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
+
+#################################################################
+# Hex-Switch
+#################################################################
+LOCATE COMP "SWITCH_IN_1" SITE "AK6" ;
+LOCATE COMP "SWITCH_IN_2" SITE "AJ6" ;
+LOCATE COMP "SWITCH_IN_3" SITE "AF10" ;
+LOCATE COMP "SWITCH_IN_4" SITE "AE11" ;
+
+DEFINE PORT GROUP "HSW_group" "SWITCH_IN*" ;
+IOBUF GROUP "HSW_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8;
+
+
+#################################################################
+# Aux Flash
+#################################################################
+LOCATE COMP "SPI_D_IN"    SITE "AG5" ;
+LOCATE COMP "SPI_SCK_OUT" SITE "AL4" ;
+LOCATE COMP "SPI_CS_OUT"  SITE "AL3" ;
+LOCATE COMP "SPI_SI_OUT"  SITE "AF7" ;
+
+DEFINE PORT GROUP "SPI_group" "SPI*" ;
+IOBUF GROUP "SPI_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8;
+
+
+#################################################################
+# I2C Tempsens
+#################################################################
+LOCATE COMP "SDA_TMP" SITE "AF6" ;
+LOCATE COMP "SCK_TMP" SITE "AK3" ;
+IOBUF PORT  "SDA_TMP" IO_TYPE=LVTTL33;
+IOBUF PORT  "SCK_TMP" IO_TYPE=LVTTL33;
+
+
+#################################################################
+# PLL User Ports
+#################################################################
+LOCATE COMP "PLLUSER_1" SITE "AH4" ;
+LOCATE COMP "PLLUSER_2" SITE "AK5" ;
+LOCATE COMP "PLLUSER_3" SITE "AJ5" ;
+LOCATE COMP "PLLUSER_4" SITE "AF8" ;
+
+DEFINE PORT GROUP "PLLUSER_group" "PLLUSER*" ;
+IOBUF GROUP "PLLUSER_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8;
+
+
+#################################################################
+# Trigger Bus
+#################################################################
+LOCATE COMP "ANT_1"  SITE "AM9" ;
+LOCATE COMP "ANT_2"  SITE "AM8" ;
+LOCATE COMP "ANT_3"  SITE "AF13" ;
+LOCATE COMP "ANT_4"  SITE "AE13" ;
+LOCATE COMP "ANT_5"  SITE "AL9" ;
+LOCATE COMP "ANT_6"  SITE "AL8" ;
+LOCATE COMP "ANT_7"  SITE "AG6" ;
+LOCATE COMP "ANT_8"  SITE "AK9" ;
+LOCATE COMP "ANT_9"  SITE "AJ9" ;
+LOCATE COMP "ANT_10" SITE "AG10" ;
+LOCATE COMP "ANT_11" SITE "AG11" ;
+LOCATE COMP "ANT_12" SITE "AM7" ;
+LOCATE COMP "ANT_13" SITE "AL7" ;
+LOCATE COMP "ANT_14" SITE "AD13" ;
+LOCATE COMP "ANT_15" SITE "AC13" ;
+LOCATE COMP "ANT_16" SITE "AK8" ;
+LOCATE COMP "ANT_17" SITE "AJ8" ;
+LOCATE COMP "ANT_18" SITE "AF11" ;
+LOCATE COMP "ANT_19" SITE "AD12" ;
+LOCATE COMP "ANT_20" SITE "AE12" ;
+LOCATE COMP "ANT_21" SITE "AM6" ;
+LOCATE COMP "ANT_22" SITE "AM5" ;
+LOCATE COMP "ANT_23" SITE "AC12" ;
+LOCATE COMP "ANT_24" SITE "AL6" ;
+LOCATE COMP "ANT_25" SITE "AL5" ;
+LOCATE COMP "ANT_26" SITE "AG7" ;
+
+DEFINE PORT GROUP "ANT_group" "ANT*" ;
+IOBUF GROUP "ANT_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8;
+
+
+#################################################################
+# PCIe Config
+#################################################################
+LOCATE COMP "X1" SITE "W30" ;
+LOCATE COMP "X4" SITE "W29" ;
+LOCATE COMP "XC" SITE "V28" ;
+
+LOCATE COMP "PE_RST_N" SITE "W31";
+LOCATE COMP "PE_SNCLK" SITE "Y31";
+LOCATE COMP "PE_SMDAT" SITE "W27";
+LOCATE COMP "PE_WAKEN" SITE "Y27";
+
+DEFINE PORT GROUP "X_group" "X*" ;
+IOBUF GROUP "X_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
+DEFINE PORT GROUP "PE_group" "PE*" ;
+IOBUF GROUP "PE_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_0" SITE "AM13" ;
+LOCATE COMP "LED_1" SITE "AM12" ;
+LOCATE COMP "LED_2" SITE "AH13" ;
+LOCATE COMP "LED_3" SITE "AH12" ;
+LOCATE COMP "LED_4" SITE "AK14" ;
+LOCATE COMP "LED_5" SITE "AJ14" ;
+LOCATE COMP "LED_6" SITE "AE15" ;
+LOCATE COMP "LED_7" SITE "AD15" ;
+
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8;
+
+
+#################################################################
+# LCD
+#################################################################
+# LOCATE COMP "DI_0" SITE "M25" ;
+# LOCATE COMP "DI_1" SITE "N25" ;
+# LOCATE COMP "DI_2" SITE "J30" ;
+# LOCATE COMP "DI_3" SITE "H30" ;
+# LOCATE COMP "DI_4" SITE "M28" ;
+# LOCATE COMP "DI_5" SITE "N28" ;
+# LOCATE COMP "DI_6" SITE "J32" ;
+# LOCATE COMP "DOUT_LCD" SITE "N26" ;
+# LOCATE COMP "AI_0" SITE "N27" ;
+# LOCATE COMP "AI_1" SITE "K31" ;
+# LOCATE COMP "WRDIS" SITE "J31" ;
+
+#################################################################
+# Debug-Port
+#################################################################
+LOCATE COMP "TEST_0" SITE "AM11" ;
+LOCATE COMP "TEST_1" SITE "AM10" ;
+LOCATE COMP "TEST_2" SITE "AH11" ;
+LOCATE COMP "TEST_3" SITE "AH10" ;
+LOCATE COMP "TEST_4" SITE "AK12" ;
+LOCATE COMP "TEST_5" SITE "AJ12" ;
+LOCATE COMP "TEST_6" SITE "AF14" ;
+LOCATE COMP "TEST_7" SITE "AE14" ;
+LOCATE COMP "TEST_8" SITE "AL11" ;
+LOCATE COMP "TEST_9" SITE "AL10" ;
+LOCATE COMP "TEST_10" SITE "AH9" ;
+LOCATE COMP "TEST_11" SITE "AH8" ;
+LOCATE COMP "TEST_12" SITE "AK11" ;
+LOCATE COMP "TEST_13" SITE "AJ11" ;
+LOCATE COMP "TEST_14" SITE "AH7" ;
+LOCATE COMP "TEST_15" SITE "AH6" ;
+LOCATE COMP "TEST_16" SITE "AM16" ;
+LOCATE COMP "TEST_17" SITE "AL16" ;
+LOCATE COMP "TEST_18" SITE "AF16" ;
+LOCATE COMP "TEST_19" SITE "AE16" ;
+LOCATE COMP "TEST_20" SITE "AM15" ;
+LOCATE COMP "TEST_21" SITE "AL15" ;
+LOCATE COMP "TEST_22" SITE "AD16" ;
+LOCATE COMP "TEST_23" SITE "AC16" ;
+LOCATE COMP "TEST_24" SITE "AM14" ;
+LOCATE COMP "TEST_25" SITE "AL14" ;
+LOCATE COMP "TEST_26" SITE "AG16" ;
+LOCATE COMP "TEST_27" SITE "AH16" ;
+LOCATE COMP "TEST_28" SITE "AK15" ;
+LOCATE COMP "TEST_29" SITE "AJ15" ;
+LOCATE COMP "TEST_30" SITE "AH15" ;
+LOCATE COMP "TEST_31" SITE "AH14" ;
+
+DEFINE PORT GROUP "TEST_group" "TEST*" ;
+IOBUF GROUP "TEST_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=8;
+
+
+#################################################################
+# RLDRAM
+#################################################################
+# LOCATE COMP "RL_A_0" SITE "W4" ;
+# LOCATE COMP "RL_A_1" SITE "W3" ;
+# LOCATE COMP "RL_A_2" SITE "V3" ;
+# LOCATE COMP "RL_A_3" SITE "V4" ;
+# LOCATE COMP "RL_A_4" SITE "V2" ;
+# LOCATE COMP "RL_A_5" SITE "V1" ;
+# LOCATE COMP "RL_A_6" SITE "U2" ;
+# LOCATE COMP "RL_A_7" SITE "U1" ;
+# LOCATE COMP "RL_A_8" SITE "T6" ;
+# LOCATE COMP "RL_A_9" SITE "T1" ;
+# LOCATE COMP "RL_A_10" SITE "T2" ;
+# LOCATE COMP "RL_A_11" SITE "U9" ;
+# LOCATE COMP "RL_A_12" SITE "R1" ;
+# LOCATE COMP "RL_A_13" SITE "R2" ;
+# LOCATE COMP "RL_A_14" SITE "AA1" ;
+# LOCATE COMP "RL_A_15" SITE "AB6" ;
+# LOCATE COMP "RL_A_16" SITE "AC6" ;
+# LOCATE COMP "RL_A_17" SITE "AC2" ;
+# LOCATE COMP "RL_A_18" SITE "AD4" ;
+# LOCATE COMP "RL_A_19" SITE "AD3" ;
+# LOCATE COMP "RL_A_20" SITE "AC5" ;
+# LOCATE COMP "RL_A_21" SITE "AD5" ;
+# LOCATE COMP "RL_A_22" SITE "AC1" ;
+# LOCATE COMP "RL_BA_0" SITE "W5" ;
+# LOCATE COMP "RL_BA_1" SITE "Y6" ;
+# LOCATE COMP "RL_BA_2" SITE "W6" ;
+# LOCATE COMP "RL_CK_N" SITE "R9" ;
+# LOCATE COMP "RL_CK_P" SITE "R8" ;
+# LOCATE COMP "RL_CS" SITE "Y2" ;
+# LOCATE COMP "RL_D_0" SITE "M5" ;
+# LOCATE COMP "RL_D_1" SITE "N5" ;
+# LOCATE COMP "RL_D_2" SITE "J1" ;
+# LOCATE COMP "RL_D_3" SITE "J2" ;
+# LOCATE COMP "RL_D_4" SITE "N7" ;
+# LOCATE COMP "RL_D_5" SITE "N6" ;
+# LOCATE COMP "RL_D_6" SITE "K2" ;
+# LOCATE COMP "RL_D_7" SITE "K1" ;
+# LOCATE COMP "RL_D_8" SITE "P8" ;
+# LOCATE COMP "RL_D_9" SITE "P7" ;
+# LOCATE COMP "RL_D_10" SITE "M4" ;
+# LOCATE COMP "RL_D_11" SITE "L4" ;
+# LOCATE COMP "RL_D_12" SITE "M3" ;
+# LOCATE COMP "RL_D_13" SITE "L3" ;
+# LOCATE COMP "RL_D_14" SITE "L2" ;
+# LOCATE COMP "RL_D_15" SITE "M2" ;
+# LOCATE COMP "RL_D_16" SITE "L1" ;
+# LOCATE COMP "RL_D_17" SITE "M1" ;
+# LOCATE COMP "RL_DK_N" SITE "N1" ;
+# LOCATE COMP "RL_DK_P" SITE "N2" ;
+# LOCATE COMP "RL_DM" SITE "Y1" ;
+# LOCATE COMP "RL_Q_0" SITE "J5" ;
+# LOCATE COMP "RL_Q_1" SITE "K5" ;
+# LOCATE COMP "RL_Q_2" SITE "F1" ;
+# LOCATE COMP "RL_Q_3" SITE "F2" ;
+# LOCATE COMP "RL_Q_4" SITE "L8" ;
+# LOCATE COMP "RL_Q_5" SITE "L7" ;
+# LOCATE COMP "RL_Q_6" SITE "G2" ;
+# LOCATE COMP "RL_Q_7" SITE "G1" ;
+# LOCATE COMP "RL_Q_8" SITE "L6" ;
+# LOCATE COMP "RL_Q_9" SITE "L5" ;
+# LOCATE COMP "RL_Q_10" SITE "H2" ;
+# LOCATE COMP "RL_Q_11" SITE "H1" ;
+# LOCATE COMP "RL_Q_12" SITE "J3" ;
+# LOCATE COMP "RL_Q_13" SITE "H3" ;
+# LOCATE COMP "RL_Q_14" SITE "N9" ;
+# LOCATE COMP "RL_Q_15" SITE "J4" ;
+# LOCATE COMP "RL_Q_16" SITE "H4" ;
+# LOCATE COMP "RL_Q_17" SITE "M8" ;
+# LOCATE COMP "RL_QK_0" SITE "AL2" ;
+# LOCATE COMP "RL_QVLD" SITE "N8" ;
+# LOCATE COMP "RL_REF" SITE "Y5" ;
+# LOCATE COMP "RL_WE" SITE "W8" ;
+
+
+#################################################################
+# Unused names
+#################################################################
+
+# LOCATE COMP "SFP1_RD_N" SITE "C31" ;
+# LOCATE COMP "SFP1_RD_P" SITE "C32" ;
+# LOCATE COMP "SFP1_TD_N" SITE "B30" ;
+# LOCATE COMP "SFP1_TD_P" SITE "A30" ;
+# LOCATE COMP "SFP2_RD_N" SITE "H28" ;
+# LOCATE COMP "SFP2_RD_P" SITE "G28" ;
+# LOCATE COMP "SFP2_TD_N" SITE "B29" ;
+# LOCATE COMP "SFP2_TD_P" SITE "A29" ;
+# LOCATE COMP "SFP3_RD_N" SITE "G25" ;
+# LOCATE COMP "SFP3_RD_P" SITE "F25" ;
+# LOCATE COMP "SFP3_TD_N" SITE "B25" ;
+# LOCATE COMP "SFP3_TD_P" SITE "A25" ;
+# LOCATE COMP "SFP4_RD_N" SITE "H23" ;
+# LOCATE COMP "SFP4_RD_P" SITE "G23" ;
+# LOCATE COMP "SFP4_TD_N" SITE "B24" ;
+# LOCATE COMP "SFP4_TD_P" SITE "A24" ;
+# LOCATE COMP "SERDES_125N" SITE "J8" ;
+# LOCATE COMP "SERDES_100N" SITE "J25";
diff --git a/special/trb_net_bridge_etrax_apl.vhd b/special/trb_net_bridge_etrax_apl.vhd
index eeee997..7ddb32e 100644
--- a/special/trb_net_bridge_etrax_apl.vhd
+++ b/special/trb_net_bridge_etrax_apl.vhd
@@ -4,7 +4,8 @@ USE IEEE.STD_LOGIC_ARITH.ALL;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 library work;
-use work.trb_net_std.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
 
 
 entity trb_net_bridge_etrax_apl is
@@ -77,7 +78,7 @@ architecture trb_net_bridge_etrax_apl_arch of trb_net_bridge_etrax_apl is
   signal fifo_pci_to_net_full    : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);
   signal fifo_pci_to_net_empty   : std_logic_vector((2**c_MUX_WIDTH)-1 downto 0);
   signal next_APL_SEND_OUT : std_logic_vector(2**c_MUX_WIDTH-1 downto 0);
-  type data_count_t is array(0 to 2**c_MUX_WIDTH-1) of std_logic_vector(9 downto 0);
+  type data_count_t is array(0 to 2**c_MUX_WIDTH-1) of std_logic_vector(10 downto 0);
   signal fifo_pci_to_net_data_count   : data_count_t;
   signal fifo_net_to_pci_data_count   : data_count_t;
   signal sender_control : std_logic_vector(32*2**(c_MUX_WIDTH)-1 downto 0);
@@ -103,28 +104,6 @@ architecture trb_net_bridge_etrax_apl_arch of trb_net_bridge_etrax_apl is
 
 
 
-  component trb_net16_fifo is
-    generic (
-      USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
-      USE_DATA_COUNT   : integer range 0 to 1 := c_NO;
-      DEPTH      : integer := 6
-      );
-    port (
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-      DATA_IN         : in  std_logic_vector(c_DATA_WIDTH - 1 downto 0);
-      PACKET_NUM_IN   : in  std_logic_vector(1 downto 0);
-      WRITE_ENABLE_IN : in  std_logic;
-      DATA_OUT        : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
-      PACKET_NUM_OUT  : out std_logic_vector(1 downto 0);
-      READ_ENABLE_IN  : in  std_logic;
-      DATA_COUNT_OUT  : out std_logic_vector(9 downto 0);
-      FULL_OUT        : out std_logic;
-      EMPTY_OUT       : out std_logic
-      );
-  end component;
-
 begin
 
   CPU_DATAREADY_OUT <= b_CPU_DATAREADY_OUT;
@@ -157,11 +136,13 @@ begin
   read_regs : process(sender_control, sender_target, sender_error, sender_status, fifo_net_to_pci_data_count,
           fifo_pci_to_net_data_count, reg_CPU_ADDRESS, reg_CPU_READ, reg_CPU_WRITE, api_status,
           fifo_net_to_pci_full, fifo_net_to_pci_empty, fifo_pci_to_net_full, fifo_pci_to_net_empty,
-          buf_CPU_DATA_OUT, reg_CPU_DATA_IN, channel_address, CTRL)
+          buf_CPU_DATA_OUT, reg_CPU_DATA_IN, channel_address, CTRL)
+		variable tmp : std_logic_vector(7 downto 0);
     begin
-      next_CPU_DATA_OUT <= (others => '0');
+      next_CPU_DATA_OUT <= (others => '0');
+			tmp := reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0);
      -- if reg_CPU_RD = '1' then
-        case reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) is
+        case tmp is
                            --middle nibble is dont care
           when x"10" =>
             next_CPU_DATA_OUT <= sender_control(channel_address*32+31 downto channel_address*32);
@@ -176,7 +157,7 @@ begin
             next_CPU_DATA_OUT <= sender_status(channel_address*32+31 downto channel_address*32);
           when x"24" =>
             next_CPU_DATA_OUT <= x"000" & "00" & fifo_net_to_pci_empty(channel_address) & fifo_net_to_pci_full(channel_address)
-                                  & "000000" & fifo_net_to_pci_data_count(channel_address)(9 downto 0);
+                                  & "00000" & fifo_net_to_pci_data_count(channel_address)(10 downto 0);
           when x"30" =>
             next_CPU_DATA_OUT <= api_status(channel_address*32+31 downto channel_address*32);
           when others         =>
@@ -194,16 +175,16 @@ begin
           sender_target  <= (others => '0');
           sender_error   <= (others => '0');
         else
-          if reg_CPU_WRITE = '1' then
-            case reg_CPU_ADDRESS(11 downto 8) & reg_CPU_ADDRESS(3 downto 0) is
+          if reg_CPU_WRITE = '1' and reg_CPU_ADDRESS(11 downto 8) = x"1" then
+            case reg_CPU_ADDRESS(3 downto 0) is
                             --middle nibble is dont care
-              when x"10" =>
+              when x"0" =>
                 sender_control(channel_address*32+8 downto channel_address*32) <= reg_CPU_DATA_IN(8 downto 0);
-              when x"11" =>
+              when x"1" =>
                 sender_target(channel_address*32+15 downto channel_address*32) <= reg_CPU_DATA_IN(15 downto 0);
-              when x"12" =>
+              when x"2" =>
                 sender_error(channel_address*32+31 downto channel_address*32) <= reg_CPU_DATA_IN;
-              when others =>
+              when others => null;
             end case;
           end if;
         end if;
@@ -286,7 +267,7 @@ begin
         PACKET_NUM_IN   => fifo_net_to_pci_din(18*i+17 downto 18*i+16),
         DATA_OUT        => fifo_net_to_pci_dout(32*i+15 downto 32*i),
         PACKET_NUM_OUT  => fifo_net_to_pci_dout(32*i+17 downto 32*i+16),
-        DATA_COUNT_OUT  => fifo_net_to_pci_data_count(i)(9 downto 0),
+        DATA_COUNT_OUT  => fifo_net_to_pci_data_count(i)(10 downto 0),
         full_out        => fifo_net_to_pci_full(i),
         empty_out       => fifo_net_to_pci_empty(i)
         );
@@ -307,7 +288,7 @@ begin
         PACKET_NUM_IN   => reg_CPU_DATA_IN(17 downto 16),
         DATA_OUT        => fifo_pci_to_net_dout(18*i+15 downto 18*i),
         PACKET_NUM_OUT  => fifo_pci_to_net_dout(18*i+17 downto 18*i+16),
-        DATA_COUNT_OUT  => fifo_pci_to_net_data_count(i)(9 downto 0),
+        DATA_COUNT_OUT  => fifo_pci_to_net_data_count(i)(10 downto 0),
         full_out        => fifo_pci_to_net_full(i),
         empty_out       => fifo_pci_to_net_empty(i)
         );
diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/special/trb_net_bridge_etrax_endpoint.vhd
index 959736b..759f603 100644
--- a/special/trb_net_bridge_etrax_endpoint.vhd
+++ b/special/trb_net_bridge_etrax_endpoint.vhd
@@ -298,6 +298,7 @@ begin
             INT_SLAVE_DATA_IN      => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
             INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
             INT_SLAVE_READ_OUT     => buf_to_apl_INIT_READ(i),
+            CTRL_SEQNR_RESET       => '0',
             -- Status and control port
             STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+1)*32-1 downto 2*i*32),
             STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+1)*32-1 downto 2*i*32)
@@ -359,6 +360,7 @@ begin
             INT_SLAVE_DATA_IN      => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
             INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
             INT_SLAVE_READ_OUT     => buf_to_apl_REPLY_READ(i),
+            CTRL_SEQNR_RESET       => '0',
             -- Status and control port
             STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32),
             STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32)
@@ -421,6 +423,7 @@ begin
               INT_SLAVE_DATA_IN      =>   buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
               INT_SLAVE_PACKET_NUM_IN=>   buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
               INT_SLAVE_READ_OUT     =>   buf_to_apl_INIT_READ(i),
+              CTRL_SEQNR_RESET       => '0',
               -- Status and control port
               STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32),
               STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32)
diff --git a/trb_net16_endpoint_active_4_channel.vhd b/trb_net16_endpoint_active_4_channel.vhd
index 08517a9..badc913 100644
--- a/trb_net16_endpoint_active_4_channel.vhd
+++ b/trb_net16_endpoint_active_4_channel.vhd
@@ -232,8 +232,8 @@ architecture trb_net16_endpoint_active_4_channel_arch of trb_net16_endpoint_acti
       MED_READ_IN        : in  STD_LOGIC;
 
       -- Internal direction port
-      INT_DATA_OUT       : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
-      INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+      INT_DATA_OUT       : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+      INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
       INT_DATAREADY_OUT  : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
       INT_READ_IN        : in  STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
 
diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 99aa5b2..be4886a 100644
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -760,7 +760,8 @@ end component trb_net16_med_scm_sfp_gbe;
 
   component trb_net16_fifo is
     generic (
-      USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
+      USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
+      USE_DATA_COUNT   : integer range 0 to 1 := c_NO;			
       DEPTH      : integer := 6
       );
     port (
@@ -772,7 +773,8 @@ end component trb_net16_med_scm_sfp_gbe;
       WRITE_ENABLE_IN : in  std_logic;
       DATA_OUT        : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
       PACKET_NUM_OUT  : out std_logic_vector(1 downto 0);
-      READ_ENABLE_IN  : in  std_logic;
+      READ_ENABLE_IN  : in  std_logic;
+			DATA_COUNT_OUT  : out std_logic_vector(10 downto 0);
       FULL_OUT        : out std_logic;
       EMPTY_OUT       : out std_logic
       );
@@ -1183,7 +1185,26 @@ end component trb_net16_med_scm_sfp_gbe;
       );
   end component;
 
-
+
+--component fifo_var_oreg is
+  --generic(
+    --FIFO_WIDTH                   : integer range 1 to 64 := 36;
+    --FIFO_DEPTH                   : integer range 1 to 16 := 8
+    --);
+  --port(
+    --Data                         : in  std_logic_vector(FIFO_WIDTH-1 downto 0);
+    --Clock                        : in  std_logic;
+    --WrEn                         : in  std_logic;
+    --RdEn                         : in  std_logic;
+    --Reset                        : in  std_logic;
+    --AmFullThresh                 : in  std_logic_vector(FIFO_DEPTH-1 downto 0);
+    --Q                            : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+    --WCNT                         : out std_logic_vector(FIFO_DEPTH downto 0);
+    --Empty                        : out std_logic;
+    --Full                         : out std_logic;
+    --AlmostFull                   : out std_logic
+    --);
+--end component;
 
 
 
@@ -2045,6 +2066,7 @@ end component;
     port (
       CLK: in std_logic;
       CLKOP: out std_logic;
+      CLKOS: out std_logic;
       LOCK: out std_logic
       );
   end component;