From: Cahit Date: Thu, 24 Apr 2014 21:32:29 +0000 (+0200) Subject: tdc_version package added X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=76a48c6d06605074d0d7fe7eb11cb7f2b0edb649;p=trb3.git tdc_version package added --- diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj index dffe62a..4ed43e2 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.prj +++ b/32PinAddOn/trb3_periph_32PinAddOn.prj @@ -52,6 +52,7 @@ impl -active "workdir" #add_file options add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "tdc_version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd index 08d8921..0a3a87d 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd +++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd @@ -7,6 +7,7 @@ use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; use work.config.all; +use work.tdc_version.all; use work.version.all; @@ -266,14 +267,14 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is signal stat_nack : std_logic := '0'; signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); - signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal sed_error : std_logic; + signal sed_din : std_logic_vector(31 downto 0); + signal sed_dout : std_logic_vector(31 downto 0); + signal sed_write : std_logic := '0'; + signal sed_read : std_logic := '0'; + signal sed_ack : std_logic := '0'; + signal sed_nack : std_logic := '0'; + signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); --TDC signal hit_in_i : std_logic_vector(64 downto 1); @@ -493,15 +494,15 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 9, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", - --5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", - --10 => x"cf80", 11 => x"d500", others => x"0000"), - 5 => x"c800", 6 => x"cf00", 7 => x"cf80", 8 => x"d500", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, - --5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, - --10 => 7, 11 => 4, others => 0) - 5 => 3, 6 => 6, 7 => 7, 8 => 4, others => 0) + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", + --5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", + --10 => x"cf80", 11 => x"d500", others => x"0000"), + 5 => x"c800", 6 => x"cf00", 7 => x"cf80", 8 => x"d500", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, + --5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, + --10 => 7, 11 => 4, others => 0) + 5 => 3, 6 => 6, 7 => 7, 8 => 4, others => 0) ) port map( CLK => clk_100_i, @@ -872,7 +873,7 @@ begin CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels STATUS_REG_NR => 21, -- Number of status regs CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => x"160", -- TDC version number + TDC_VERSION => TDC_VERSION, -- TDC version number DEBUG => c_YES, SIMULATION => c_NO) port map ( diff --git a/ADA_Addon/trb3_periph_ADA.prj b/ADA_Addon/trb3_periph_ADA.prj index 6304f52..db0557f 100644 --- a/ADA_Addon/trb3_periph_ADA.prj +++ b/ADA_Addon/trb3_periph_ADA.prj @@ -53,6 +53,7 @@ impl -active "workdir" #add_file options add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "tdc_version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" diff --git a/ADA_Addon/trb3_periph_ADA.vhd b/ADA_Addon/trb3_periph_ADA.vhd index 0bef5c3..1f990f8 100644 --- a/ADA_Addon/trb3_periph_ADA.vhd +++ b/ADA_Addon/trb3_periph_ADA.vhd @@ -7,6 +7,7 @@ use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; use work.config.all; +use work.tdc_version.all; use work.version.all; @@ -752,7 +753,7 @@ begin CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels STATUS_REG_NR => 20, -- Number of status regs CONTROL_REG_NR => 5, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => x"160", -- TDC version number + TDC_VERSION => TDC_VERSION, -- TDC version number DEBUG => c_YES, SIMULATION => c_NO) port map ( diff --git a/cbmtof/cbmtof.prj b/cbmtof/cbmtof.prj index 6cfc9c8..3543b0c 100644 --- a/cbmtof/cbmtof.prj +++ b/cbmtof/cbmtof.prj @@ -52,6 +52,7 @@ impl -active "workdir" #add_file options add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "tdc_version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd index ef8e332..ab623c8 100644 --- a/cbmtof/cbmtof.vhd +++ b/cbmtof/cbmtof.vhd @@ -7,6 +7,7 @@ use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; use work.config.all; +use work.tdc_version.all; use work.version.all; @@ -500,8 +501,8 @@ begin --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- --- timing_trg_received_i <= SPARE_LINE(0); - timing_trg_received_i <= CLK_CM(3); + timing_trg_received_i <= SPARE_LINE(0); +-- timing_trg_received_i <= CLK_CM(3); --------------------------------------------------------------------------- -- Bus Handler diff --git a/cbmtof/config.vhd b/cbmtof/config.vhd index 606270f..300eb4c 100644 --- a/cbmtof/config.vhd +++ b/cbmtof/config.vhd @@ -13,7 +13,6 @@ package config is --Include GbE logic constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons - constant TDC_VERSION : std_logic_vector(11 downto 0) := x"160"; constant USE_DOUBLE_EDGE : integer := c_YES; --Include SPI on AddOn connector diff --git a/hadesstart/trb3_periph_hadesstart.prj b/hadesstart/trb3_periph_hadesstart.prj index 2cbe905..347a7ce 100644 --- a/hadesstart/trb3_periph_hadesstart.prj +++ b/hadesstart/trb3_periph_hadesstart.prj @@ -52,6 +52,7 @@ impl -active "workdir" #add_file options add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "tdc_version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" @@ -166,6 +167,7 @@ add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd" #add_file -vhdl -lib "work" "currentRelease/Reference_Channel_200.vhd" #add_file -vhdl -lib "work" "currentRelease/Reference_Channel.vhd" diff --git a/hadesstart/trb3_periph_hadesstart.vhd b/hadesstart/trb3_periph_hadesstart.vhd index 09f1a2c..12ded44 100644 --- a/hadesstart/trb3_periph_hadesstart.vhd +++ b/hadesstart/trb3_periph_hadesstart.vhd @@ -7,6 +7,7 @@ use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; use work.config.all; +use work.tdc_version.all; use work.version.all; @@ -818,7 +819,7 @@ THE_SED : entity work.sedcheck CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels STATUS_REG_NR => 22, -- Number of status regs CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => x"160", -- TDC version number + TDC_VERSION => TDC_VERSION -- TDC version number DEBUG => c_YES, SIMULATION => c_NO) port map ( diff --git a/tdc_releases/tdc_v1.6.1/tdc_version.vhd b/tdc_releases/tdc_v1.6.1/tdc_version.vhd new file mode 100644 index 0000000..cecf226 --- /dev/null +++ b/tdc_releases/tdc_v1.6.1/tdc_version.vhd @@ -0,0 +1,9 @@ +library ieee; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +package tdc_version is + + constant TDC_VERSION : std_logic_vector(11 downto 0) := x"161"; + +end; diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj index 3915fc1..bac5341 100644 --- a/wasa/trb3_periph_padiwa.prj +++ b/wasa/trb3_periph_padiwa.prj @@ -52,6 +52,7 @@ impl -active "workdir" #add_file options add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "tdc_version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index 225a1a4..b77b5b5 100644 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -7,6 +7,7 @@ use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; use work.config.all; +use work.tdc_version.all; use work.version.all; @@ -913,7 +914,7 @@ THE_SED : entity work.sedcheck CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels STATUS_REG_NR => 21, -- Number of status regs CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => x"160", -- TDC version number + TDC_VERSION => TDC_VERSION -- TDC version number DEBUG => c_YES, SIMULATION => c_NO) port map (