From: hadeshyp Date: Tue, 8 Jun 2010 17:51:56 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=76ae7953329f03e40bf2f8288e689e835da77343;p=daqdocu.git *** empty log message *** --- diff --git a/cts.tex b/cts.tex index 82c102b..e7f938b 100644 --- a/cts.tex +++ b/cts.tex @@ -1,6 +1,6 @@ - + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Memory Map} @@ -11,17 +11,18 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% For all registers described in this subsection refer to the Fig.\ref{cts_logic} \begin{description} - - \item [0xA0CC] Individual bits are enabling inputs - \item [0xA0D1 - 0xA0D4] Delay input signals, each nibble corresponds to one input e.g. 0xA0D1(3 to 0) corresponds to first input of the start part (Start 0). Delay value = 4 bit value * clock period (5ns) - \item [0xA0CD - 0xA0CE] Downscale input signals, each input signal is downscaled - $2^{value}$ - \item [0xA0D6 - 0xA0D8] Set width = value*clock period - \item [0xA0D9] Bits 12 down to 0 - TS gating disable - \item [0xA0DA] Bits 14 down to 0 - trigger out enable - \item [0xA0DB] Bits 6 down to 0 is selecting multiplexer output for ADO TTL(1) line and 14 down to 8 for ADO TTL(2) - \begin{description} - \item [31 - 0] delayed signals - \item [46 - 32] pti $and$ gts out + \item [0xA089: Debug] Trigger logic debug out + \item [0xA09B -- 0xA0BA: Scaler] Scalers out + \item [0xA0CC: Input enable] Individual bits are enabling inputs + \item [0xA0CD -- 0xA0CE: Downscale] Downscales the input signals, each input signal is downscaled by $2^{value}$ + \item [0xA0D1 -- 0xA0D4: Delay] Delay input signals, each nibble corresponds to one input e.g. 0xA0D1(3 to 0) corresponds to first input of the start part (Start 0). Delay value = 4 bit value * clock period (5ns) + \item [0xA0D6 -- 0xA0D8] Set width = value*clock period + \item [0xA0D9] Bits 12 downto 0 - TS gating disable + \item [0xA0DA: Trigger output] Bits 14 downto 0 - trigger out enable + \item [0xA0DB: Output select] Bits 6 downto 0 is selecting multiplexer output for ADO TTL(1) line and 14 down to 8 for ADO TTL(2): + \begin{description} + \item [31 -- 0] delayed signals + \item [46 -- 32] pti $and$ gts out \item [47] lvl1 trigger \item [48] Start and Veto antycoincidence \item [49] Veto set width out @@ -32,13 +33,14 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic} \item [54] Veto downscaled out \item [63 - 55] Multiplicity out \end{description} - \item [0xA0DC 4 downto 0], if 0xA0DC(4)=0 then standard trigger selection else trigger code = 0xA0DC(3 downto 0) - \item [0xA0DC bit 5] MDC calibration trigger enable - \item [0xA0DC bit 6] Force update Shower pedestals trigger (write ..1..0) - \item [0xA0DC bit 7] Disable Shower pedestals update (generated once during each spill off) - \item [0xA0DC 11 down to 8] Select frequency for internally generated trigger - $781.25kHz/(2^value)$ - \item [0xA089] Trigger logic debug out - \item [0xA09B -0xA0BA] Scalers out + \item [0xA0DC] Different settings: + \begin{description} + \item[Bit 4 -- 0] If (4)=0 then standard trigger selection else trigger code = (3 downto 0) + \item[Bit 5] MDC calibration trigger enable + \item[Bit 6] Force update Shower pedestals trigger (write ..1..0) + \item[Bit 7] Disable Shower pedestals update (generated once during each spill off) + \item[Bit 11 -- 8] Select frequency for internally generated trigger - $781.25kHz/(2^{value})$ + \end{description} \end{description} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -75,7 +77,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic} \item[Bit 3] CTS event number / type fifo empty \item[Bit 11 -- 4] Difference between LVL1 and IPU event counters \item[Bit 23 -- 12] IPU event number - \item[Bit 31 -- 24] CTS fifo data counter + \item[Bit 31 -- 24] CTS fifo data counter \end{description} \item[0xA0C3: Etrax control] Etrax readout control register @@ -88,7 +90,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic} % \item[0xA0C9] Select how many times should be sent data to the EB with current ID (which corresponds to the EB IP number), when 0 does not swith between IDs % \item[0xA0CA] Tables of 8 EB IDs (each ID has four bits), the IDs are switched form CA(3 down to 0) to CA(7 down to 4) ... CB(31 down to 28) -% \item[0xA0CB] Tables of 8 EB IDs (each ID has four bits) +% \item[0xA0CB] Tables of 8 EB IDs (each ID has four bits) % \end{description} @@ -96,45 +98,47 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic} For the time being "old" logic of the CTS is not removed. \item[0xA0C5 old CTS trigger selection] Trigger source selection \begin{description} - \item[Bits 4 - 0] enable trigger input on LVDS(4 downto 0) - corresponds to ADO LV(9 downto 0) on the trbv2 schematics - \item[Bits 9 - 5] enable trigger input on LVTTL(20 downto 16) - corresponds to ADO TTL(20 downto 16) on the trbv2 schematics + \item[Bit 4 -- 0] enable trigger input on LVDS(4 downto 0) - corresponds to ADO LV(9 downto 0) on the trbv2 schematics + \item[Bit 9 -- 5] enable trigger input on LVTTL(20 downto 16) - corresponds to ADO TTL(20 downto 16) on the trbv2 schematics \item[Bit 10] trigger form fast reference trigger - corresponds to Vir Trig on the trbv2 schematics - \item[Bit 11] self triggering (internal generator) - \item[Bit 12] enable LVDS(0) and LVDS(1) coincidence + \item[Bit 11] self triggering (internal generator) + \item[Bit 12] enable LVDS(0) and LVDS(1) coincidence \item[Bit 13] Trigger from C5(28) register - \item[Bit 14] enable LVTTL(16) and LVTTL(17) coincidence + \item[Bit 14] enable LVTTL(16) and LVTTL(17) coincidence \item[Bit 15] enable LVTTL(18) and LVTTL(19) - \item[Bits 17 - 16] Change source of LVL2 trigger: "00" - auto (defaoult, generated after LVL1 trigger),"01" - LVDS lines,"10"- local source - \item[Bits 27 - 20] Number of how many LVL1 trigger has to pass to send LVL2 trigger + \item[Bit 17 -- 16] Change source of LVL2 trigger: "00" - auto (defaoult, generated after LVL1 trigger),"01" - LVDS lines,"10"- local source + \item[Bit 27 -- 20] Number of how many LVL1 trigger has to pass to send LVL2 trigger \item[Bit 28] Making trigger on rising edge (0...1...0) - \item[bit 29] not used - \item[bit 30] Enable LVL1 trigger source te be trigger logic (see Fig.\ref{cts_logic}) - \item[bit 31] Make double APV pulse (0...1...0) + \item[Bit 29] not used + \item[Bit 30] Enable LVL1 trigger source te be trigger logic (see Fig.\ref{cts_logic}) + \item[Bit 31] Make double APV pulse (0...1...0) \end{description} -\item[0xA0C6] LVL1 and IPU mixed +\item[0xA0C6] LVL1 and IPU mixed \begin{description} - \item[Bits 7 - 0] IPU downscale - not used in current scheme. - \item[Bits 27 - 8] Frequency of self triggering : 50MHz/value - \item[Bit 31 - 28] Length of timing trigger : 100ns + value*10ns (when is value< 7), when value > 6 time = (value - 7) * 10ns + \item[Bit 7 -- 0] IPU downscale - not used in current scheme. + \item[Bit 27 -- 8] Frequency of self triggering : 50MHz/value + \item[Bit 31 -- 28] Length of timing trigger : 100ns + value*10ns (when is value< 7), when value > 6 time = (value - 7) * 10ns \end{description} + \item[0xA0C7] LVL1 trigger type selection \begin{description} - \item[Bits 4 - 0] If c7(4)=1 the lvl1 trigger type equals c7(3 downto 0) else type is defined internally or by trigger logic + \item[Bit 4 -- 0] If c7(4)=1 the lvl1 trigger type equals c7(3 downto 0) else type is defined internally or by trigger logic \end{description} \item[0xA0C7] LVL1 trigger information \begin{description} - \item[Bits 13 - 0] LVL1 trigger information 13 downto 0 + \item[Bit 13 -- 0] LVL1 trigger information 13 downto 0 \end{description} -\end{description} +\end{description} + + \begin{figure} \centering \includegraphics[width=.9\textwidth]{cts_doc.pdf} \caption{CTS trigger box logic} \label{cts_logic} - \end{figure} - + diff --git a/hubs.tex b/hubs.tex index 62b93db..ecdd484 100755 --- a/hubs.tex +++ b/hubs.tex @@ -5,7 +5,7 @@ \item[0x84: Active Ports] Status of all ports. Each bit gives the current status of one port: 1 when the link is active and able to transport data, 0 if not. \item[0x85: Uplinks] Configuration of the Ports. Each bit gives the configuration of one port: 1 if this port is configured as an uplink, 0 if not. \item[0x86: Downlinks] Configuration of the Ports. Each bit gives the configuration of one port: 1 if this port is configured as downlink, 0 if not. - \item[0x87: IPU channel state] Shows the current state of the state machine handling the IPU channel. + \item[0x87: IPU channel state] Shows the current state of the state machine handling the IPU channel. \begin{description} \item[Bit 0 - 3] FSM state \begin{description} @@ -23,18 +23,19 @@ \item[0xB] Waiting for init channel to finish \item[0xF] Default value \end{description} - \item[Bit 4 - 9] don't care + \item[Bit 4 - 9] don't care \item[Bit 10 - 12] current packet counter \item[Bit 13 - 15] read pointer to DHDR memory \end{description} \item[0x88 - 0x8B: Timeouts $\dagger$] One register for each TrbNet channel. Each bit gives the status of one port: 1 if there was a timeout on this port, 0 otherwise. These registers are cleared after being read. \item[0x8C - 0x8F: Waiting for ACK] One register for each TrbNet channel. Each bit gives the status of one port: 1 if data transmission on this port is stopped because the receiver did not acknowledge previous EOB words, 0 otherwise. + \item[0x90: Link error status] One bit for each port. 0 if normal operation / inactive, 1 in cave of error (e.g. code violation). \item[0xA0 - 0xA3: Error-/Status-Bits $\dagger$] One register for each TrbNet channel. Each register is the last Error-/Status-Bits, combined from all ports. \item[0xA4: Slow Control Error $\dagger$] One bit for each port. 1 if either one of the Errorbits 1,3,6 on the slow control channel have been set before. This register is cleared after being read. \item[0xA5: Endpoint reached] One bit for each port. 1 if this port returned the ``Endpoint reached'' bit in the status word set in the last slow control access, 0 otherwise. This information can be used to track a single board in the network: First a read access using the network address of the selected board has to be done. Immediately afterward this register can be read. To secure this non-atomic operation, the register is only updated if the board also return the ``don't understand' bit, e.g. after a read memory access to register 0. \item[0x4000 - 0x400F: IPU Packet counter] One register for each port. Each register is a 32 bit counter of the packets (with 64bit payload each) received on the IPU channel on this port. A write to 0x4000 resets all counters. \item[0x4010 - 0x401F: Slow Control Packet counter] One register for each port. Each register is a 32 bit counter of the packets (with 64bit payload each) received on the slow control channel on this port. A write to 0x4010 resets all counters. - \item[0x4020 - 0x402F: Error Bits $\dagger$] One register for each port. Contents are part of the last Error-/Status-Bits received on this port: + \item[0x4020 - 0x402F: Error Bits $\dagger$] One register for each port. Contents are part of the last Error-/Status-Bits received on this port: \begin{itemize} \item Bit 0 - 7 of each register: Bit 0 - 7 of Errorbits on LVL1 channel @@ -62,7 +63,7 @@ $\dagger$: Register is not reset during network reset \begin{description} \item[0x0000 - 0x00FF:] Standard internal RegIO addresses \item[0x1000 - 0x3FFF:] Reserved in hub\_base for monitoring features - \item[0x4000 - 0x7FFF:] Reserved in hub\_base + \item[0x4000 - 0x7FFF:] Reserved in hub\_base \item[0x8000 - 0xBFFF:] Forwarded to \portname{REGIO} ports of hub\_base, reserved for GbE \item[0xC000 - 0xFFFF:] Forwarded to \portname{REGIO} ports of hub\_base, reserved for board specific funtions, e.g. 0xD000 - 0xD2FF for Flash programming \end{description} diff --git a/lvl1trigger.tex b/lvl1trigger.tex index 36887a0..54ebcc5 100755 --- a/lvl1trigger.tex +++ b/lvl1trigger.tex @@ -118,8 +118,8 @@ The CTS will include features to set these bits via slow control either to a sta 1 - 6 & t.b.d. & Not yet defined \\ 7 & no timing trigger & Marks a LVL1 trigger which was not preceded by a timing trigger (e.g. calibration) \\ 8 - 10 & RICH & RICH data configuration bits \\ -11 - 13 & Shower & 11: tbd, 12: tbd, 13: tbd\\ -14 - 16 & MDC & 14: data format select (0: debug, 1: compressed (2 hits in 1 word))\\ +11 - 13 & Shower & Not yet defined \\ +14 - 16 & MDC & Not yet defined \\ 17 - 23 & t.b.d. & Not yet defined \\ \hline \end{tabularx} diff --git a/mdc.tex b/mdc.tex index b7da3d7..eb190d0 100755 --- a/mdc.tex +++ b/mdc.tex @@ -98,8 +98,24 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr \subsubsection{MDC OEP Status Register} \begin{description} \item[0x9000: \filename{Control} status register] + \begin{description} + \item[Bit 0] Token Back + \item[Bit 1] Token Missing + \item[Bit 2] CMS active + \end{description} \item[0x9001: \filename{Trigger\_Handler} status register] + \item[0x9002: \filename{Data\_Handler} status register] + \begin{description} + \item[Bit 3..0] State machine status + \item[Bit 4] Start Readout + \item[Bit 5] Finished Readout + \item[Bit 6] Data Write Enable + \item[Bit 7] Send Debug Information enable + \item[Bit 8] Send Dummy Data enable + \item[Bit 9] Data Format Select enable + \item[Bit 10] Data Valid In + \end{description} \item[0x9003: \filename{Tdc\_Readout} status register] The status register of the entity that reads data provided by the MBO. \begin{description} \item[Bit 3..0] State machine status \\ 0: idle; 1: save\_L\_word, 2: send\_token, 3: wait\_1, 4: wait\_2, 5: save\_L\_word\_next. 6: wait\_for\_AOD\_low, 7: wait\_3, 8: wait\_4, 9: save\_H\_word\_state\_next @@ -111,6 +127,18 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr \item[Bit 12..9] Lower four bits of trigger number - used to tag data in fifos \end{description} \item[0x9004: \filename{Control\_Line\_Handler} status register] + \begin{description} + \item[Bit 3..0] State machine status + \item[Bit 4] Finished Begrun Out + \item[Bit 5] Finished Load Calib Out + \item[Bit 6] Token Back + \item[Bit 7] No Token Back + \item[Bit 8] MBO initialized + \item[Bit 9] Line Select + \item[Bit 10] GDE + \item[Bit 11] Start Debug Readout + \end{description} + \item[0x9005: \filename{Trigger\_Begrun} status register] The status register of the entity that controls the entities controlling mode lines and loading configuration to the MBO. \begin{description} \item[Bit 3..0] Step of the mode line loading sequence diff --git a/networkaddresses.tex b/networkaddresses.tex index c34ba1b..f562579 100755 --- a/networkaddresses.tex +++ b/networkaddresses.tex @@ -18,19 +18,22 @@ On boards with two or more FPGAs each FPGA gets its own address. The FPGA provid 2000 - 2FFF & MDC OEP & 2nd digit: MDC layer (0-3); 3rd digit: sector (0-5); 4th digit MBO (0-F) \\ 3000 - 31FF & RICH ADCM & 3rd digit: sector (0-5); 4th digit: segment (0-4) \\ 3200 - 37FF & Shower AddOn & 3rd digit: sector (0-5); 4th digit: FPGA (0-2) \\ -4000 - 40FF & Start/Veto & 1 TRB for both detectors \\ +4000 - 400F & Start & Start detector \\ +4010 - 401F & Veto & Veto detector \\ 4400 - 47FF & Wall & 3 TRBs for forward wall \\ 4800 - 4BFF & RPC & 3rd digit: sector (0-5), 4th digit: segment (0-3) \\ 4C00 - 4FFF & TOF & 3rd digit: sector (0-5); 4th digit: 0 for normal TRB, 1 for additional TRB to resemble broken channels\\ 5555 & SEB & Dummy Address used in headers generated by SubEventBuilders \\ -8000 - 80FF & CTS Hub & central hub\\ +8000 - 80FF & Central Hub & central hub\\ 8100 - 81FF & MDC Hub & Hub for inner MDC (3rd digit 0) or outer MDC (3rd digit 1)\\ 8300 - 83FF & RICH Hubs & Hubs for RICH, last digit: sector divided by 2 \\ 8400 - 84FF & RPC Hubs & Hubs for RPC, last digit: sector divided by 3 \\ 8500 - 85FF & Shower Hub & \\ 8600 - 86FF & TOF Hub & \\ 8700 - 87FF & Forward Wall Hub & \\ -F000 - FEFF & Test Setups & \\ +8800 - 88FF & Start/Veto/CTS Hub & \\ +F000 - FDFF & Test Setups & \\ +FE00 - FEFF & Reserved & Reserved for extension of broadcast addresses \\ FF00 - FFFF & Broadcasts & \end{tabularx} \caption{Network Addresses} @@ -73,7 +76,7 @@ If the bitmask configuration of an endpoint contains two unset bits it will answ \label{subeventids} The subevent ids are assigned based on the trbnet addresses of the board forming the subevent. The range in which TRBs are located is restricted due to demands of the unpacking software. -In summary, the only boards that send subevents are the Hubs, MDC Concentrators and Shower AddOns as well as the CTS. This sums up to 59 individual SubEvents. +In summary, the only boards that send subevents are the Hubs, MDC Concentrators and Shower AddOns as well as the CTS. This sums up to 30 individual SubEvents. \begin{table}[hb] \begin{center} @@ -82,17 +85,16 @@ In summary, the only boards that send subevents are the Hubs, MDC Concentrators CTS & 0000 - 00FF & 1 & \\ MDC & 1000 - 17FF & 12 & second digit is inner(0) or outer(1) MDC, 3rd digit is the sector \\ Shower & 3200 - 33FF & 6 & 3rd digit is the sector \\ -Start/Veto & 4000 - 43FF & 1 & \\ Forw. Wall & 4400 - 47FF & 3 & last digit is the segment of FW \\ RPC & 4800 - 4BFF & 24 & 3rd digit is the sector, last digit normal(0) or additional(1) TRB \\ TOF & 4C00 - 4FFF & 9 & 3rd digit is normal(0) or additional(1) TRB, last digit is the sector \\ -Start/Veto & 8000 - 80FF & 1 & Start / Veto / Forward Wall readout via GbE \\ RICH & 8300 - 83FF & 3 & last digit is the sector divided by 2 \\ -RPC *) & 8400 - 84FF & 2 & RPC readout via GbE \\ -TOF *) & 8600 - 86FF & 1 & TOF readout via GbE \\ -Wall *) & 8700 - 87FF & 1 & Forward Wall readout via GbE \\ +RPC & 8400 - 84FF & 2 & RPC readout via GbE \\ +TOF & 8600 - 86FF & 1 & TOF readout via GbE \\ +Wall & 8700 - 87FF & 1 & Forward Wall readout via GbE \\ +Start/Veto & 8800 - 88FF & 1 & Start / Veto (and CTS in the final version) \\ \end{tabularx} -\caption{Reserved SubEvent IDs Ranges. The star marks possible future setups which are not implemented now but might come later. In that case, data from several TRB (only from one subsystem) will be merged into one SubEvent. The id of each TRB is still available inside the data stream.} +\caption{Reserved SubEvent IDs Ranges. } \label{subeventidtable} \end{center} \end{table}