From: Ludwig Maier Date: Fri, 5 Jun 2015 15:23:41 +0000 (+0200) Subject: scaler tmp.... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=76f612e4f16facdb4ad20f2f96e16e300e60d2b9;p=trb3.git scaler tmp.... --- diff --git a/scaler/Makefile b/scaler/Makefile index e3607d8..7a2bc8d 100644 --- a/scaler/Makefile +++ b/scaler/Makefile @@ -15,6 +15,7 @@ all: workdir/$(TARGET).bit .PHONY: clean clean: rm -rf workdir/* + rm -f workdir/.[a-z,A-Z]* .PHONY: distclean distclean: @@ -57,6 +58,13 @@ workdir/$(TARGET).ncd: workdir/$(TARGET)_map.ncd cd workdir && \ par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd + # + # Multipar geht gerade nicht + #par $(TARGET)_map.ncd $(TARGET).prf + #mv $(TARGET).prf.ncd $(TARGET).ncd + # par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf + #cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd + # Mapper workdir/$(TARGET)_map.ncd: workdir/$(TARGET).ngd $(TARGET).lpf diff --git a/scaler/nodelist.txt b/scaler/nodelist.txt index 0c760d8..11587ec 100755 --- a/scaler/nodelist.txt +++ b/scaler/nodelist.txt @@ -2,49 +2,4 @@ system = linux corenum = 2 env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs2] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs3] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs4] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs5] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs6] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs7] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs8] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs9] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs10] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +workdir = /home/rich/TRB/nXyter/trb3/scaler/workdir/ diff --git a/scaler/source/adc_ad9228.vhd b/scaler/source/adc_ad9228.vhd index 6c958f3..8486654 100644 --- a/scaler/source/adc_ad9228.vhd +++ b/scaler/source/adc_ad9228.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity adc_ad9228 is generic ( diff --git a/scaler/source/adc_ad9228_data_handler.vhd b/scaler/source/adc_ad9228_data_handler.vhd index af29502..a94d191 100644 --- a/scaler/source/adc_ad9228_data_handler.vhd +++ b/scaler/source/adc_ad9228_data_handler.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity adc_ad9228_data_handler is generic ( diff --git a/scaler/source/adc_spi_master.vhd b/scaler/source/adc_spi_master.vhd index 0d773dc..cc30bde 100644 --- a/scaler/source/adc_spi_master.vhd +++ b/scaler/source/adc_spi_master.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity adc_spi_master is generic ( diff --git a/scaler/source/adc_spi_readbyte.vhd b/scaler/source/adc_spi_readbyte.vhd index 934ce84..d7d447e 100644 --- a/scaler/source/adc_spi_readbyte.vhd +++ b/scaler/source/adc_spi_readbyte.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity adc_spi_readbyte is diff --git a/scaler/source/adc_spi_sendbyte.vhd b/scaler/source/adc_spi_sendbyte.vhd index 7c41eba..495d97d 100644 --- a/scaler/source/adc_spi_sendbyte.vhd +++ b/scaler/source/adc_spi_sendbyte.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity adc_spi_sendbyte is diff --git a/scaler/source/debug_multiplexer.vhd b/scaler/source/debug_multiplexer.vhd index b116439..c857b3d 100644 --- a/scaler/source/debug_multiplexer.vhd +++ b/scaler/source/debug_multiplexer.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity debug_multiplexer is generic ( diff --git a/scaler/source/fifo_44_data_delay_my.vhd b/scaler/source/fifo_44_data_delay_my.vhd index b923484..0bd72d2 100644 --- a/scaler/source/fifo_44_data_delay_my.vhd +++ b/scaler/source/fifo_44_data_delay_my.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity fifo_44_data_delay_my is port ( diff --git a/scaler/source/nx_data_delay.vhd b/scaler/source/nx_data_delay.vhd index 9ee143c..afcc24d 100644 --- a/scaler/source/nx_data_delay.vhd +++ b/scaler/source/nx_data_delay.vhd @@ -6,7 +6,7 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_data_delay is port( diff --git a/scaler/source/nx_data_receiver.vhd b/scaler/source/nx_data_receiver.vhd index 1440a2b..a57e8e8 100644 --- a/scaler/source/nx_data_receiver.vhd +++ b/scaler/source/nx_data_receiver.vhd @@ -5,7 +5,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_data_receiver is generic ( diff --git a/scaler/source/nx_data_validate.vhd b/scaler/source/nx_data_validate.vhd index 0c9ef06..15b2bf0 100644 --- a/scaler/source/nx_data_validate.vhd +++ b/scaler/source/nx_data_validate.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_data_validate is port ( diff --git a/scaler/source/nx_event_buffer.vhd b/scaler/source/nx_event_buffer.vhd index 3e092cf..b2d2e66 100644 --- a/scaler/source/nx_event_buffer.vhd +++ b/scaler/source/nx_event_buffer.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; use work.trb3_components.all; entity nx_event_buffer is diff --git a/scaler/source/nx_fpga_timestamp.vhd b/scaler/source/nx_fpga_timestamp.vhd index c54b0a6..c54ceef 100644 --- a/scaler/source/nx_fpga_timestamp.vhd +++ b/scaler/source/nx_fpga_timestamp.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_fpga_timestamp is port ( diff --git a/scaler/source/nx_histogram.vhd b/scaler/source/nx_histogram.vhd index 2ea47d7..2fe6cc3 100644 --- a/scaler/source/nx_histogram.vhd +++ b/scaler/source/nx_histogram.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_histogram is generic ( diff --git a/scaler/source/nx_histograms.vhd b/scaler/source/nx_histograms.vhd index 1f86376..977d094 100644 --- a/scaler/source/nx_histograms.vhd +++ b/scaler/source/nx_histograms.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_histograms is port ( diff --git a/scaler/source/nx_i2c_master.vhd b/scaler/source/nx_i2c_master.vhd index a506ffa..ec473f0 100644 --- a/scaler/source/nx_i2c_master.vhd +++ b/scaler/source/nx_i2c_master.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_i2c_master is generic ( diff --git a/scaler/source/nx_i2c_readbyte.vhd b/scaler/source/nx_i2c_readbyte.vhd index 0be3797..d7d6d87 100644 --- a/scaler/source/nx_i2c_readbyte.vhd +++ b/scaler/source/nx_i2c_readbyte.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_i2c_readbyte is diff --git a/scaler/source/nx_i2c_sendbyte.vhd b/scaler/source/nx_i2c_sendbyte.vhd index ecf6718..804302d 100644 --- a/scaler/source/nx_i2c_sendbyte.vhd +++ b/scaler/source/nx_i2c_sendbyte.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_i2c_sendbyte is diff --git a/scaler/source/nx_i2c_startstop.vhd b/scaler/source/nx_i2c_startstop.vhd index 481c2ab..d0d9fc7 100644 --- a/scaler/source/nx_i2c_startstop.vhd +++ b/scaler/source/nx_i2c_startstop.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_i2c_startstop is generic ( diff --git a/scaler/source/nx_register_setup.vhd b/scaler/source/nx_register_setup.vhd index 71821ba..1072137 100644 --- a/scaler/source/nx_register_setup.vhd +++ b/scaler/source/nx_register_setup.vhd @@ -5,7 +5,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_register_setup is port( diff --git a/scaler/source/nx_status.vhd b/scaler/source/nx_status.vhd index 81423cf..7d4ca5d 100644 --- a/scaler/source/nx_status.vhd +++ b/scaler/source/nx_status.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_status is port( diff --git a/scaler/source/nx_status_event.vhd b/scaler/source/nx_status_event.vhd index 5eb13be..f573acc 100644 --- a/scaler/source/nx_status_event.vhd +++ b/scaler/source/nx_status_event.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; use work.trb3_components.all; entity nx_status_event is diff --git a/scaler/source/nx_timestamp_sim.vhd b/scaler/source/nx_timestamp_sim.vhd index 18465e8..74348c7 100644 --- a/scaler/source/nx_timestamp_sim.vhd +++ b/scaler/source/nx_timestamp_sim.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nxyter_timestamp_sim is port( diff --git a/scaler/source/nx_trigger_generator.vhd b/scaler/source/nx_trigger_generator.vhd index 2b51489..3d239c1 100644 --- a/scaler/source/nx_trigger_generator.vhd +++ b/scaler/source/nx_trigger_generator.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_trigger_generator is port ( diff --git a/scaler/source/nx_trigger_handler.vhd b/scaler/source/nx_trigger_handler.vhd index e925fb8..2dde37b 100644 --- a/scaler/source/nx_trigger_handler.vhd +++ b/scaler/source/nx_trigger_handler.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_trigger_handler is port ( diff --git a/scaler/source/nx_trigger_validate.vhd b/scaler/source/nx_trigger_validate.vhd index 661add2..8325485 100644 --- a/scaler/source/nx_trigger_validate.vhd +++ b/scaler/source/nx_trigger_validate.vhd @@ -3,7 +3,7 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.nxyter_components.all; +use work.scaler_components.all; entity nx_trigger_validate is generic ( diff --git a/scaler/source/pulse_delay.vhd b/scaler/source/pulse_delay.vhd index d6a1e9f..401d437 100644 --- a/scaler/source/pulse_delay.vhd +++ b/scaler/source/pulse_delay.vhd @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity pulse_delay is generic ( diff --git a/scaler/source/pulse_dtrans.vhd b/scaler/source/pulse_dtrans.vhd index cd3c80e..2675332 100644 --- a/scaler/source/pulse_dtrans.vhd +++ b/scaler/source/pulse_dtrans.vhd @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity pulse_dtrans is generic ( diff --git a/scaler/source/pulse_to_level.vhd b/scaler/source/pulse_to_level.vhd index 1b91bf8..0836494 100644 --- a/scaler/source/pulse_to_level.vhd +++ b/scaler/source/pulse_to_level.vhd @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity pulse_to_level is generic ( diff --git a/scaler/source/scaler.vhd b/scaler/source/scaler.vhd index 706b975..575392d 100644 --- a/scaler/source/scaler.vhd +++ b/scaler/source/scaler.vhd @@ -24,33 +24,10 @@ entity scaler is PLL_NX_CLK_LOCK_IN : in std_logic; PLL_RESET_OUT : out std_logic; TRIGGER_OUT : out std_logic; - - -- I2C Ports - I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line - I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line - I2C_SM_RESET_OUT : inout std_logic; -- reset nXyter I2C SMachine - I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers - - -- ADC SPI - SPI_SCLK_OUT : out std_logic; - SPI_SDIO_INOUT : inout std_logic; - SPI_CSB_OUT : out std_logic; - -- nXyter Timestamp Ports - NX_TIMESTAMP_CLK_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX_RESET_OUT : out std_logic; - NX_TESTPULSE_OUT : out std_logic; - NX_TIMESTAMP_TRIGGER_OUT : out std_logic; - - -- ADC nXyter Pulse Hight Ports - ADC_SAMPLE_CLK_OUT : out std_logic; - ADC_FCLK_IN : in std_logic; - ADC_DCLK_IN : in std_logic; - ADC_A_IN : in std_logic; - ADC_B_IN : in std_logic; - ADC_NX_IN : in std_logic; - ADC_D_IN : in std_logic; + -- Scaler Channels + SCALER_LATCH_IN : in std_logic; + SCALER_CHANNELS_IN : in std_logic_vector (7 downto 0); -- Input Triggers TIMING_TRIGGER_IN : in std_logic; @@ -101,7 +78,7 @@ architecture Behavioral of scaler is ------------------------------------------------------------------------------- -- Bus Handler - constant NUM_PORTS : integer := 13; + constant NUM_PORTS : integer := 2; signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); @@ -215,26 +192,46 @@ architecture Behavioral of scaler is signal error_event_buffer : std_logic; -- Debug Handler - constant DEBUG_NUM_PORTS : integer := 14; + constant DEBUG_NUM_PORTS : integer := 1; -- 14 signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1); -begin + ---------------------------------------------------------------------- + -- Testing Delay + ---------------------------------------------------------------------- -------------------------------------------------------------------------------- --- DEBUG -------------------------------------------------------------------------------- - -- DEBUG_LINE_OUT(0) <= CLK_IN; - -- DEBUG_LINE_OUT(15 downto 0) <= (others => '0'); - -- See Multiplexer + signal clock_div : unsigned(11 downto 0); + signal clk_pulse : std_logic; + + signal scaler_counter : unsigned(11 downto 0); + signal input_pulse : std_logic; + signal INPUT : std_logic; -------------------------------------------------------------------------------- --- Errors -------------------------------------------------------------------------------- - error_all(0) <= error_data_receiver; - error_all(1) <= error_data_validate; - error_all(2) <= error_event_buffer; - error_all(3) <= not nxyter_online; - error_all(7 downto 4) <= (others => '0'); + signal debug_test : std_logic_vector(15 downto 0); + + ---------------------------------------------------------------------- + -- Reset + ---------------------------------------------------------------------- + signal reset_scaler_clk_in_ff : std_logic; + signal reset_scaler_clk_in_f : std_logic; + signal RESET_SCALER_CLK_IN : std_logic; + + attribute syn_keep : boolean; + attribute syn_keep of reset_scaler_clk_in_ff : signal is true; + attribute syn_keep of reset_scaler_clk_in_f : signal is true; + + attribute syn_preserve : boolean; + attribute syn_preserve of reset_scaler_clk_in_ff : signal is true; + attribute syn_preserve of reset_scaler_clk_in_f : signal is true; + +begin + ----------------------------------------------------------------------------- + -- Reset Domain Transfer + ----------------------------------------------------------------------------- + reset_scaler_clk_in_ff <= RESET_IN when rising_edge(CLK_NX_MAIN_IN); + reset_scaler_clk_in_f <= reset_scaler_clk_in_ff + when rising_edge(CLK_NX_MAIN_IN); + RESET_SCALER_CLK_IN <= reset_scaler_clk_in_f + when rising_edge(CLK_NX_MAIN_IN); ------------------------------------------------------------------------------- -- Port Maps @@ -244,37 +241,15 @@ begin generic map( PORT_NUMBER => NUM_PORTS, - PORT_ADDRESSES => ( 0 => x"0100", -- NX Status Handler - 1 => x"0040", -- I2C Master - 2 => x"0500", -- Data Receiver - 3 => x"0080", -- Event Buffer - 4 => x"0060", -- SPI Master - 5 => x"0140", -- Trigger Generator - 6 => x"0120", -- Data Validate - 7 => x"0160", -- Trigger Handler - 8 => x"0400", -- Trigger Validate - 9 => x"0200", -- NX Register Setup - 10 => x"0800", -- NX Histograms - 11 => x"0020", -- Debug Handler - 12 => x"0000", -- Data Delay - others => x"0000" - ), + PORT_ADDRESSES => (0 => x"0020", -- Debug Handler + 1 => x"0040", -- Scaler Channel 0 + others => x"0000" + ), - PORT_ADDR_MASK => ( 0 => 4, -- NX Status Handler - 1 => 1, -- I2C master - 2 => 5, -- Data Receiver - 3 => 3, -- Event Buffer - 4 => 0, -- SPI Master - 5 => 3, -- Trigger Generator - 6 => 5, -- Data Validate - 7 => 4, -- Trigger Handler - 8 => 6, -- Trigger Validate - 9 => 9, -- NX Register Setup - 10 => 11, -- NX Histograms - 11 => 0, -- Debug Handler - 12 => 3, -- Data Delay - others => 0 - ), + PORT_ADDR_MASK => (0 => 0, -- Debug Handler + 1 => 2, -- Scaler Channel 0 + others => 0 + ), PORT_MASK_ENABLE => 1 ) @@ -310,509 +285,53 @@ begin ); ------------------------------------------------------------------------------- --- Registers -------------------------------------------------------------------------------- - nx_status_1: nx_status - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - - PLL_NX_CLK_LOCK_IN => PLL_NX_CLK_LOCK_IN, - PLL_ADC_DCLK_LOCK_IN => '1', - PLL_ADC_SCLK_LOCK_IN => pll_sadc_clk_lock, - PLL_RESET_OUT => PLL_RESET_OUT, - - I2C_SM_RESET_OUT => I2C_SM_RESET_OUT, - I2C_REG_RESET_OUT => i2c_reg_reset_o, - NX_ONLINE_OUT => nxyter_online, - - ERROR_ALL_IN => error_all, - - SLV_READ_IN => slv_read(0), - SLV_WRITE_IN => slv_write(0), - SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), - SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32), - SLV_ADDR_IN => slv_addr(0*16+15 downto 0*16), - SLV_ACK_OUT => slv_ack(0), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(0), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0), - - DEBUG_OUT => debug_line(0) - ); - - nx_register_setup_1: nx_register_setup - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - I2C_ONLINE_IN => nxyter_online, - I2C_COMMAND_OUT => i2c_command, - I2C_COMMAND_BUSY_IN => i2c_command_busy, - I2C_DATA_IN => i2c_data, - I2C_DATA_BYTES_IN => i2c_data_bytes, - I2C_LOCK_OUT => i2c_lock, - I2C_REG_RESET_IN => i2c_reg_reset_o, - SPI_COMMAND_OUT => spi_command, - SPI_COMMAND_BUSY_IN => spi_command_busy, - SPI_DATA_IN => spi_data, - SPI_LOCK_OUT => spi_lock, - INT_READ_IN => int_read, - INT_ADDR_IN => int_addr, - INT_ACK_OUT => int_ack, - INT_DATA_OUT => int_data, - NX_CLOCK_ON_OUT => nxyter_clock_on, - SLV_READ_IN => slv_read(9), - SLV_WRITE_IN => slv_write(9), - SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32), - SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32), - SLV_ADDR_IN => slv_addr(9*16+15 downto 9*16), - SLV_ACK_OUT => slv_ack(9), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(9), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(9), - - DEBUG_OUT => debug_line(1) - ); - -------------------------------------------------------------------------------- --- I2C master block for accessing the nXyter -------------------------------------------------------------------------------- - - nx_i2c_master_1: nx_i2c_master - generic map ( - I2C_SPEED => x"3e8" - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - SDA_INOUT => I2C_SDA_INOUT, - SCL_INOUT => I2C_SCL_INOUT, - INTERNAL_COMMAND_IN => i2c_command, - COMMAND_BUSY_OUT => i2c_command_busy, - I2C_DATA_OUT => i2c_data, - I2C_DATA_BYTES_OUT => i2c_data_bytes, - I2C_LOCK_IN => i2c_lock, - SLV_READ_IN => slv_read(1), - SLV_WRITE_IN => slv_write(1), - SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), - SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), - SLV_ADDR_IN => slv_addr(1*16+15 downto 1*16), - SLV_ACK_OUT => slv_ack(1), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(1), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1), - - DEBUG_OUT => debug_line(2) - ); - -------------------------------------------------------------------------------- --- SPI master block to access the ADC +-- DEBUG ------------------------------------------------------------------------------- - - adc_spi_master_1: adc_spi_master - generic map ( - SPI_SPEED => x"c8" - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - SCLK_OUT => SPI_SCLK_OUT, - SDIO_INOUT => SPI_SDIO_INOUT, - CSB_OUT => SPI_CSB_OUT, - INTERNAL_COMMAND_IN => spi_command, - COMMAND_ACK_OUT => spi_command_busy, - SPI_DATA_OUT => spi_data, - SPI_LOCK_IN => spi_lock, - SLV_READ_IN => slv_read(4), - SLV_WRITE_IN => slv_write(4), - SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32), - SLV_DATA_IN => slv_data_wr(4*32+31 downto 4*32), - SLV_ACK_OUT => slv_ack(4), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(4), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4), - - DEBUG_OUT => debug_line(3) - ); -------------------------------------------------------------------------------- --- FPGA Timestamp -------------------------------------------------------------------------------- + --DEBUG_LINE_OUT(15 downto 0) <= (others => '0'); + -- See Multiplexer - nx_fpga_timestamp_1: nx_fpga_timestamp - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, - TIMESTAMP_RESET_IN => nx_timestamp_reset, - TIMESTAMP_RESET_OUT => nx_timestamp_reset_o, - TRIGGER_IN => timestamp_trigger, - TIMESTAMP_HOLD_OUT => timestamp_hold, - TIMESTAMP_TRIGGER_OUT => NX_TIMESTAMP_TRIGGER_OUT, - SLV_READ_IN => open, - SLV_WRITE_IN => open, - SLV_DATA_OUT => open, - SLV_DATA_IN => open, - SLV_ACK_OUT => open, - SLV_NO_MORE_DATA_OUT => open, - SLV_UNKNOWN_ADDR_OUT => open, - - DEBUG_OUT => debug_line(4) - ); - -------------------------------------------------------------------------------- --- Trigger Handler -------------------------------------------------------------------------------- - - nx_trigger_handler_1: nx_trigger_handler - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, - NXYTER_OFFLINE_IN => not nxyter_online, - - TIMING_TRIGGER_IN => TIMING_TRIGGER_IN, - LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, - LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN, - LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN, - LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN, - - LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, - LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, - LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, - LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN, - LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN, - - FEE_DATA_OUT => FEE_DATA_OUT, - FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, - FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT, - FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT, - FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT, - - FEE_DATA_0_IN => fee_data_o_0, - FEE_DATA_WRITE_0_IN => fee_data_write_o_0, - FEE_DATA_1_IN => fee_data_o_1, - FEE_DATA_WRITE_1_IN => fee_data_write_o_1, - INTERNAL_TRIGGER_IN => internal_trigger, - - TRIGGER_VALIDATE_BUSY_IN => trigger_validate_busy, - TRIGGER_BUSY_0_IN => trigger_evt_busy_0, - TRIGGER_BUSY_1_IN => trigger_evt_busy_1, - - VALID_TRIGGER_OUT => trigger, - TIMESTAMP_TRIGGER_OUT => timestamp_trigger, - TRIGGER_TIMING_OUT => trigger_timing, - TRIGGER_STATUS_OUT => trigger_status, - TRIGGER_CALIBRATION_OUT => trigger_calibration, - FAST_CLEAR_OUT => fast_clear, - TRIGGER_BUSY_OUT => trigger_busy, - - NX_TESTPULSE_OUT => NX_TESTPULSE_OUT, - - SLV_READ_IN => slv_read(7), - SLV_WRITE_IN => slv_write(7), - SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32), - SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32), - SLV_ADDR_IN => slv_addr(7*16+15 downto 7*16), - SLV_ACK_OUT => slv_ack(7), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(7), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7), - - DEBUG_OUT => debug_line(5) - ); - -------------------------------------------------------------------------------- --- NX Trigger Generator -------------------------------------------------------------------------------- - - nx_trigger_generator_1: nx_trigger_generator + PROC_CLOCK_DIVIDER: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1') then + clock_div <= (others => '0'); + clk_pulse <= '0'; + else + if (clock_div < x"3e8") then + clk_pulse <= '0'; + clock_div <= clock_div + 1; + else + clk_pulse <= '1'; + clock_div <= (others => '0'); + end if; + end if; + end if; + end process PROC_CLOCK_DIVIDER; + + + scaler_channel_1: scaler_channel port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - - TRIGGER_BUSY_IN => trigger_busy, - EXTERNAL_TRIGGER_OUT => TRIGGER_OUT, - INTERNAL_TRIGGER_OUT => internal_trigger, + CLK_SCALER_IN => CLK_NX_MAIN_IN, + RESET_SCALER_IN => RESET_SCALER_CLK_IN, + LATCH_IN => clk_pulse, + PULSE_IN => clk_pulse, + INHIBIT_IN => '0', - DATA_IN => data_recv, - DATA_CLK_IN => data_clk_recv, + SLV_READ_IN => slv_read(1), + SLV_WRITE_IN => slv_write(1), + SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), + SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), + SLV_ADDR_IN => slv_addr(1*16+15 downto 1*16), + SLV_ACK_OUT => slv_ack(1), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(1), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1), - SLV_READ_IN => slv_read(5), - SLV_WRITE_IN => slv_write(5), - SLV_DATA_OUT => slv_data_rd(5*32+31 downto 5*32), - SLV_DATA_IN => slv_data_wr(5*32+31 downto 5*32), - SLV_ADDR_IN => slv_addr(5*16+15 downto 5*16), - SLV_ACK_OUT => slv_ack(5), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(5), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5), - - DEBUG_OUT => debug_line(6) - ); - -------------------------------------------------------------------------------- --- nXyter Data Receiver -------------------------------------------------------------------------------- - - nx_data_receiver_1: nx_data_receiver - generic map ( - DEBUG_ENABLE => true - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TRIGGER_IN => trigger_timing, -- for debugging only - NX_ONLINE_IN => nxyter_online, - NX_CLOCK_ON_IN => nxyter_clock_on, - - NX_DATA_CLK_IN => NX_TIMESTAMP_CLK_IN, - NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, - NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset, - - ADC_SAMPLE_CLK_OUT => ADC_SAMPLE_CLK_OUT, - ADC_SCLK_LOCK_OUT => pll_sadc_clk_lock, - - ADC_FCLK_IN => ADC_FCLK_IN, - ADC_DCLK_IN => ADC_DCLK_IN, - ADC_A_IN => ADC_A_IN, - ADC_B_IN => ADC_B_IN, - ADC_NX_IN => ADC_NX_IN, - ADC_D_IN => ADC_D_IN, - - DATA_OUT => data_recv, - DATA_CLK_OUT => data_clk_recv, - - SLV_READ_IN => slv_read(2), - SLV_WRITE_IN => slv_write(2), - SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), - SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32), - SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16), - SLV_ACK_OUT => slv_ack(2), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), - - ADC_TR_ERROR_IN => adc_tr_error, - DISABLE_ADC_OUT => disable_adc_receiver, - ERROR_OUT => error_data_receiver, - DEBUG_OUT => debug_line(7) - ); - -------------------------------------------------------------------------------- --- NX and ADC Data Delay FIFO -------------------------------------------------------------------------------- - nx_data_delay_1: nx_data_delay - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - - DATA_IN => data_recv, - DATA_CLK_IN => data_clk_recv, - - DATA_OUT => data_delayed, - DATA_CLK_OUT => data_clk_delayed, - - FIFO_DELAY_IN => data_fifo_delay, - - SLV_READ_IN => slv_read(12), - SLV_WRITE_IN => slv_write(12), - SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32), - SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32), - SLV_ADDR_IN => slv_addr(12*16+15 downto 12*16), - SLV_ACK_OUT => slv_ack(12), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(12), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(12), - - DEBUG_OUT => debug_line(8) - ); - -------------------------------------------------------------------------------- --- Timestamp Decoder and Valid Data Filter -------------------------------------------------------------------------------- - - nx_data_validate_1: nx_data_validate - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - - DATA_IN => data_delayed, - DATA_CLK_IN => data_clk_delayed, - - TIMESTAMP_OUT => timestamp, - CHANNEL_OUT => timestamp_channel_id, - TIMESTAMP_STATUS_OUT => timestamp_status, - ADC_DATA_OUT => adc_data, - DATA_CLK_OUT => data_clk, - - NX_TOKEN_RETURN_OUT => nx_token_return, - NX_NOMORE_DATA_OUT => nx_nomore_data, - - SLV_READ_IN => slv_read(6), - SLV_WRITE_IN => slv_write(6), - SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32), - SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32), - SLV_ADDR_IN => slv_addr(6*16+15 downto 6*16), - SLV_ACK_OUT => slv_ack(6), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6), - - ADC_TR_ERROR_OUT => adc_tr_error, - DISABLE_ADC_IN => disable_adc_receiver, - ERROR_OUT => error_data_validate, - DEBUG_OUT => debug_line(9) - ); - -------------------------------------------------------------------------------- --- NX Trigger Validate -------------------------------------------------------------------------------- - - nx_trigger_validate_1: nx_trigger_validate - generic map ( - BOARD_ID => BOARD_ID, - VERSION_NUMBER => VERSION_NUMBER - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - - DATA_CLK_IN => data_clk, - TIMESTAMP_IN => timestamp, - CHANNEL_IN => timestamp_channel_id, - TIMESTAMP_STATUS_IN => timestamp_status, - ADC_DATA_IN => adc_data, - NX_TOKEN_RETURN_IN => nx_token_return, - NX_NOMORE_DATA_IN => nx_nomore_data, - - TRIGGER_IN => trigger, - TRIGGER_CALIBRATION_IN => trigger_calibration, - TRIGGER_BUSY_IN => trigger_busy, - FAST_CLEAR_IN => fast_clear, - TRIGGER_BUSY_OUT => trigger_validate_busy, - TIMESTAMP_FPGA_IN => timestamp_hold, - DATA_FIFO_DELAY_OUT => data_fifo_delay, - - DATA_OUT => trigger_data, - DATA_CLK_OUT => trigger_data_clk, - NOMORE_DATA_OUT => validate_nomore_data, - EVT_BUFFER_CLEAR_OUT => event_buffer_clear, - EVT_BUFFER_FULL_IN => evt_buffer_full, - - HISTOGRAM_RESET_OUT => reset_hists, - HISTOGRAM_FILL_OUT => trigger_validate_fill, - HISTOGRAM_BIN_OUT => trigger_validate_bin, - HISTOGRAM_ADC_OUT => trigger_validate_adc, - HISTOGRAM_TS_OUT => trigger_validate_ts, - HISTOGRAM_PILEUP_OUT => trigger_validate_pileup, - HISTOGRAM_OVERFLOW_OUT => trigger_validate_ovfl, - - SLV_READ_IN => slv_read(8), - SLV_WRITE_IN => slv_write(8), - SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32), - SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32), - SLV_ADDR_IN => slv_addr(8*16+15 downto 8*16), - SLV_ACK_OUT => slv_ack(8), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(8), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8), - - DEBUG_OUT => debug_line(10) - ); - -------------------------------------------------------------------------------- --- Data Buffer FIFO -------------------------------------------------------------------------------- - - nx_event_buffer_1: nx_event_buffer - generic map ( - BOARD_ID => BOARD_ID - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - RESET_DATA_BUFFER_IN => event_buffer_clear, - NXYTER_OFFLINE_IN => not nxyter_online, - - DATA_IN => trigger_data, - DATA_CLK_IN => trigger_data_clk, - EVT_NOMORE_DATA_IN => validate_nomore_data, - - TRIGGER_IN => trigger_timing, - FAST_CLEAR_IN => fast_clear, - TRIGGER_BUSY_OUT => trigger_evt_busy_0, - EVT_BUFFER_FULL_OUT => evt_buffer_full, - - FEE_DATA_OUT => fee_data_o_0, - FEE_DATA_WRITE_OUT => fee_data_write_o_0, - FEE_DATA_ALMOST_FULL_IN => FEE_DATA_ALMOST_FULL_IN, - - SLV_READ_IN => slv_read(3), - SLV_WRITE_IN => slv_write(3), - SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32), - SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32), - SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16), - SLV_ACK_OUT => slv_ack(3), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(3), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3), - - ERROR_OUT => error_event_buffer, - DEBUG_OUT => debug_line(11) - ); - - nx_status_event_1: nx_status_event - generic map ( - BOARD_ID => BOARD_ID, - VERSION_NUMBER => VERSION_NUMBER - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - NXYTER_OFFLINE_IN => not nxyter_online, - TRIGGER_IN => trigger_status, - FAST_CLEAR_IN => fast_clear, - TRIGGER_BUSY_OUT => trigger_evt_busy_1, - FEE_DATA_OUT => fee_data_o_1, - FEE_DATA_WRITE_OUT => fee_data_write_o_1, - FEE_DATA_ALMOST_FULL_IN => FEE_DATA_ALMOST_FULL_IN, - INT_READ_OUT => int_read, - INT_ADDR_OUT => int_addr, - INT_ACK_IN => int_ack, - INT_DATA_IN => int_data, - DEBUG_OUT => debug_line(13) - ); - - nx_histograms_1: nx_histograms - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - - RESET_HISTS_IN => reset_hists, - CHANNEL_FILL_IN => trigger_validate_fill, - CHANNEL_ID_IN => trigger_validate_bin, - CHANNEL_ADC_IN => trigger_validate_adc, - CHANNEL_TS_IN => trigger_validate_ts, - CHANNEL_PILEUP_IN => trigger_validate_pileup, - CHANNEL_OVERFLOW_IN => trigger_validate_ovfl, - - SLV_READ_IN => slv_read(10), - SLV_WRITE_IN => slv_write(10), - SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32), - SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32), - SLV_ADDR_IN => slv_addr(10*16+15 downto 10*16), - SLV_ACK_OUT => slv_ack(10), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(10), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(10), - - DEBUG_OUT => debug_line(12) + DEBUG_OUT => debug_line(0) ); -------------------------------------------------------------------------------- --- nXyter Signals -------------------------------------------------------------------------------- - NX_RESET_OUT <= not nx_timestamp_reset_o; - -------------------------------------------------------------------------------- --- I2C Signals -------------------------------------------------------------------------------- - - I2C_REG_RESET_OUT <= not i2c_reg_reset_o; - -------------------------------------------------------------------------------- --- Others -------------------------------------------------------------------------------- - ------------------------------------------------------------------------------- -- DEBUG Line Select ------------------------------------------------------------------------------- @@ -825,14 +344,14 @@ begin RESET_IN => RESET_IN, DEBUG_LINE_IN => debug_line, DEBUG_LINE_OUT => DEBUG_LINE_OUT, - SLV_READ_IN => slv_read(11), - SLV_WRITE_IN => slv_write(11), - SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32), - SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32), - SLV_ADDR_IN => slv_addr(11*16+15 downto 11*16), - SLV_ACK_OUT => slv_ack(11), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(11), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(11) + SLV_READ_IN => slv_read(0), + SLV_WRITE_IN => slv_write(0), + SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), + SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32), + SLV_ADDR_IN => slv_addr(0*16+15 downto 0*16), + SLV_ACK_OUT => slv_ack(0), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(0), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0) ); ------------------------------------------------------------------------------- diff --git a/scaler/source/scaler_components.vhd b/scaler/source/scaler_components.vhd index ef64b2f..54ae3ab 100644 --- a/scaler/source/scaler_components.vhd +++ b/scaler/source/scaler_components.vhd @@ -2,68 +2,75 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -package nxyter_components is +package scaler_components is ------------------------------------------------------------------------------- -- TRBNet interfaces ------------------------------------------------------------------------------- - + component scaler generic ( BOARD_ID : std_logic_vector(1 downto 0)); port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - CLK_NX_MAIN_IN : in std_logic; - PLL_NX_CLK_LOCK_IN : in std_logic; - PLL_RESET_OUT : out std_logic; - TRIGGER_OUT : out std_logic; - I2C_SDA_INOUT : inout std_logic; - I2C_SCL_INOUT : inout std_logic; - I2C_SM_RESET_OUT : inout std_logic; - I2C_REG_RESET_OUT : out std_logic; - SPI_SCLK_OUT : out std_logic; - SPI_SDIO_INOUT : inout std_logic; - SPI_CSB_OUT : out std_logic; - NX_TIMESTAMP_CLK_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX_RESET_OUT : out std_logic; - NX_TESTPULSE_OUT : out std_logic; - NX_TIMESTAMP_TRIGGER_OUT : out std_logic; - ADC_SAMPLE_CLK_OUT : out std_logic; - ADC_FCLK_IN : in std_logic; - ADC_DCLK_IN : in std_logic; - ADC_A_IN : in std_logic; - ADC_B_IN : in std_logic; - ADC_NX_IN : in std_logic; - ADC_D_IN : in std_logic; - TIMING_TRIGGER_IN : in std_logic; - LVL1_TRG_DATA_VALID_IN : in std_logic; - LVL1_VALID_TIMING_TRG_IN : in std_logic; - LVL1_VALID_NOTIMING_TRG_IN : in std_logic; - LVL1_INVALID_TRG_IN : in std_logic; - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - FEE_TRG_RELEASE_OUT : out std_logic; - FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATA_FINISHED_OUT : out std_logic; - FEE_DATA_ALMOST_FULL_IN : in std_logic; - REGIO_ADDR_IN : in std_logic_vector(15 downto 0); - REGIO_DATA_IN : in std_logic_vector(31 downto 0); - REGIO_DATA_OUT : out std_logic_vector(31 downto 0); - REGIO_READ_ENABLE_IN : in std_logic; - REGIO_WRITE_ENABLE_IN : in std_logic; - REGIO_TIMEOUT_IN : in std_logic; - REGIO_DATAREADY_OUT : out std_logic; - REGIO_WRITE_ACK_OUT : out std_logic; - REGIO_NO_MORE_DATA_OUT : out std_logic; - REGIO_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLK_NX_MAIN_IN : in std_logic; + PLL_NX_CLK_LOCK_IN : in std_logic; + PLL_RESET_OUT : out std_logic; + TRIGGER_OUT : out std_logic; + SCALER_LATCH_IN : in std_logic; + SCALER_CHANNELS_IN : in std_logic_vector (7 downto 0); + TIMING_TRIGGER_IN : in std_logic; + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; + LVL1_INVALID_TRG_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + FEE_TRG_RELEASE_OUT : out std_logic; + FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + FEE_DATA_ALMOST_FULL_IN : in std_logic; + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); + REGIO_DATA_IN : in std_logic_vector(31 downto 0); + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); + REGIO_READ_ENABLE_IN : in std_logic; + REGIO_WRITE_ENABLE_IN : in std_logic; + REGIO_TIMEOUT_IN : in std_logic; + REGIO_DATAREADY_OUT : out std_logic; + REGIO_WRITE_ACK_OUT : out std_logic; + REGIO_NO_MORE_DATA_OUT : out std_logic; + REGIO_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) + ); + end component; + +---------------------------------------------------------------------- +-- Scaler Channel Entity +---------------------------------------------------------------------- + component scaler_channel + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLK_SCALER_IN : in std_logic; + RESET_SCALER_IN : in std_logic; + LATCH_IN : in std_logic; + PULSE_IN : in std_logic; + INHIBIT_IN : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; diff --git a/scaler/source/signal_async_to_pulse.vhd b/scaler/source/signal_async_to_pulse.vhd index 57a85ed..b8fa049 100644 --- a/scaler/source/signal_async_to_pulse.vhd +++ b/scaler/source/signal_async_to_pulse.vhd @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use work.nxyter_components.all; +use work.scaler_components.all; entity signal_async_to_pulse is generic ( diff --git a/scaler/trb3_periph_scaler.lpf b/scaler/trb3_periph_scaler.lpf index 50e70e7..13f7813 100644 --- a/scaler/trb3_periph_scaler.lpf +++ b/scaler/trb3_periph_scaler.lpf @@ -89,43 +89,30 @@ IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST; -# nXyter 1 - -LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46 +# Scaler LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29 LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45 #LOCATE COMP "NX1_DATA_CLK_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -LOCATE COMP "NX1_DATA_CLK_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE -LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34 -LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36 -LOCATE COMP "NX1_I2C_SDA_INOUT" SITE "R5"; #DQLL1_6 #42 -LOCATE COMP "NX1_I2C_SCL_INOUT" SITE "R6"; #DQLL1_7 #44 - -LOCATE COMP "NX1_ADC_D_IN" SITE "B2"; #DQUL0_0 #74 -LOCATE COMP "NX1_ADC_A_IN" SITE "D4"; #DQUL0_2 #78 -LOCATE COMP "NX1_ADC_NX_IN" SITE "C3"; #DQUL0_4 #82 -LOCATE COMP "NX1_ADC_DCLK_IN" SITE "G5"; #DQSUL0_T #86 -LOCATE COMP "NX1_ADC_B_IN" SITE "E3"; #DQUL0_6 #90 -LOCATE COMP "NX1_ADC_FCLK_IN" SITE "H6"; #DQUL0_8 #94 -LOCATE COMP "NX1_ADC_SAMPLE_CLK_OUT" SITE "H5"; #DQUL1_6 #89 LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73 LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77 LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81 -LOCATE COMP "NX1_TIMESTAMP_IN_0" SITE "K2"; #DQUL2_0 #50 -LOCATE COMP "NX1_TIMESTAMP_IN_1" SITE "J4"; #DQUL2_2 #54 -LOCATE COMP "NX1_TIMESTAMP_IN_2" SITE "D1"; #DQUL2_4 #58 -LOCATE COMP "NX1_TIMESTAMP_IN_3" SITE "E1"; #DQUL2_6 #66 -#LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L5"; #DQUL2_8 #70 -LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L2"; #DQUL3_6 # +LOCATE COMP "SCALER_LATCH_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE +LOCATE COMP "SCALER_CHANNELS_IN_0" SITE "K2"; #DQUL2_0 #50 +LOCATE COMP "SCALER_CHANNELS_IN_1" SITE "J4"; #DQUL2_2 #54 +LOCATE COMP "SCALER_CHANNELS_IN_2" SITE "D1"; #DQUL2_4 #58 +LOCATE COMP "SCALER_CHANNELS_IN_3" SITE "E1"; #DQUL2_6 #66 +#LOCATE COMP "SCALER_CHANNELS_IN_6" SITE "L5"; #DQUL2_8 #70 +LOCATE COMP "SCALER_CHANNELS_IN_4" SITE "L2"; #DQUL3_6 # -LOCATE COMP "NX1_TIMESTAMP_IN_5" SITE "H2"; #DQUL3_0 #49 -LOCATE COMP "NX1_TIMESTAMP_IN_6" SITE "K3"; #DQUL3_2 #53 -LOCATE COMP "NX1_TIMESTAMP_IN_7" SITE "H1"; #DQUL3_4 #57 +LOCATE COMP "SCALER_CHANNELS_IN_5" SITE "H2"; #DQUL3_0 #49 +LOCATE COMP "SCALER_CHANNELS_IN_6" SITE "K3"; #DQUL3_2 #53 +LOCATE COMP "SCALER_CHANNELS_IN_7" SITE "H1"; #DQUL3_4 #57 +LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46 #DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ; @@ -164,22 +151,22 @@ IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=4; IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4; # Nxyter Debug Lines Addon Board -LOCATE COMP "NX1_DEBUG_LINE_1" SITE "R25"; #DQLR2_0 #170 -LOCATE COMP "NX1_DEBUG_LINE_3" SITE "R26"; #DQLR2_1 #172 -LOCATE COMP "NX1_DEBUG_LINE_5" SITE "T25"; #DQLR2_2 #174 -LOCATE COMP "NX1_DEBUG_LINE_7" SITE "T24"; #DQLR2_3 #176 -LOCATE COMP "NX1_DEBUG_LINE_9" SITE "T26"; #DQLR2_4 #178 -LOCATE COMP "NX1_DEBUG_LINE_11" SITE "U26"; #DQLR2_5 #180 -LOCATE COMP "NX1_DEBUG_LINE_13" SITE "U24"; #DQLR2_6 #186 -LOCATE COMP "NX1_DEBUG_LINE_15" SITE "V24"; #DQLR2_7 #188 -LOCATE COMP "NX1_DEBUG_LINE_14" SITE "W23"; #DQLR1_0 #169 -LOCATE COMP "NX1_DEBUG_LINE_12" SITE "W22"; #DQLR1_1 #171 -LOCATE COMP "NX1_DEBUG_LINE_10" SITE "AA25"; #DQLR1_2 #173 -LOCATE COMP "NX1_DEBUG_LINE_8" SITE "Y24"; #DQLR1_3 #175 -LOCATE COMP "NX1_DEBUG_LINE_6" SITE "AA26"; #DQLR1_4 #177 -LOCATE COMP "NX1_DEBUG_LINE_4" SITE "AB26"; #DQLR1_5 #179 -LOCATE COMP "NX1_DEBUG_LINE_2" SITE "AA24"; #DQLR1_6 #185 -LOCATE COMP "NX1_DEBUG_LINE_0" SITE "AA23"; #DQLR1_7 #187 +LOCATE COMP "SCALER_DEBUG_LINE_1" SITE "R25"; #DQLR2_0 #170 +LOCATE COMP "SCALER_DEBUG_LINE_3" SITE "R26"; #DQLR2_1 #172 +LOCATE COMP "SCALER_DEBUG_LINE_5" SITE "T25"; #DQLR2_2 #174 +LOCATE COMP "SCALER_DEBUG_LINE_7" SITE "T24"; #DQLR2_3 #176 +LOCATE COMP "SCALER_DEBUG_LINE_9" SITE "T26"; #DQLR2_4 #178 +LOCATE COMP "SCALER_DEBUG_LINE_11" SITE "U26"; #DQLR2_5 #180 +LOCATE COMP "SCALER_DEBUG_LINE_13" SITE "U24"; #DQLR2_6 #186 +LOCATE COMP "SCALER_DEBUG_LINE_15" SITE "V24"; #DQLR2_7 #188 +LOCATE COMP "SCALER_DEBUG_LINE_14" SITE "W23"; #DQLR1_0 #169 +LOCATE COMP "SCALER_DEBUG_LINE_12" SITE "W22"; #DQLR1_1 #171 +LOCATE COMP "SCALER_DEBUG_LINE_10" SITE "AA25"; #DQLR1_2 #173 +LOCATE COMP "SCALER_DEBUG_LINE_8" SITE "Y24"; #DQLR1_3 #175 +LOCATE COMP "SCALER_DEBUG_LINE_6" SITE "AA26"; #DQLR1_4 #177 +LOCATE COMP "SCALER_DEBUG_LINE_4" SITE "AB26"; #DQLR1_5 #179 +LOCATE COMP "SCALER_DEBUG_LINE_2" SITE "AA24"; #DQLR1_6 #185 +LOCATE COMP "SCALER_DEBUG_LINE_0" SITE "AA23"; #DQLR1_7 #187 DEFINE PORT GROUP "NX1_DEBUG_LINE_group" "NX1_DEBUG_LINE_*" ; IOBUF GROUP "NX1_DEBUG_LINE_group" IO_TYPE=LVCMOS25 SLEWRATE=FAST; diff --git a/scaler/trb3_periph_scaler.p2t b/scaler/trb3_periph_scaler.p2t index 2a1babe..b36220e 100644 --- a/scaler/trb3_periph_scaler.p2t +++ b/scaler/trb3_periph_scaler.p2t @@ -1,7 +1,7 @@ -w -i 2 -l 5 --n 8 +-n 1 -t 1 -s 1 -c 1 diff --git a/scaler/trb3_periph_scaler.prj b/scaler/trb3_periph_scaler.prj index cf4d31b..29cfbe2 100644 --- a/scaler/trb3_periph_scaler.prj +++ b/scaler/trb3_periph_scaler.prj @@ -143,7 +143,7 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" # nXyter Files -add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd" +add_file -vhdl -lib "work" "cores/pll_clk400.vhd" add_file -vhdl -lib "work" "cores/pll_adc_sampling_clk.vhd" add_file -vhdl -lib "work" "cores/fifo_data_stream_44to44_dc.vhd" add_file -vhdl -lib "work" "cores/ram_dp_128x40.vhd" @@ -176,6 +176,7 @@ add_file -vhdl -lib "work" "source/debug_multiplexer.vhd" add_file -vhdl -lib "work" "source/fifo_44_data_delay_my.vhd" add_file -vhdl -lib "work" "source/scaler.vhd" +add_file -vhdl -lib "work" "source/scaler_channel.vhd" add_file -vhdl -lib "work" "source/nx_data_receiver.vhd" add_file -vhdl -lib "work" "source/nx_data_delay.vhd" add_file -vhdl -lib "work" "source/nx_data_validate.vhd" diff --git a/scaler/trb3_periph_scaler.vhd b/scaler/trb3_periph_scaler.vhd index 64b1d31..ab70efc 100644 --- a/scaler/trb3_periph_scaler.vhd +++ b/scaler/trb3_periph_scaler.vhd @@ -16,7 +16,7 @@ use ecp3.components.all; entity trb3_periph_scaler is port( --Clocks - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left! CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! @@ -37,36 +37,11 @@ entity trb3_periph_scaler is --Bit 2/3 output, serial link TX active --------------------------------------------------------------------------- - -- BEGIN AddonBoard nXyter + -- BEGIN AddonBoard Scaler --------------------------------------------------------------------------- - --Connections to NXYTER-FEB 1 - - NX1_RESET_OUT : out std_logic; - NX1_I2C_SDA_INOUT : inout std_logic; - NX1_I2C_SCL_INOUT : inout std_logic; - NX1_I2C_SM_RESET_OUT : inout std_logic; - NX1_I2C_REG_RESET_OUT : out std_logic; - NX1_SPI_SCLK_OUT : out std_logic; - NX1_SPI_SDIO_INOUT : inout std_logic; - NX1_SPI_CSB_OUT : out std_logic; - NX1_DATA_CLK_IN : in std_logic; - NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX1_MAIN_CLK_OUT : out std_logic; - NX1_TESTPULSE_OUT : out std_logic; - NX1_TS_HOLD_OUT : out std_logic; - NX1_ADC_FCLK_IN : in std_logic; - NX1_ADC_DCLK_IN : in std_logic; - NX1_ADC_SAMPLE_CLK_OUT : out std_logic; - NX1_ADC_A_IN : in std_logic; - NX1_ADC_B_IN : in std_logic; - NX1_ADC_NX_IN : in std_logic; - NX1_ADC_D_IN : in std_logic; - NX1B_ADC_FCLK_IN : in std_logic; - NX1B_ADC_DCLK_IN : in std_logic; - NX1B_ADC_A_IN : in std_logic; - NX1B_ADC_B_IN : in std_logic; - NX1B_ADC_NX_IN : in std_logic; - NX1B_ADC_D_IN : in std_logic; + --Connections to Scaler Channels + SCALER_LATCH_IN : in std_logic; + SCALER_CHANNELS_IN : in std_logic_vector (7 downto 0); --------------------------------------------------------------------------- -- END AddonBoard nXyter @@ -86,9 +61,10 @@ entity trb3_periph_scaler is LED_RED : out std_logic; LED_YELLOW : out std_logic; SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0); - NX1_DEBUG_LINE : out std_logic_vector(15 downto 0) + TEST_LINE : out std_logic_vector(15 downto 0) + --SCALER_DEBUG_LINE : out std_logic_vector(15 downto 0) ); attribute syn_useioff : boolean; @@ -109,9 +85,9 @@ entity trb3_periph_scaler is attribute syn_useioff of FLASH_DOUT : signal is true; attribute syn_useioff of FPGA5_COMM : signal is true; attribute syn_useioff of TEST_LINE : signal is false; - attribute syn_useioff of NX1_DEBUG_LINE : signal is false; + --attribute syn_useioff of SCALER_DEBUG_LINE : signal is false; --attribute syn_useioff of INP : signal is false; - attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true; + attribute syn_useioff of SCALER_CHANNELS_IN : signal is true; --attribute syn_useioff of NX1_ADC_NX_IN : signal is true; --attribute syn_useioff of NX1_ADC_D_IN : signal is true; @@ -130,11 +106,6 @@ architecture Behavioral of trb3_periph_scaler is constant NUM_NXYTER : integer := 1; - -- For 250MHz PLL scaler clock, THE_32M_ODDR_1 - attribute ODDRAPPS : string; - attribute ODDRAPPS of THE_NX_MAIN_ODDR_1 : label is "SCLK_ALIGNED"; - -- attribute ODDRAPPS of THE_ADC_SAMPLE_ODDR_1 : label is "SCLK_ALIGNED"; - --Constants constant REGIO_NUM_STAT_REGS : integer := 5; constant REGIO_NUM_CTRL_REGS : integer := 3; @@ -257,13 +228,8 @@ architecture Behavioral of trb3_periph_scaler is -- SED Detection signal sed_error : std_logic; - signal sed_din : std_logic_vector(31 downto 0); - signal sed_dout : std_logic_vector(31 downto 0); - signal sed_write : std_logic := '0'; - signal sed_read : std_logic := '0'; - signal sed_ack : std_logic := '0'; - signal sed_nack : std_logic := '0'; - signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal bussed_rx : CTRLBUS_RX; + signal bussed_tx : CTRLBUS_TX; -- nXyter-FEB-Board Clocks signal nx_main_clk : std_logic; @@ -564,16 +530,16 @@ begin BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out, BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out, - BUS_READ_ENABLE_OUT(3) => sed_read, - BUS_WRITE_ENABLE_OUT(3) => sed_write, - BUS_DATA_OUT(3*32+31 downto 3*32) => sed_din, - BUS_ADDR_OUT(3*16+15 downto 3*16) => sed_addr, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(3*32+31 downto 3*32) => sed_dout, - BUS_DATAREADY_IN(3) => sed_ack, - BUS_WRITE_ACK_IN(3) => sed_ack, - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => sed_nack, + BUS_READ_ENABLE_OUT(3) => bussed_rx.read, + BUS_WRITE_ENABLE_OUT(3) => bussed_rx.write, + BUS_DATA_OUT(3*32+31 downto 3*32) => bussed_rx.data, + BUS_ADDR_OUT(3*16+15 downto 3*16) => bussed_rx.addr, + BUS_TIMEOUT_OUT(3) => bussed_rx.timeout, + BUS_DATA_IN(3*32+31 downto 3*32) => bussed_tx.data, + BUS_DATAREADY_IN(3) => bussed_tx.ack, + BUS_WRITE_ACK_IN(3) => bussed_tx.ack, + BUS_NO_MORE_DATA_IN(3) => bussed_tx.nack, + BUS_UNKNOWN_ADDR_IN(3) => bussed_tx.unknown, STAT_DEBUG => open ); @@ -651,7 +617,7 @@ begin ----------------------------------------------------------------------------- -- The xXyter-FEB #1 ----------------------------------------------------------------------------- - + scaler_0: scaler generic map ( BOARD_ID => "01" @@ -664,31 +630,10 @@ begin PLL_RESET_OUT => nx_pll_reset, TRIGGER_OUT => fee1_trigger, - - I2C_SDA_INOUT => NX1_I2C_SDA_INOUT, - I2C_SCL_INOUT => NX1_I2C_SCL_INOUT, - I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT, - I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT, - SPI_SCLK_OUT => NX1_SPI_SCLK_OUT, - SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT, - SPI_CSB_OUT => NX1_SPI_CSB_OUT, - - NX_TIMESTAMP_CLK_IN => NX1_DATA_CLK_IN, - NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN, - - NX_RESET_OUT => NX1_RESET_OUT, - NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT, - NX_TIMESTAMP_TRIGGER_OUT => NX1_TS_HOLD_OUT, - - ADC_SAMPLE_CLK_OUT => nx1_adc_sample_clk, - ADC_FCLK_IN => NX1_ADC_FCLK_IN, - ADC_DCLK_IN => NX1_ADC_DCLK_IN, - ADC_A_IN => NX1_ADC_A_IN, - ADC_B_IN => NX1_ADC_B_IN, - ADC_NX_IN => NX1_ADC_NX_IN, - ADC_D_IN => NX1_ADC_D_IN, - + SCALER_LATCH_IN => SCALER_LATCH_IN, + SCALER_CHANNELS_IN => SCALER_CHANNELS_IN, + TIMING_TRIGGER_IN => TRIGGER_RIGHT, LVL1_TRG_DATA_VALID_IN => trg_data_valid_i, LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i, @@ -718,39 +663,36 @@ begin REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out, REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out, - DEBUG_LINE_OUT => nx1_debug_line_o - --DEBUG_LINE_OUT => open + --DEBUG_LINE_OUT => TEST_LINE + DEBUG_LINE_OUT => open ); - - TEST_LINE <= nx1_debug_line_o; - NX1_DEBUG_LINE <= nx1_debug_line_o; - - FPGA5_COMM(10) <= fee1_trigger; - + + nx1_regio_addr_in(15 downto 12) <= (others => '0'); + + TEST_LINE(0) <= clk_100_i; + TEST_LINE(1) <= nx1_regio_read_enable_in; + TEST_LINE(2) <= nx1_regio_write_enable_in; + TEST_LINE(3) <= nx1_regio_dataready_out; + TEST_LINE(4) <= nx1_regio_write_ack_out; + TEST_LINE(5) <= nx1_regio_unknown_addr_out; + TEST_LINE(15 downto 6) <= (others => '0'); --------------------------------------------------------------------------- -- SED Detection --------------------------------------------------------------------------- - THE_SED : entity work.sedcheck port map( - CLK => clk_100_i, - ERROR_OUT => sed_error, - - DATA_IN => sed_din, - DATA_OUT => sed_dout, - WRITE_IN => sed_write, - READ_IN => sed_read, - ACK_OUT => sed_ack, - NACK_OUT => sed_nack, - ADDR_IN => sed_addr + CLK => clk_100_i, + ERROR_OUT => sed_error, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx ); ----------------------------------------------------------------------------- -- nXyter Main and ADC Clocks ----------------------------------------------------------------------------- - -- nXyter Main Clock (250MHz) - pll_nx_clk250_1: entity work.pll_nx_clk250 + -- Scaler Domain Clock(400MHz) + pll_clk400_1: entity work.pll_clk400 port map ( CLK => CLK_PCLK_RIGHT, RESET => nx_pll_reset, @@ -758,15 +700,4 @@ begin LOCK => nx_pll_clk_lock ); - -- Port FF for Nxyter Main Clocks - THE_NX_MAIN_ODDR_1: ODDRXD1 - port map( - SCLK => nx_main_clk, - DA => '1', - DB => '0', - Q => NX1_MAIN_CLK_OUT - ); - - NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk; - end architecture; diff --git a/scaler/trb3_periph_scaler_constraints.lpf b/scaler/trb3_periph_scaler_constraints.lpf index dfd77fa..0b80b70 100644 --- a/scaler/trb3_periph_scaler_constraints.lpf +++ b/scaler/trb3_periph_scaler_constraints.lpf @@ -14,32 +14,19 @@ BLOCK RD_DURING_WR_PATHS ; # CLK_PCLK_RIGHT : real Oszillator 200MHz # CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities # -# CLK_PCLK_RIGHT --> nx_main_clk 1+2 -# (250 MHz) -----> nXyter Main Clock 1+2 -# | -# |----> FPGA Timestamp Entity 1+2 -# -# nx_main_clk 1+2 --> nXyter Data Clk -# (1/2 = 125MHz) -----> FPGA Data Receiver -# | -# |----> Johnson 1/4 --> ADC SCLK -# -# ADC_DATA_CLK --> ADC Data Clk -----> FPGA ADC Handler -# DDR (187.5 MHz) +# CLK_PCLK_RIGHT --> clk_scaler +# (400 MHz) -----> Scaler Smapling Clock +# # Speed for the configuration Flash access SYSCONFIG MCCLK_FREQ = 20; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz; -FREQUENCY PORT NX1_ADC_DCLK_IN 187.5 MHz; -FREQUENCY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK_c" 93.750000 MHz; USE PRIMARY NET "CLK_PCLK_RIGHT_c"; -USE PRIMARY NET "clk_100_i_c"; -USE PRIMARY NET "nx_main_clk_c"; -USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK_c"; +USE PRIMARY NET "clk_100_i"; +USE PRIMARY NET "nx_main_clk"; ################################################################# # Reset Nets @@ -72,61 +59,61 @@ LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reset_nx_main_clk_in_ff*" 30 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*" 30 ns; -MULTICYCLE to CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/calibration_trigger_o*" 50 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/timestamp_calib_trigger_c*" 20 ns; - -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/internal_trigger_o*" 100 ns; - -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/reset_nx_main_clk_in_ff*" 30 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_reset_ff*" 10 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns; - -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*" 30 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*" 30 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cnx_ff*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_dt_error_ctr_r*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/timestamp_dt_error_ctr_*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_r*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns; - -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns; - -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns; - - -MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 500 ns; - - -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns; - -MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ; -MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; -MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ; -MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reset_nx_main_clk_in_ff*" 30 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*" 30 ns; +# MULTICYCLE to CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*" 30 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/calibration_trigger_o*" 50 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/timestamp_calib_trigger_c*" 20 ns; +# +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/internal_trigger_o*" 100 ns; +# +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/reset_nx_main_clk_in_ff*" 30 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_reset_ff*" 10 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns; +# +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*" 30 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*" 30 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cnx_ff*" 30 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*" 100 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_dt_error_ctr_r*" 100 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/timestamp_dt_error_ctr_*" 100 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_r*" 100 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns; +# +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns; +# +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns; +# +# +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 500 ns; +# +# +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns; +# MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns; +# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns; +# +# MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ; +# MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; +# MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ; +# MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; ################################################################# # Constraints for nxyter inputs @@ -134,9 +121,3 @@ MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; # look at .par and .twr.setup file for clocks # IN .mrp you find the semantic errors - -PROHIBIT PRIMARY NET "NX1_DATA_CLK_IN_c"; -PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c"; - -DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN";