From: Peter Lemmens Date: Wed, 16 Apr 2014 10:14:18 +0000 (+0200) Subject: removing files from version control X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=79ceea4ca5e030136fd26b88e230d8f950b2b335;p=soda.git removing files from version control --- diff --git a/.gitignore b/.gitignore index 7dcfa30..4893bbb 100644 --- a/.gitignore +++ b/.gitignore @@ -14,3 +14,14 @@ version.vhd *.kate-swp *.html *.xml +source/serdes_4_sync_downstream.ipx +source/serdes_4_sync_downstream.lpc +source/serdes_sync_client_upstream.ipx +source/serdes_sync_upstream.ipx +source/serdes_sync_upstream.lpc +source/serdes_sync_upstream.txt +source/soda_client_synconstraints.fdc +source/soda_hub_synconstraints.fdc +source/soda_source_clock_constraints.sdc +source/soda_source_syn_translated.fdc +source/soda_source_synconstraints.fdc diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index cfc43b1..b415a3b 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -18,7 +18,7 @@ entity med_ecp3_sfp_sync_down is SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset - -- + -- -- PCSA_REFCLKP : in std_logic; -- external refclock straight into serdes PL! -- PCSA_REFCLKN : in std_logic; -- external refclock straight into serdes PL! --Internal Connection TX @@ -40,8 +40,8 @@ entity med_ecp3_sfp_sync_down is RX_DLM : out std_logic := '0'; RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; TX_DLM : in std_logic := '0'; - TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; - TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! + TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; + TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL! LINK_PHASE_OUT : out std_logic := '0'; --PL! --SFP Connection @@ -80,7 +80,7 @@ architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is attribute syn_sharing : string; attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off"; - + component DCS -- synthesis translate_off @@ -101,7 +101,7 @@ end component; --signal refclk_p_in_S : std_logic; --PL! --signal refclk_n_in_S : std_logic; --PL! ---signal refclk2core_S : std_logic; --PL! +--signal refclk2core_S : std_logic; --PL! signal clk_200_i : std_logic; signal clk_200_internal : std_logic; @@ -175,7 +175,7 @@ signal start_timer : unsigned(18 downto 0) := (others => '0'); begin -clk_200_internal <= CLK; +clk_200_internal <= CLK; CLK_RX_HALF_OUT <= clk_rx_half; CLK_RX_FULL_OUT <= clk_rx_full; @@ -187,7 +187,7 @@ CLK_TX_FULL_OUT <= clk_tx_full; SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready ---rst_n <= not CLEAR; PL! +--rst_n <= not CLEAR; PL! --rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger); --rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); -- or watchdog_trigger); rst_n <= not(CLEAR or internal_make_link_reset_out); @@ -206,9 +206,9 @@ end generate; ------------------------------------------------- -- Serdes ------------------------------------------------- -THE_SERDES : entity work.serdes_sync_downstream +THE_SERDES : entity work.serdes_sync_source_downstream port map( --- refclkp => PCSA_REFCLKP, -- external refclock straight into serdes PL! +-- refclkp => PCSA_REFCLKP, -- external refclock straight into serdes PL! -- refclkn => PCSA_REFCLKN, -- external refclock straight into serdes PL! hdinp_ch0 => SD_RXD_P_IN, hdinn_ch0 => SD_RXD_N_IN, @@ -240,7 +240,7 @@ THE_SERDES : entity work.serdes_sync_downstream lsm_status_ch0_s => lsm_status, rx_cdr_lol_ch0_s => rx_cdr_lol, tx_div2_mode_ch0_c => '0', - rx_div2_mode_ch0_c => '0', + rx_div2_mode_ch0_c => '0', refclk2fpga => open, --refclk2core_S, SCI_WRDATA => sci_data_in_i, @@ -368,14 +368,14 @@ THE_TX : soda_tx_control START_RETRANSMIT_IN => start_retr_i, --TODO START_POSITION_IN => request_retr_position_i, --TODO - + TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN, SEND_DLM => TX_DLM, SEND_DLM_WORD => TX_DLM_WORD, SEND_LINK_RESET_IN => CTRL_OP(15), TX_ALLOW_IN => tx_allow, - RX_ALLOW_IN => rx_allow, + RX_ALLOW_IN => rx_allow, LINK_PHASE_OUT => link_phase_S, --PL! DEBUG_OUT => debug_tx_control_i, @@ -553,4 +553,3 @@ STAT_OP(5) <= request_retr_i; STAT_OP(4) <= start_retr_i; STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; end med_ecp3_sfp_sync_down_arch; - diff --git a/soda_client.ldf b/soda_client.ldf index 68940a9..da04f89 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -5,49 +5,49 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -311,7 +311,7 @@ - + @@ -320,7 +320,7 @@ - + diff --git a/soda_source.ldf b/soda_source.ldf index fbb4eb8..c94c37a 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -26,9 +26,6 @@ - - - @@ -311,13 +308,16 @@ - + - + - + + + + diff --git a/soda_source/soda_source_syn.prj b/soda_source/soda_source_syn.prj index 19fbdfe..cc7ca04 100644 --- a/soda_source/soda_source_syn.prj +++ b/soda_source/soda_source_syn.prj @@ -1,25 +1,23 @@ #-- Synopsys, Inc. #-- Version I-2013.09L #-- Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj -#-- Written on Wed Apr 9 12:12:25 2014 +#-- Written on Tue Apr 15 15:02:27 2014 #project files -add_file -fpga_constraint "/local/lemmens/lattice/soda/source/soda_source_synconstraints.fdc" +add_file -fpga_constraint "/local/lemmens/lattice/soda/code/soda_source_synconstraints.fdc" add_file -vhdl -lib work "/usr/local/diamond/3.1_x64/cae_library/synthesis/vhdl/ecp3.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/version.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_components.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_source.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_d8crc8.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_packet_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_reply_pkt_builder.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_superburst_gen.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/med_ecp3_sfp_sync_up.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/serdes_sync_downstream.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_SOB_faker.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_calibration_timer.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_reply_handler.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/soda_tx_control.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/version.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_components.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_source.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_d8crc8.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_packet_handler.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_superburst_gen.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/med_ecp3_sfp_sync_down.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_SOB_faker.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_calibration_timer.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_reply_handler.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_tx_control.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/cores/pll_in200_out100.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/trb3_components.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_components.vhd" @@ -107,7 +105,10 @@ add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_f add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd" -add_file -vhdl -lib work "/local/lemmens/lattice/soda/source/trb3_periph_sodasource.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/trb3_periph_sodasource.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_packet_builder.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/posedge_to_pulse.vhd" +add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/serdes_sync_source_downstream.vhd" diff --git a/source/serdes_4_sync_downstream.ipx b/source/serdes_4_sync_downstream.ipx deleted file mode 100644 index 752b576..0000000 --- a/source/serdes_4_sync_downstream.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/source/serdes_4_sync_downstream.lpc b/source/serdes_4_sync_downstream.lpc deleted file mode 100644 index 7c4a1e5..0000000 --- a/source/serdes_4_sync_downstream.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_4_sync_downstream -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=02/25/2014 -Time=13:41:30 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=RXTX -_mode1=RXTX -_mode2=RXTX -_mode3=RXTX -_protocol0=G8B10B -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=G8B10B -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=2 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=200 -_tx_protocol0=G8B10B -_tx_protocol1=G8B10B -_tx_protocol2=G8B10B -_tx_protocol3=G8B10B -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=DISABLED -_tx_fifo1=DISABLED -_tx_fifo2=DISABLED -_tx_fifo3=DISABLED -_tx_ficlk_rate0=200 -_tx_ficlk_rate1=200 -_tx_ficlk_rate2=200 -_tx_ficlk_rate3=200 -_pll_rxsrc0=INTERNAL -_pll_rxsrc1=INTERNAL -_pll_rxsrc2=INTERNAL -_pll_rxsrc3=INTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=2 -_rx_datarange1=2 -_rx_datarange2=2 -_rx_datarange3=2 -_rx_protocol0=G8B10B -_rx_protocol1=G8B10B -_rx_protocol2=G8B10B -_rx_protocol3=G8B10B -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=200 -_rxrefclk_rate1=200 -_rxrefclk_rate2=200 -_rxrefclk_rate3=200 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=DISABLED -_rx_fifo1=DISABLED -_rx_fifo2=DISABLED -_rx_fifo3=DISABLED -_rx_ficlk_rate0=200 -_rx_ficlk_rate1=200 -_rx_ficlk_rate2=200 -_rx_ficlk_rate3=200 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=DC -_rx_dcc1=DC -_rx_dcc2=DC -_rx_dcc3=DC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=DC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P157 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P157 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111100 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111100 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=1 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=1 -_k00=01 -_k01=01 -_k02=01 -_k03=01 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=01 -_k31=01 -_k32=01 -_k33=01 -_byten00=00011100 -_byten01=00011100 -_byten02=00011100 -_byten03=00011100 -_byten10=00000000 -_byten11=00000000 -_byten12=00000000 -_byten13=00000000 -_byten20=00011100 -_byten21=00011100 -_byten22=00011100 -_byten23=00011100 -_byten30=00011100 -_byten31=00011100 -_byten32=00011100 -_byten33=00011100 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=ENABLED -_sci_int_port=DISABLED -_refck2core=ENABLED -Regen=module -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_4_sync_downstream.pp=pp -serdes_4_sync_downstream.tft=tft -serdes_4_sync_downstream.txt=pcs_module -serdes_4_sync_downstream.sym=sym diff --git a/source/serdes_sync_client_upstream.ipx b/source/serdes_sync_client_upstream.ipx deleted file mode 100644 index c1cdc76..0000000 --- a/source/serdes_sync_client_upstream.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/source/serdes_sync_upstream.ipx b/source/serdes_sync_upstream.ipx deleted file mode 100644 index 1485eb0..0000000 --- a/source/serdes_sync_upstream.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/source/serdes_sync_upstream.lpc b/source/serdes_sync_upstream.lpc deleted file mode 100644 index 15a05bb..0000000 --- a/source/serdes_sync_upstream.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_sync_upstream -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=02/25/2014 -Time=13:39:52 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=DISABLED -_mode1=DISABLED -_mode2=DISABLED -_mode3=RXTX -_protocol0=G8B10B -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=G8B10B -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=2.0 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=200.0 -_tx_protocol0=DISABLED -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=G8B10B -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=ENABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED -_tx_ficlk_rate0=200.0 -_tx_ficlk_rate1=200.0 -_tx_ficlk_rate2=200.0 -_tx_ficlk_rate3=200.0 -_pll_rxsrc0=INTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=INTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=2.0 -_rx_datarange1=2.5 -_rx_datarange2=2.5 -_rx_datarange3=2 -_rx_protocol0=DISABLED -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=G8B10B -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=200.0 -_rxrefclk_rate1=250.0 -_rxrefclk_rate2=250.0 -_rxrefclk_rate3=200 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=DISABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=DISABLED -_rx_ficlk_rate0=200.0 -_rx_ficlk_rate1=250.0 -_rx_ficlk_rate2=250.0 -_rx_ficlk_rate3=200 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=AC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=DC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P157 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P157 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111100 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111100 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=1 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=1 -_k00=01 -_k01=00 -_k02=01 -_k03=01 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=01 -_k31=01 -_k32=01 -_k33=01 -_byten00=00011100 -_byten01=00000000 -_byten02=00011100 -_byten03=00011100 -_byten10=00000000 -_byten11=00000000 -_byten12=00000000 -_byten13=00000000 -_byten20=00011100 -_byten21=00011100 -_byten22=00011100 -_byten23=00011100 -_byten30=00011100 -_byten31=00011100 -_byten32=00011100 -_byten33=00011100 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=ENABLED -_sci_int_port=ENABLED -_refck2core=DISABLED -Regen=module -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_sync_upstream.pp=pp -serdes_sync_upstream.tft=tft -serdes_sync_upstream.txt=pcs_module -serdes_sync_upstream.sym=sym diff --git a/source/serdes_sync_upstream.txt b/source/serdes_sync_upstream.txt deleted file mode 100644 index 062baf6..0000000 --- a/source/serdes_sync_upstream.txt +++ /dev/null @@ -1,58 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH3_PROTOCOL "G8B10B" -CH0_MODE "DISABLED" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "RXTX" -CH3_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MEDHIGH" -CH3_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "10X" -#REFCLK_RATE 200.0 -CH3_RX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" -CH3_TX_DATA_WIDTH "8" -CH3_RX_DATA_WIDTH "8" -CH3_TX_FIFO "ENABLED" -CH3_RX_FIFO "DISABLED" -CH3_TDRV "0" -#CH3_TX_FICLK_RATE 200.0 -#CH3_RXREFCLK_RATE "200" -#CH3_RX_FICLK_RATE 200 -CH3_TX_PRE "DISABLED" -CH3_RTERM_TX "50" -CH3_RX_EQ "DISABLED" -CH3_RTERM_RX "50" -CH3_RX_DCC "DC" -CH3_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH3_TX_SB "DISABLED" -CH3_RX_SB "DISABLED" -CH3_TX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" -CH3_COMMA_A "1100000101" -CH3_COMMA_B "0011111010" -CH3_COMMA_M "1111111100" -CH3_RXWA "ENABLED" -CH3_ILSM "ENABLED" -CH3_CTC "DISABLED" -CH3_CC_MATCH4 "0100011100" -CH3_CC_MATCH_MODE "1" -CH3_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH3_SSLB "DISABLED" -CH3_SPLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" -INT_ALL "ENABLED" -QD_REFCK2CORE "DISABLED" - - diff --git a/source/soda_client_synconstraints.fdc b/source/soda_client_synconstraints.fdc deleted file mode 100644 index e9ff28d..0000000 --- a/source/soda_client_synconstraints.fdc +++ /dev/null @@ -1,66 +0,0 @@ -################################################################################ -#### This file contains constraints from Synplicity SDC files that have been -#### translated into Synopsys FPGA Design Constraints (FDC). -#### Translated FDC output file: -#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc -#### client SDC files to the translation: -#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc -################################################################################ - - -###==== BEGIN Header - -# Synopsys, Inc. constraint file -# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc -# Written on Wed Dec 18 11:52:15 2013 -# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor - -# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. -# These sections are generated from SCOPE spreadsheet tabs. - -###==== END Header - - -################################################################################ -#### The following Synplicity constraints from file: -#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc -#### are disabled and have not been translated. -############################################################################## -# FDC constraints translated from Synplify Legacy Timing & Design Constraints -############################################################################## - -set_rtl_ff_names {} -###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) -define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable -define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable -define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable -define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable -###==== END Collections -###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0} -create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -create_clock -name {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5} - - -#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} -period {10.0} -waveform {0 5.0} -#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} } -set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} } -#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} } -#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} } -###==== END Clocks -###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) -###==== END "Generated Clocks" -###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) -###==== END Inputs/Outputs -###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) -###==== END "Delay Paths" -###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) -###==== END Attributes -###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) -###==== END "I/O Standards" -###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) -###==== END "Compile Points" - diff --git a/source/soda_hub_synconstraints.fdc b/source/soda_hub_synconstraints.fdc deleted file mode 100644 index 694b82b..0000000 --- a/source/soda_hub_synconstraints.fdc +++ /dev/null @@ -1,64 +0,0 @@ -################################################################################ -#### This file contains constraints from Synplicity SDC files that have been -#### translated into Synopsys FPGA Design Constraints (FDC). -#### Translated FDC output file: -#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc -#### client SDC files to the translation: -#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc -################################################################################ - - -###==== BEGIN Header - -# Synopsys, Inc. constraint file -# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc -# Written on Wed Dec 18 11:52:15 2013 -# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor - -# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. -# These sections are generated from SCOPE spreadsheet tabs. - -###==== END Header - - -################################################################################ -#### The following Synplicity constraints from file: -#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc -#### are disabled and have not been translated. -############################################################################## -# FDC constraints translated from Synplify Legacy Timing & Design Constraints -############################################################################## - -set_rtl_ff_names {} -###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) -define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable -define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable -define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable -define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable -###==== END Collections -###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} {n:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0} -create_clock -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -create_clock -name {n:trb3_periph_sodahub_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodahub_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5} - - -set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_full_clk_ch0} } -set_clock_groups -derive -asynchronous -name {THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_HUB_SYNC_UPLINK.THE_SERDES.rx_half_clk_ch0} } -#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} } -#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} } -###==== END Clocks -###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) -###==== END "Generated Clocks" -###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) -###==== END Inputs/Outputs -###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) -###==== END "Delay Paths" -###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) -###==== END Attributes -###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) -###==== END "I/O Standards" -###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) -###==== END "Compile Points" - diff --git a/source/soda_source_clock_constraints.sdc b/source/soda_source_clock_constraints.sdc deleted file mode 100644 index b224237..0000000 --- a/source/soda_source_clock_constraints.sdc +++ /dev/null @@ -1,11 +0,0 @@ -#define_clock {p:CLK_PCLK_LEFT} -freq 200 - -#define_clock {n:gen_200_PLL.THE_MAIN_PLL.CLKOP} -name {n:gen_200_PLL.THE_MAIN_PLL.CLKOP} -freq 100 -#define_clock {n:gen_200_PLL.THE_MAIN_PLL.CLKOK} -name {n:gen_200_PLL.THE_MAIN_PLL.CLKOK} -freq 200 - -# Just to stop the nagging: -define_clock {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -name {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -freq 100 -define_clock {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -name {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -freq 200 - -#define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200.THE_SERDES.rx_half_clk_ch1} -freq 100 -#define_clock {n:clk_raw_internal} -name {nn:clk_raw_internal} -freq 200 diff --git a/source/soda_source_syn_translated.fdc b/source/soda_source_syn_translated.fdc deleted file mode 100644 index e9ff28d..0000000 --- a/source/soda_source_syn_translated.fdc +++ /dev/null @@ -1,66 +0,0 @@ -################################################################################ -#### This file contains constraints from Synplicity SDC files that have been -#### translated into Synopsys FPGA Design Constraints (FDC). -#### Translated FDC output file: -#### /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc -#### client SDC files to the translation: -#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc -################################################################################ - - -###==== BEGIN Header - -# Synopsys, Inc. constraint file -# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc -# Written on Wed Dec 18 11:52:15 2013 -# by Synplify Pro, G-2012.09L-SP1 FDC Constraint Editor - -# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. -# These sections are generated from SCOPE spreadsheet tabs. - -###==== END Header - - -################################################################################ -#### The following Synplicity constraints from file: -#### /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc -#### are disabled and have not been translated. -############################################################################## -# FDC constraints translated from Synplify Legacy Timing & Design Constraints -############################################################################## - -set_rtl_ff_names {} -###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) -define_scope_collection {all_inputs_fdc} {find -port * -filter @direction==input} -disable -define_scope_collection {all_outputs_fdc} {find -port * -filter @direction==output} -disable -define_scope_collection {all_clocks_fdc} {find -hier -clock *} -disable -define_scope_collection {all_registers_fdc} {find -hier -seq *} -disable -###==== END Collections -###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0} -create_clock -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -create_clock -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -create_clock -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -create_clock -name {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5} - - -#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} -period {10.0} -waveform {0 5.0} -#create_clock -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} } -set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} } -#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} } -#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} } -###==== END Clocks -###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) -###==== END "Generated Clocks" -###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) -###==== END Inputs/Outputs -###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) -###==== END "Delay Paths" -###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) -###==== END Attributes -###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) -###==== END "I/O Standards" -###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) -###==== END "Compile Points" - diff --git a/source/soda_source_synconstraints.fdc b/source/soda_source_synconstraints.fdc deleted file mode 100644 index d1ccd96..0000000 --- a/source/soda_source_synconstraints.fdc +++ /dev/null @@ -1,48 +0,0 @@ - -###==== BEGIN Header - -# Synopsys, Inc. constraint file -# /local/lemmens/lattice/soda/soda_source/soda_source_synconstraints.fdc -# Written on Tue Dec 3 18:26:37 2013 -# by Synplify Pro, G-2012.09L-1 FDC Constraint Editor - -# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. -# These sections are generated from SCOPE spreadsheet tabs. - -###==== END Header - -###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) -###==== END Collections - -###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock -name {rx_clk_half} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10} -create_clock -name {rx_clk_full} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5} - -#create_clock -name {clk_sys_internal} {n:gen_200_PLL\.THE_MAIN_PLL.CLKOP} -period {10} -#create_clock -name {serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} -period {10} -#create_clock -name {serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} -period {5} -#set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_0} -group { {c:serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} } -#set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_1} -group { {c:serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} } -#set_clock_groups -derive -asynchronous -name {raw_internal} -group { {c:clk_raw_internal} } -#set_clock_groups -derive -asynchronous -name {sys_internal} -group { {c:clk_sys_internal} } -###==== END Clocks - -###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) -###==== END "Generated Clocks" - -###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) -###==== END Inputs/Outputs - -###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) -###==== END "Delay Paths" - -###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) -###==== END Attributes - -###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) -###==== END "I/O Standards" - -###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) -###==== END "Compile Points" - - diff --git a/trb3_soda_source.xcf b/trb3_soda_source.xcf index a0368f7..de8ad9f 100644 --- a/trb3_soda_source.xcf +++ b/trb3_soda_source.xcf @@ -47,8 +47,8 @@ 1 0 - /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140414.bit - 04/14/14 11:17:17 + /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140415.bit + 04/15/14 15:30:13 Fast Program