From: Thomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Date: Wed, 30 Sep 2020 13:21:31 +0000 (+0200)
Subject: rx_control: Use system clock for sampling rx_allow
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7a173d2477badc3d15fd5c3ac817217f97b84b0e;p=trbnet.git

rx_control: Use system clock for sampling rx_allow

rx_allow is synchronous to the system clock. ct_fifo_reset is
asynchronous and can therefore be produced with the system clock to
avoid timing errors.
---

diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd
index 88c91fb..8e8085b 100644
--- a/media_interfaces/sync/rx_control.vhd
+++ b/media_interfaces/sync/rx_control.vhd
@@ -128,7 +128,7 @@ THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg
     AlmostFull        => ct_fifo_afull
     );
 
-ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200);    
+ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_100);    
 
 
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