From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Thu, 26 Feb 2015 07:42:39 +0000 (+0100)
Subject: Enable outreg again
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7ab1b0df3cbc3f6cfe13b7a4f3b800f6e21f47e2;p=trb3.git

Enable outreg again
---

diff --git a/ADC/cores/dpram_32x512.ipx b/ADC/cores/dpram_32x512.ipx
index 0050b6f..0e1c1be 100644
--- a/ADC/cores/dpram_32x512.ipx
+++ b/ADC/cores/dpram_32x512.ipx
@@ -1,10 +1,10 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="dpram_32x512" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 20 17:02:38.118" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="dpram_32x512" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 26 08:42:01.001" version="6.1" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-		<File name="" type="mem" modified="2015 02 20 17:02:37.000"/>
-		<File name="dpram_32x512.lpc" type="lpc" modified="2015 02 20 17:02:35.000"/>
-		<File name="dpram_32x512.vhd" type="top_level_vhdl" modified="2015 02 20 17:02:36.000"/>
-		<File name="dpram_32x512_tmpl.vhd" type="template_vhdl" modified="2015 02 20 17:02:36.000"/>
-		<File name="tb_dpram_32x512_tmpl.vhd" type="testbench_vhdl" modified="2015 02 20 17:02:36.000"/>
+		<File name="" type="mem" modified="2015 02 26 08:42:00.000"/>
+		<File name="dpram_32x512.lpc" type="lpc" modified="2015 02 26 08:41:58.000"/>
+		<File name="dpram_32x512.vhd" type="top_level_vhdl" modified="2015 02 26 08:41:58.000"/>
+		<File name="dpram_32x512_tmpl.vhd" type="template_vhdl" modified="2015 02 26 08:41:58.000"/>
+		<File name="tb_dpram_32x512_tmpl.vhd" type="testbench_vhdl" modified="2015 02 26 08:41:58.000"/>
   </Package>
 </DiamondModule>
diff --git a/ADC/cores/dpram_32x512.lpc b/ADC/cores/dpram_32x512.lpc
index 3289d98..a3cfa4f 100644
--- a/ADC/cores/dpram_32x512.lpc
+++ b/ADC/cores/dpram_32x512.lpc
@@ -16,8 +16,8 @@ CoreRevision=6.1
 ModuleName=dpram_32x512
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=02/20/2015
-Time=17:02:35
+Date=02/26/2015
+Time=08:41:58
 
 [Parameters]
 Verilog=0
@@ -35,7 +35,7 @@ enByte=0
 ByteSize=9
 adPipeline=0
 inPipeline=0
-outPipeline=0
+outPipeline=1
 MOR=0
 InData=Registered
 AdControl=Registered
diff --git a/ADC/cores/dpram_32x512.vhd b/ADC/cores/dpram_32x512.vhd
index b6c3a5b..2738e01 100644
--- a/ADC/cores/dpram_32x512.vhd
+++ b/ADC/cores/dpram_32x512.vhd
@@ -1,8 +1,8 @@
 -- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
 -- Module  Version: 6.1
---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 512 -cascade -1 -e 
+--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 512 -outdata REGISTERED -cascade -1 -e 
 
--- Fri Feb 20 17:02:36 2015
+-- Thu Feb 26 08:41:58 2015
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -113,7 +113,7 @@ begin
 
     dpram_32x512_0_0_0: PDPW16KC
         generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
-        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        REGMODE=> "OUTREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
         port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
             DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
             DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),