From: hadeshyp Date: Mon, 11 Dec 2006 17:03:58 +0000 (+0000) Subject: auto-answering for the API, Ingo X-Git-Tag: oldGBE~774 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7aca6e802602074f74ebd23687ff00c8782baec8;p=trbnet.git auto-answering for the API, Ingo --- diff --git a/testbench/in_active_api.txt b/testbench/in_active_api.txt index 5fb14a5..6288035 100644 --- a/testbench/in_active_api.txt +++ b/testbench/in_active_api.txt @@ -1,6 +1,6 @@ 0:0:0000 0:0:0000 -0:0:0000 +1:0:0011 -- prefill 0:0:0000 0:1:0000 -- start sending here 0:1:0000 diff --git a/testbench/in_active_api_tb.txt b/testbench/in_active_api_tb.txt new file mode 100644 index 0000000..e0f9ed3 --- /dev/null +++ b/testbench/in_active_api_tb.txt @@ -0,0 +1,14 @@ +0:000:0000:0000 +0:000:0000:0000 +0:000:0000:0000 +0:000:0000:0000 +1:001:0011:0001 --hdr +1:000:0011:0010 --dat +1:000:0011:0011 --dat +1:000:0011:0100 --dat +1:001:0000:0001 --hdr +1:000:0000:0001 --dat +1:000:0000:0010 --dat +1:000:0000:0011 --dat +1:010:0000:0000 --trm +0:000:0000:0000 \ No newline at end of file diff --git a/testbench/trb_net_active_api_testbench.vhd b/testbench/trb_net_active_api_testbench.vhd index a7c3b3d..5363e66 100644 --- a/testbench/trb_net_active_api_testbench.vhd +++ b/testbench/trb_net_active_api_testbench.vhd @@ -24,7 +24,16 @@ architecture trb_net_active_api_testbench_arch of trb_net_active_api_testbench i signal int_init_data_out : std_logic_vector(50 downto 0) := (others => '0'); signal int_init_dataready_out : std_logic := '0'; - + signal int_init_dataready_in : std_logic := '0'; + signal int_init_data_in : std_logic_vector(50 downto 0) := (others => '0'); + signal read_type : std_logic_vector(2 downto 0) := (others => '0'); + signal read_xf2 : std_logic_vector(3 downto 0) := (others => '0'); + signal read_xf1 : std_logic_vector(3 downto 0) := (others => '0'); + + signal int_init_read_out : std_logic := '0'; + signal int_reply_data_out : std_logic_vector(50 downto 0) := (others => '0'); + signal int_reply_dataready_out: std_logic := '0'; + signal read_f1 : std_logic_vector(3 downto 0) := (others => '0'); component trb_net_active_api @@ -98,7 +107,7 @@ begin UUT: trb_net_active_api generic map ( - FIFO_TERM_BUFFER_DEPTH => 0) + FIFO_TERM_BUFFER_DEPTH => 3) port map ( CLK => clk, RESET => reset, @@ -117,15 +126,18 @@ UUT: trb_net_active_api INT_INIT_READ_IN => '1', --advanced read - INT_INIT_DATAREADY_IN => '0', INT_INIT_DATAREADY_OUT => int_init_dataready_out, - INT_INIT_DATA_IN => (others => '0'), + INT_INIT_DATA_IN => int_init_data_in, + INT_INIT_DATAREADY_IN => int_init_dataready_in, + INT_INIT_READ_OUT => int_init_read_out, INT_INIT_ERROR_IN => (others => '0'), INT_INIT_DATA_OUT => int_init_data_out, - - INT_REPLY_HEADER_IN => '0', - INT_REPLY_READ_IN => '0', + + INT_REPLY_DATA_OUT => int_reply_data_out, + INT_REPLY_DATAREADY_OUT => int_reply_dataready_out, INT_REPLY_DATAREADY_IN => '0', + INT_REPLY_HEADER_IN => '0', + INT_REPLY_READ_IN => '1', INT_REPLY_DATA_IN => (others => '0'), INT_REPLY_ERROR_IN => (others => '0') ); @@ -134,7 +146,10 @@ UUT: trb_net_active_api apl_data_in(3 downto 0) <= read_f1; - + int_init_data_in(50 downto 48) <= read_type; + int_init_data_in(19 downto 16) <= read_xf2;-- target + int_init_data_in(35 downto 32) <= read_xf1; -- source + DO_RESET : process @@ -172,7 +187,37 @@ UUT: trb_net_active_api end if; end process STIMULI; + TB_STIMULI: process (clk) + file protokoll : text open read_mode is "in_active_api_tb.txt"; + variable myoutline : line; + variable leer : character; + variable var1, var2 : std_logic; + variable varx1 : std_logic_vector(2 downto 0); + variable varx2, varx3 : std_logic_vector(3 downto 0); + begin + if falling_edge(CLK) then + if (not endfile(protokoll)) then + readline(protokoll,myoutline); + + read(myoutline,var1); + int_init_dataready_in <= var1; + read(myoutline,leer); + + read(myoutline,varx1); + read_type <= varx1; + read(myoutline,leer); + read(myoutline,varx2); + read_xf2 <= varx2; + read(myoutline,leer); + + read(myoutline,varx3); + read_xf1 <= varx3; + + + end if; + end if; + end process TB_STIMULI; end trb_net_active_api_testbench_arch; diff --git a/trb_net_active_api.vhd b/trb_net_active_api.vhd index e91b5e9..ef9e4b6 100644 --- a/trb_net_active_api.vhd +++ b/trb_net_active_api.vhd @@ -115,18 +115,21 @@ signal fifo_to_apl_full : std_logic; signal fifo_to_apl_empty : std_logic; -- signals for the test buffer -signal fifo_term_buffer_data_in : std_logic_vector(47 downto 0); +signal fifo_term_buffer_data_in : std_logic_vector(50 downto 0); signal fifo_term_buffer_write : std_logic; -signal fifo_term_buffer_data_out : std_logic_vector(47 downto 0); +signal fifo_term_buffer_data_out : std_logic_vector(50 downto 0); signal fifo_term_buffer_read : std_logic; signal fifo_term_buffer_full : std_logic; signal fifo_term_buffer_empty : std_logic; type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); +type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR); signal current_state, next_state : API_STATE; +signal tb_current_state, tb_next_state : TERM_BUFFER_STATE; signal combined_header, registered_header, next_registered_header: std_logic_vector(47 downto 0); signal combined_trailer, registered_trailer, next_registered_trailer: std_logic_vector(47 downto 0); +signal tb_registered_trailer, tb_next_registered_trailer: std_logic_vector(47 downto 0); signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0); signal next_INT_INIT_DATA_OUT, reg_INT_INIT_DATA_OUT: std_logic_vector(50 downto 0); @@ -170,7 +173,7 @@ CHECK_BUFFER: if FIFO_TERM_BUFFER_DEPTH >0 generate FIFO_TERM_BUFFER: trb_net_fifo generic map ( - WIDTH => 48, + WIDTH => 51, DEPTH => FIFO_TERM_BUFFER_DEPTH) port map ( CLK => CLK, @@ -183,23 +186,80 @@ CHECK_BUFFER: if FIFO_TERM_BUFFER_DEPTH >0 generate FULL_OUT => fifo_term_buffer_full, EMPTY_OUT => fifo_term_buffer_empty ); + +end generate CHECK_BUFFER; + + FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_INIT_DATA_IN, + INT_INIT_DATAREADY_IN, tb_next_registered_trailer, tb_registered_trailer, + fifo_term_buffer_empty, fifo_term_buffer_data_out, + INT_REPLY_READ_IN) + begin -- process + INT_INIT_READ_OUT <= '0'; + fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_ILLEGAL; + fifo_term_buffer_data_in(DWORD_POSITION) <= (others => '0'); + fifo_term_buffer_write <= '0'; + tb_next_state <= MY_ERROR; + tb_next_registered_trailer <= tb_registered_trailer; + fifo_term_buffer_read<= '0'; + INT_REPLY_DATAREADY_OUT <= '0'; + INT_REPLY_DATA_OUT(DWORD_POSITION) <= (others => '0'); + INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL; + if tb_current_state = IDLE then + INT_INIT_READ_OUT <= '1'; -- I always can read + tb_next_state <= IDLE; + if INT_INIT_DATA_IN(TYPE_POSITION) = TYPE_HDR and INT_INIT_DATAREADY_IN = '1' then + fifo_term_buffer_data_in(F1_POSITION) <= INT_INIT_DATA_IN(F2_POSITION); + fifo_term_buffer_data_in(F2_POSITION) <= INT_INIT_DATA_IN(F1_POSITION); + fifo_term_buffer_data_in(F3_POSITION) <= INT_INIT_DATA_IN(F3_POSITION); + fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_HDR; + fifo_term_buffer_write <= '1'; + -- switch source and target adress + elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_DAT and INT_INIT_DATAREADY_IN = '1' then + fifo_term_buffer_data_in <= INT_INIT_DATA_IN; + fifo_term_buffer_write <= '1'; + elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_TRM and INT_INIT_DATAREADY_IN = '1' then + tb_next_registered_trailer <= INT_INIT_DATA_IN(DWORD_POSITION); + --keep trailer for later use + tb_next_state <= RUNNING; + end if; + elsif tb_current_state = RUNNING then + tb_next_state <= RUNNING; + if fifo_term_buffer_empty = '0' then -- Have buffered stuff + INT_REPLY_DATAREADY_OUT <= '1'; + INT_REPLY_DATA_OUT <= fifo_term_buffer_data_out; + if (INT_REPLY_READ_IN = '1') then + fifo_term_buffer_read <= '1'; + end if; + else + tb_next_state <= SEND_TRAILER; + end if; -- Have buffered stuff + elsif tb_current_state = SEND_TRAILER then + INT_REPLY_DATAREADY_OUT <= '1'; + INT_REPLY_DATA_OUT(DWORD_POSITION) <= tb_registered_trailer; + INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; + if (INT_REPLY_READ_IN = '1') then + tb_next_state <= IDLE; + end if; + end if; -- tb_current_state switch + end process; + - end generate CHECK_BUFFER; + -- combinatorial part of state machine STATE_COMB : process(current_state, APL_SEND_IN, combined_header, INT_INIT_READ_IN, - APL_WRITE_IN, fifo_to_int_empty, next_registered_header, + APL_WRITE_IN, fifo_to_int_empty, next_registered_header, registered_header, reg_INT_INIT_DATA_OUT, reg_INT_INIT_DATA_OUT, fifo_to_int_data_out, combined_trailer, - next_registered_trailer) + next_registered_trailer, fifo_to_int_data_out) begin -- process next_state <= MY_ERROR; - next_registered_header <= next_registered_header; + next_registered_header <= registered_header; next_INT_INIT_DATAREADY_OUT <= '0'; next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL; next_INT_INIT_DATA_OUT(DWORD_POSITION) <= (others => '0'); - next_registered_trailer <= next_registered_trailer; - + next_registered_trailer <= registered_trailer; + fifo_to_int_read <= '0'; ------------------------------------------------------------------------------- -- IDLE ------------------------------------------------------------------------------- @@ -232,6 +292,7 @@ CHECK_BUFFER: if FIFO_TERM_BUFFER_DEPTH >0 generate next_INT_INIT_DATAREADY_OUT <= '1'; next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + fifo_to_int_read <= '1'; end if; -- fifo_to_int_empty else next_state <= SEND_HEADER; @@ -255,7 +316,13 @@ CHECK_BUFFER: if FIFO_TERM_BUFFER_DEPTH >0 generate end if; else -- APL_SEND_IN: still running next_state <= RUNNING; - -- BUGBUG data words have to be prepared + if fifo_to_int_empty = '0' then + -- data words have to be prepared + next_INT_INIT_DATAREADY_OUT <= '1'; + next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; + next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + fifo_to_int_read <= '1'; + end if; end if; ------------------------------------------------------------------------------- -- SEND_TRAILER @@ -285,9 +352,19 @@ CHECK_BUFFER: if FIFO_TERM_BUFFER_DEPTH >0 generate -- this is not very consequent, find a better solution the be independent -- with the range + -- connect Transmitter port + fifo_to_int_data_in <= APL_DATA_IN; + fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full) when (current_state = IDLE or + current_state = SEND_HEADER or + current_state = RUNNING) + else '0'; + INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT; -- registered output for -- internal port INT_INIT_DATAREADY_OUT <= reg_INT_INIT_DATAREADY_OUT; + + + -- generate the sequence counter -- combinatorial part @@ -308,22 +385,28 @@ CLK_REG: process(CLK) reg_INT_INIT_DATA_OUT <= (others => '0'); reg_INT_INIT_DATAREADY_OUT <= '0'; current_state <= IDLE; + tb_current_state <= IDLE; registered_header <= (others => '0'); registered_trailer <= (others => '0'); + tb_registered_trailer <= (others => '0'); elsif CLK_EN = '1' then sequence_counter <= next_sequence_counter; reg_INT_INIT_DATA_OUT <= next_INT_INIT_DATA_OUT; reg_INT_INIT_DATAREADY_OUT <= next_INT_INIT_DATAREADY_OUT; current_state <= next_state; + tb_current_state <= tb_next_state; registered_header <= next_registered_header; registered_trailer <= next_registered_trailer; + tb_registered_trailer <= tb_next_registered_trailer; else sequence_counter <= sequence_counter; reg_INT_INIT_DATA_OUT <= reg_INT_INIT_DATA_OUT; reg_INT_INIT_DATAREADY_OUT <= reg_INT_INIT_DATAREADY_OUT; current_state <= current_state; + tb_current_state <= tb_current_state; registered_header <= registered_header; registered_trailer <= registered_trailer; + tb_registered_trailer <= tb_registered_trailer; end if; end if; end process;