From: hadeshyp <hadeshyp>
Date: Fri, 14 Nov 2008 16:17:12 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~515
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7aeebb2122c23e61285c172bba1241ac592706ef;p=trbnet.git

*** empty log message ***
---

diff --git a/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd b/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd
index 2796ead..5278d22 100644
--- a/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd
+++ b/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd
@@ -36,6 +36,8 @@ architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_du
           Empty: out  std_logic; Full: out  std_logic);
   end component;
 
+  signal buf_empty_out, buf_full_out : std_logic;
+
 BEGIN
   FIFO_DP_BRAM : lattice_ecp2m_fifo_16bit_dualport
     port map (
@@ -47,12 +49,12 @@ BEGIN
       Reset => fifo_gsr_in,
       RPReset => '0',
       Q => read_data_out,
-      Empty => empty_out,
-      Full => full_out
+      Empty => buf_empty_out,
+      Full => buf_full_out
       );
 
-almost_empty_out <= empty_out;
-almost_full_out  <= full_out;
+almost_empty_out <= buf_empty_out;
+almost_full_out  <= buf_full_out;
 fifostatus_out <= (others => '0');
 valid_read_out <= '0';
 end architecture trb_net_fifo_16bit_bram_dualport_arch;