From: Cahit <c.ugur@gsi.de>
Date: Mon, 5 Aug 2013 10:58:04 +0000 (+0200)
Subject: contacts update
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7cb680ae09dbb35619fccdda5bbd723cc8f40856;p=trb3web.git

contacts update
---

diff --git a/publications.htm b/publications.htm
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index 0000000..24dd765
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+<h3>Publications & Presentations</h3>
+
+
+<table>
+  <tr>
+    <th> Publication </th>
+    <th> Description </th>
+  </tr>
+<tr> <td><a href="schematics/trb3.pdf">TRB3</a> <td>The main TRB3 board. 
+<tr> <td><a href="schematics/clockdistribution.png">TRB3 clock distribution</a> <td>The distribution of clock and trigger signals on the TRB3
+<tr> <td><a href="schematics/4conn.pdf">4conn AddOn</a> <td>AddOn with four 40-pin connectors, compatible to connector on Padiwa front-end module
+<tr> <td><a href="schematics/ada1.pdf">ADA AddOn</a> <td>AddOn with two 80-pin connectors, compatible to input on TRB2
+<tr> <td><a href="schematics/gpin.pdf">GPin AddOn</a> <td>AddOn with 16 ECL and 8 NIM inputs
+<tr> <td><a href="schematics/multitest.pdf">MultiTest AddOn</a> <td>AddOn with several test ciruits
+<tr> <td><a href="schematics/sfp.pdf">SFP AddOn</a> <td>AddOn with 6 SFP cages. For use as TrbNet hub
+<tr> <td><a href="schematics/cts.pdf">CTS AddOn</a> <td>AddOn for the central FPGA with additional I/O for CTS
+</table>