From: Ingo Froehlich <ingo@nomail.fake>
Date: Tue, 30 Jan 2018 11:21:17 +0000 (+0100)
Subject: bug fix in flash master, IF
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7cce5c30bb4a6bbb35730b539181a81bbf69282b;p=vhdlbasics.git

bug fix in flash master, IF
---

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index 29b490d..b864057 100644
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -344,7 +344,7 @@ PROC_SELECTOR : process begin
       reg_LOC_READ_OUT  <= '0';
       reg_SPI_READY_OUT <= '1';
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');
-      reg_SPI_DATA_OUT(15 downto 0) <= x"00" & "00" & master_running & master_start_reg & '0' & flash_busy & flash_err & enable_cfg_flash;
+      reg_SPI_DATA_OUT(15 downto 0) <= x"00" & "0" & auto_reset & master_running & master_start_reg & '0' & flash_busy & flash_err & enable_cfg_flash;
     elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then
       reg_LOC_READ_OUT  <= '0';
       reg_SPI_READY_OUT <= '1';
@@ -373,10 +373,14 @@ flash_go <= master_flash_go when master_running = '1' else spi_flash_go;
 flash_page <= master_flash_page when master_running = '1' else spi_flash_page;
 flash_command <= master_flash_command when master_running = '1' else spi_flash_command;
 
-state_machine :  process (clk_f)
+state_machine :  process (clk_l)
 begin
-  if rising_edge(clk_f) then
-    master_flash_go  <= '0';
+  if rising_edge(clk_l) then
+
+    if (master_flash_go = '1' and flash_busy = '1') then
+      master_flash_go  <= '0';
+    end if;
+      
     master_WRITE_OUT <= '0';
     clean_master_start_reg <= '0';
 
@@ -411,7 +415,7 @@ begin
         state <= EnableFLASH3;
       when EnableFLASH3 =>
         state <= EnableFLASH3;
-        if (flash_busy = '0') then
+        if (flash_busy = '0' and master_flash_go = '0') then
            state <= Start;
            master_flash_command <= "000";
         end if;                    
@@ -426,7 +430,7 @@ begin
         state <= WaitFlash2;
       when WaitFlash2 =>
         state <= WaitFlash2;
-        if (flash_busy = '0') then
+        if (flash_busy = '0' and master_flash_go = '0') then
           state <= ReadRAM;
         end if;
       when ReadRAM =>
@@ -500,9 +504,9 @@ begin
         master_flash_go <= '1';
       when DisableFLASH2 =>
         state <= DisableFLASH3;
-        master_flash_go <= '0';
+        --master_flash_go <= '0';
       when DisableFLASH3 =>
-        if (flash_busy = '0') then
+        if (flash_busy = '0' and master_flash_go = '0') then
            state <= IDLE;
            master_flash_command <= "000";
         end if;