From: hadaq Date: Mon, 14 Nov 2011 16:38:58 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7e0a62959e724a52cf38434c8ea36f5142d89b67;p=trb3.git *** empty log message *** --- diff --git a/tdc_test/compile_periph_synonly_hades27.pl b/tdc_test/compile_periph_synonly_hades27.pl new file mode 100755 index 0000000..fe2573d --- /dev/null +++ b/tdc_test/compile_periph_synonly_hades27.pl @@ -0,0 +1,155 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph"; #Name of top-level entity +my $BasePath = "../base/"; #path to "base" directory +my $lattice_path = '/opt/lattice/diamond/1.3'; +my $synplify_path = '/opt/synplicity/fpga_e201103'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; +################################################################################### + + + + + + + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +#create full lpf file +system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; + +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + + + +foreach (@a) +{ + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } +} + + +#$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +#$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +#execute($c); + +#my $tpmap = $TOPNAME . "_map" ; + +#$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +#execute($c); + + +#system("rm $TOPNAME.ncd"); + +#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +#execute($c); + +## IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +## TWR Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/tdc_test/trb3_periph.prj b/tdc_test/trb3_periph.prj index c44cce6..0e43cc1 100644 --- a/tdc_test/trb3_periph.prj +++ b/tdc_test/trb3_periph.prj @@ -138,18 +138,13 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "./trb3_periph.vhd" -add_file -vhdl -lib "work" "source/TDC.vhd" add_file -vhdl -lib "work" "source/Adder_320.vhd" +add_file -vhdl -lib "work" "source/bit_sync.vhd" add_file -vhdl -lib "work" "source/Channel_320.vhd" add_file -vhdl -lib "work" "source/Encoder_320_Bit.vhd" -add_file -vhdl -lib "work" "source/FIFO_32x512_NOreg.vhd" +add_file -vhdl -lib "work" "source/FIFO_32x512_OutReg.vhd" +add_file -vhdl -lib "work" "source/Reference_channel.vhd" +add_file -vhdl -lib "work" "source/reset_generator.vhd" add_file -vhdl -lib "work" "source/ROM_FIFO.vhd" -add_file -vhdl -lib "work" "source/bit_sync.vhd" -add_file -vhdl -lib "work" "source/edge_to_pulse_fast.vhd" +add_file -vhdl -lib "work" "source/TDC.vhd" add_file -vhdl -lib "work" "source/up_counter.vhd" - - - - - - diff --git a/tdc_test/trb3_periph.vhd b/tdc_test/trb3_periph.vhd index 528f540..70d14d3 100644 --- a/tdc_test/trb3_periph.vhd +++ b/tdc_test/trb3_periph.vhd @@ -13,10 +13,10 @@ use work.version.all; entity trb3_periph is port( --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA - CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! - CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz < -- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz < -- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz < -- For TDC. Same oscillator as GPLL right! --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out @@ -70,27 +70,27 @@ entity trb3_periph is attribute syn_useioff : boolean; --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - attribute syn_useioff of CODE_LINE : signal is false; - attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; attribute syn_useioff of TRIGGER_RIGHT : signal is false; --important signals _with_ IO-FF - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; attribute syn_useioff of FLASH_DOUT : signal is true; attribute syn_useioff of FPGA5_COMM : signal is true; - attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of DQLL : signal is true; - attribute syn_useioff of DQUL : signal is true; - attribute syn_useioff of DQLR : signal is true; - attribute syn_useioff of DQUR : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of DQLL : signal is true; + attribute syn_useioff of DQUL : signal is true; + attribute syn_useioff of DQLR : signal is true; + attribute syn_useioff of DQUR : signal is true; attribute syn_useioff of SPARE_LINE : signal is true; @@ -105,14 +105,14 @@ architecture trb3_periph_arch of trb3_periph is attribute syn_preserve : boolean; --Clock / Reset - signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; --Media Interface signal med_stat_op : std_logic_vector (1*16-1 downto 0); @@ -139,6 +139,11 @@ architecture trb3_periph_arch of trb3_periph is signal trg_code_i : std_logic_vector(7 downto 0); signal trg_information_i : std_logic_vector(23 downto 0); signal trg_int_number_i : std_logic_vector(15 downto 0); + signal trg_multiple_trg_i : std_logic; + signal trg_timeout_detected_i: std_logic; + signal trg_spurious_trg_i : std_logic; + signal trg_missing_tmg_trg_i : std_logic; + signal trg_spike_detected_i : std_logic; --Data channel signal fee_trg_release_i : std_logic; @@ -204,20 +209,32 @@ architecture trb3_periph_arch of trb3_periph is --TDC component component TDC generic ( - CHANNEL_NUMBER : integer range 0 to 64); + CHANNEL_NUMBER : integer range 0 to 64; + TRG_WIN_PRE : std_logic_vector(15 downto 0); + TRG_WIN_POST : std_logic_vector(15 downto 0)); port ( - RESET : in std_logic; - CLK_TDC : in std_logic; - CLK_READOUT : in std_logic; - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - TRIGGER_IN : in std_logic; - TRIGGER_WIN_IN : in std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - TRB_WR_CLK_OUT : out std_logic; - DATA_VALID_OUT : out std_logic; - DATA_FINISHED_OUT : out std_logic; - READY_OUT : out std_logic; - TDC_DEBUG_00 : out std_logic_vector(31 downto 0)); + RESET : in std_logic; + CLK_TDC : in std_logic; + CLK_READOUT : in std_logic; + REFERENCE_TIME : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-2 downto 0); + TRG_DATA_VALID_IN : in std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + INVALID_TRG_IN : in std_logic; + TMGTRG_TIMEOUT_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + TRG_CODE_IN : in std_logic_vector(7 downto 0); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + TRG_TYPE_IN : in std_logic_vector(3 downto 0); + TRG_RELEASE_OUT : out std_logic; + TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_WRITE_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; + TDC_DEBUG_00 : out std_logic_vector(31 downto 0)); end component; begin @@ -229,7 +246,7 @@ begin THE_RESET_HANDLER : trb_net_reset_handler generic map( - RESET_DELAY => x"FEEE" + RESET_DELAY => x"FEEE" ) port map( CLEAR_IN => '0', -- reset input (high active, async) @@ -242,7 +259,7 @@ begin CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => open - ); + ); --------------------------------------------------------------------------- @@ -262,9 +279,9 @@ begin --------------------------------------------------------------------------- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp generic map( - SERDES_NUM => 1, --number of serdes in quad - EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES --run on 200 MHz clock + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES --run on 200 MHz clock ) port map( CLK => clk_200_i, @@ -304,8 +321,8 @@ begin --------------------------------------------------------------------------- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg ADDRESS_MASK => x"FFFF", BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"45", @@ -317,7 +334,7 @@ begin TIMING_TRIGGER_RAW => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_DEPTH => 13, --13 DATA_BUFFER_WIDTH => 32, DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024 TRG_RELEASE_AFTER_DATA => c_YES, @@ -325,19 +342,19 @@ begin HEADER_BUFFER_FULL_THRESH => 2**9-16 ) port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, -- open, -- - MED_DATA_OUT => med_data_out, -- open, -- - MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, -- open, -- - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, --Timing trigger in TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, @@ -353,6 +370,13 @@ begin LVL1_TRG_INFORMATION_OUT => trg_information_i, LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i, + TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i, + TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i, + TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i, + TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i, + --Response from FEE FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, @@ -410,9 +434,9 @@ begin -- AddOn --------------------------------------------------------------------------- DQLL(47 downto 8) <= (others => '0'); - DQUL <= (others => '0'); - DQLR <= (others => '0'); - DQUR <= (others => '0'); + DQUL <= (others => '0'); + DQLR <= (others => '0'); + DQUR <= (others => '0'); --------------------------------------------------------------------------- -- Bus Handler @@ -424,8 +448,8 @@ begin PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) ) port map( - CLK => clk_100_i, - RESET => reset_i, + CLK => clk_100_i, + RESET => reset_i, DAT_ADDR_IN => regio_addr_out, DAT_DATA_IN => regio_data_out, @@ -541,12 +565,14 @@ begin --------------------------------------------------------------------------- -- Test Connector ---------------------------------------------------------------------------- - TEST_LINE(7 downto 0) <= open; -- med_data_in(7 downto 0); - TEST_LINE(8) <= open; -- med_dataready_in; - TEST_LINE(9) <= open; -- med_dataready_out; - TEST_LINE(10) <= open; -- stat_reg_strobe(0); - TEST_LINE(15 downto 11) <= open; -- (others => '0'); +--------------------------------------------------------------------------- +-- TEST_LINE(7 downto 0) <= x"00"; -- med_data_in(7 downto 0); +-- TEST_LINE(8) <= '0'; -- med_dataready_in; +-- TEST_LINE(9) <= '0'; -- med_dataready_out; +-- TEST_LINE(10) <= '0'; -- stat_reg_strobe(0); +-- TEST_LINE(15 downto 11) <= "00000"; -- (others => '0'); + + TEST_LINE(15 downto 0) <= x"0000"; --------------------------------------------------------------------------- @@ -564,21 +590,55 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 8) -- Number of TDC channels + CHANNEL_NUMBER => 8, -- Number of TDC channels + TRG_WIN_PRE => x"0023", -- Pre-Trigger window width + TRG_WIN_POST => x"0023") -- Post-Trigger window width port map ( - RESET => reset_i, - CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement - CLK_READOUT => clk_100_i, -- Clock for the readout - HIT_IN => DQLL(7 downto 0), -- Channel start signals - TRIGGER_IN => trg_timing_valid_i, -- Readout trigger - TRIGGER_WIN_IN => x"00640000", -- Trigger window register relative to - -- the trigger (post edge & pre edge) - DATA_OUT => fee_data_i, -- Data to readout - TRB_WR_CLK_OUT => open, -- Readout clk (maybe not necessary - -- in trb3) - DATA_VALID_OUT => fee_data_write_i, -- Data valid signal - DATA_FINISHED_OUT => fee_data_finished_i, -- Readout finished signal - READY_OUT => fee_trg_release_i, -- Ready for the next trigger - TDC_DEBUG_00 => open); -- Debug + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => DQLL(6 downto 0), -- Channel start signals + TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal + -- from trbnet + VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger + -- signal from trbnet + VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal + -- from trbnet + INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet + TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet + SPIKE_DETECTED_IN => trg_spike_detected_i, + MULTI_TMG_TRG_IN => trg_multiple_trg_i, + + TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package + TRG_CODE_IN => trg_code_i, -- + TRG_INFORMATION_IN => trg_information_i, -- + TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package + TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal + TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of + -- the tdc + DATA_OUT => fee_data_i, -- tdc data + DATA_WRITE_OUT => fee_data_write_i, -- data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + TDC_DEBUG_00 => stat_reg(31 downto 0)); + +-- THE_TDC : TDC +-- generic map ( +-- CHANNEL_NUMBER => 8) -- Number of TDC channels +-- port map ( +-- RESET => reset_i, +-- CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement +-- CLK_READOUT => clk_100_i, -- Clock for the readout +-- HIT_IN => DQLL(7 downto 0), -- Channel start signals +-- TRIGGER_IN => trg_timing_valid_i, -- Readout trigger +-- TRIGGER_WIN_IN => x"00640000", -- Trigger window register relative to +-- -- the trigger (post edge & pre edge) +-- DATA_OUT => fee_data_i, -- Data to readout +-- TRB_WR_CLK_OUT => open, -- Readout clk (maybe not necessary +-- -- in trb3) +-- DATA_VALID_OUT => fee_data_write_i, -- Data valid signal +-- DATA_FINISHED_OUT => fee_data_finished_i, -- Readout finished signal +-- READY_OUT => fee_trg_release_i, -- Ready for the next trigger +-- TDC_DEBUG_00 => open); -- Debug end architecture;