From: Ingo Froehlich <ingo@nomail.fake>
Date: Wed, 30 Aug 2017 12:48:28 +0000 (+0200)
Subject: 32bit flash read and endian option, IF
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7e294c8da4c41ae0fbbbdc21adfac0a730172894;p=vhdlbasics.git

32bit flash read and endian option, IF
---

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index da219b8..f59260f 100644
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -16,8 +16,9 @@
 --  0x5C : control register
 --         Bit 0 : Enable cfg flash
 --         Bit 1 : Master start (starts unpacking = booting)
---  0x5D : Flash memory return buswidth:
+--  0x5D : Bits 0/1: Flash memory read buswidth:
 --         00 : 8 Bit, 01 : 16 Bit, 11 : 32 Bit (if available)
+--         Bit 8: 0: Little Endian; 1: Big Endian
 --  0x5E-5F : Debug registers
 
 
@@ -251,16 +252,24 @@ PROC_SELECTOR : process begin
     else --continue
       reg_SPI_READY_OUT <= '0';
       if (memreg(1) = '1') then
-        -- at least 32 bit burst
+        -- at least 24 bit burst
         spi_ram_addr_i <= std_logic_vector(unsigned(spi_ram_addr_i)+1); --prepare nibble3
       end if;
-      reg_SPI_DATA_OUT(15 downto 0) <= x"00" & ram_data_o; -- write nibble1
+      if (memreg(8) = '1') then
+        reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) <= ram_data_o;
+      else
+        reg_SPI_DATA_OUT(15 downto 0) <= x"00" & ram_data_o; -- write nibble1
+      end if;
       out_delay <= "011";
     end if;
   elsif (out_delay = "011") then
     reg_LOC_READ_OUT  <= '0';
-    reg_SPI_DATA_OUT(15 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(7 downto 0);
+    if (memreg(8) = '1') then
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-16) <= reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-8) & ram_data_o;
+    else
+      reg_SPI_DATA_OUT(15 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(7 downto 0);
     -- write nibble2
+    end if;
     if (memreg(1) = '0' or DATA_BUS_WIDTH < 32) then
       out_delay <= "000";
       reg_SPI_READY_OUT <= '1';
@@ -273,12 +282,21 @@ PROC_SELECTOR : process begin
   elsif (out_delay = "100" and DATA_BUS_WIDTH > 16) then
     reg_LOC_READ_OUT  <= '0';
     reg_SPI_READY_OUT <= '0';
-    reg_SPI_DATA_OUT(23 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(15 downto 0);
+    if (memreg(8) = '1') then
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-24) <= reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto DATA_BUS_WIDTH-16) & ram_data_o;
+    else
+      reg_SPI_DATA_OUT(23 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(15 downto 0);
+    end if;
     out_delay <= "101";
   elsif (out_delay = "101" and DATA_BUS_WIDTH > 24) then
     reg_LOC_READ_OUT  <= '0';
     reg_SPI_READY_OUT <= '1';
-    reg_SPI_DATA_OUT(31 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(23 downto 0);
+    if (memreg(8) = '1') then
+      reg_SPI_DATA_OUT(31 downto 0) <= reg_SPI_DATA_OUT(31 downto 8) & ram_data_o;
+    else
+      reg_SPI_DATA_OUT(31 downto 0) <= ram_data_o & reg_SPI_DATA_OUT(23 downto 0);
+    end if;
+    out_delay <= "000";
   else
     out_delay <= "000";
   end if;