From: Jan Michel Date: Thu, 4 Jul 2013 14:18:51 +0000 (+0200) Subject: made 'bit' required for fields X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7f3c07615d99d9461be4800584e2958c9b35f0f6;p=daqtools.git made 'bit' required for fields --- diff --git a/xml-db/database/JtagController.xml b/xml-db/database/JtagController.xml index edf0504..8f32ba0 100644 --- a/xml-db/database/JtagController.xml +++ b/xml-db/database/JtagController.xml @@ -54,7 +54,7 @@ address="0010" mode="rw" purpose="config" > Generate a reset before doing init sequence + start="0" bits="1" mode="rw" purpose="config" format="boolean"> Enable to send a reset pulse before starting init sequence @@ -62,7 +62,7 @@ address="0011" mode="rw" purpose="config" > Generate a reset after first register write sequence + start="0" bits="1" mode="rw" purpose="config" format="boolean"> Enable to send a reset pulse after the first writing of JTAG registers @@ -81,59 +81,59 @@ address="0000" repeat="5" > Sets fixed values for all outputs for JTAG and sensor control and inverts the outputs if needed. One register for each JTAG chain. + start="0" bits="1" format="boolean"> Invert TDO input signal + start="2" bits="1" format="boolean"> Invert TDI output signal + start="4" bits="1" format="boolean"> Invert TMS output signal + start="6" bits="1" format="boolean"> Invert TCK output signal + start="8" bits="1" format="boolean"> Invert Start output signal + start="10" bits="1" format="boolean"> Invert Reset output signal + start="12" bits="1" format="boolean"> Invert Clock output signal + start="1" bits="1" format="boolean"> Enable TDO input signal + start="3" bits="1" format="boolean"> Enable TDI output signal + start="5" bits="1" format="boolean"> Enable TMS output signal + start="7" bits="1" format="boolean"> Enable TCK output signal + start="9" bits="1" format="boolean"> Enable Start output signal + start="11" bits="1" format="boolean"> Enable Reset output signal + start="13" bits="1" format="boolean"> Enable Clock output signal @@ -181,27 +181,27 @@ address="0005" purpose="status" mode="r" > Status flags of the JTAG chain + start="0" bits="1" mode="r" purpose="status" format="boolean" > JTAG has been started + start="4" bits="1" mode="r" purpose="status" format="boolean" > Last JTAG run was successful + start="8" bits="1" mode="r" purpose="status" format="boolean" > Data in the sensor was corrupted at last JTAG run + start="12" bits="1" mode="r" purpose="status" format="boolean" > Last run had a JTAG write error + start="16" bits="1" mode="r" purpose="status" format="boolean" > Last run had a JTAG read error + start="20" bits="1" mode="r" purpose="status" format="boolean" > Last run had a JTAG CRC error diff --git a/xml-db/database/TDC.xml b/xml-db/database/TDC.xml index 5700f8a..6ffe0a6 100644 --- a/xml-db/database/TDC.xml +++ b/xml-db/database/TDC.xml @@ -52,11 +52,11 @@ Number of implemented channels - + Reference time synchronised to 100 MHz Trb-Net clock - + Trigger type @@ -77,7 +77,7 @@ Trigger window width AFTER the trigger with granularity of 5 ns - + Trigger window enabled? @@ -182,11 +182,11 @@ Enables different signals to the HPLA* output for debugging with logic analyser - + Enables the Debug Mode. Different statistics and debug words are sent after every trigger - + Resets the internal counters @@ -207,7 +207,7 @@ Trigger window width AFTER the trigger with granularity of 5 ns. ATTENTION: Minimum value is x"00f"! - + Trigger window enable diff --git a/xml-db/schema/TrbNetCommon.xsd b/xml-db/schema/TrbNetCommon.xsd index 97ea901..d776494 100644 --- a/xml-db/schema/TrbNetCommon.xsd +++ b/xml-db/schema/TrbNetCommon.xsd @@ -187,7 +187,7 @@ - +