From: Ludwig Maier Date: Fri, 28 Aug 2015 14:04:24 +0000 (+0200) Subject: update X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=80e57a0039ff5a02564de51714ba0b73d7951503;p=adcm.git update --- diff --git a/0x4c168bfe/adcmv3.lpf b/0x4c168bfe/adcmv3.lpf old mode 100644 new mode 100755 diff --git a/Makefile b/Makefile index fd51954..92959c8 100644 --- a/Makefile +++ b/Makefile @@ -1,10 +1,8 @@ -# Call . /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env - TARGET=adcmv3 -FAMILYNAME=LatticeECP3 -DEVICENAME=LFE3-150EA -PACKAGE=FPBGA672 -SPEEDGRADE=8 +FAMILYNAME=LATTICEECP2M +DEVICENAME=LFE2M100E +PACKAGE=FPBGA900 +SPEEDGRADE=6 TIMESTAMP=$(shell date '+%s') VERSION=$(shell cat version-major-minor.txt) @@ -17,6 +15,7 @@ all: workdir/$(TARGET).bit .PHONY: clean clean: rm -rf workdir/* + rm -f workdir/.[a-z,A-Z]* .PHONY: distclean distclean: @@ -39,6 +38,8 @@ checkenv: # Bitgen workdir/$(TARGET).bit: workdir/$(TARGET).ncd + @$(MAKE) report + @echo "" @echo "----------------------------------------------------------------------" @echo "-------------- Bitgen ------------------------------------------------" @@ -46,7 +47,7 @@ workdir/$(TARGET).bit: workdir/$(TARGET).ncd cd workdir && \ bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $(TARGET).ncd \ $(TARGET).bit $(TARGET).prf - @$(MAKE) report + @$(MAKE) error # Place and Route (multipar) @@ -59,6 +60,13 @@ workdir/$(TARGET).ncd: workdir/$(TARGET)_map.ncd cd workdir && \ par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd + # + # Multipar geht gerade nicht + #par $(TARGET)_map.ncd $(TARGET).prf + #mv $(TARGET).prf.ncd $(TARGET).ncd + # par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf + #cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd + # Mapper workdir/$(TARGET)_map.ncd: workdir/$(TARGET).ngd $(TARGET).lpf @@ -100,6 +108,9 @@ workdir/$(TARGET).edf: @echo "----------------------------------------------------------------------" @echo "--------------- VHDL Compiler ----------------------------------------" @echo "----------------------------------------------------------------------" + + #$(SYNPLIFY)/bin/synplify_premier_dp -batch $TOPNAME.prj || \ + # (grep "@E" workdir/$(TARGET).srr && exit 2) synpwrap -prj $(TARGET).prj || \ (grep "@E" workdir/$(TARGET).srr && exit 2) @@ -136,9 +147,9 @@ workdir: @echo "-------------- Setup Workdir -----------------------------------------" @echo "----------------------------------------------------------------------" mkdir -p workdir - cd workdir && ../../base/linkdesignfiles.sh + #cd workdir && ../../base/linkdesignfiles.sh cp $(TARGET).lpf workdir/$(TARGET).lpf -# cat $(TARGET)_constraints.lpf >> workdir/$(TARGET).lpf + cat $(TARGET)_constraints.lpf >> workdir/$(TARGET).lpf cp nodelist.txt workdir/ # Timing Report diff --git a/adcmv3.lpf b/adcmv3.lpf index 9b69a65..f0f5fea 100755 --- a/adcmv3.lpf +++ b/adcmv3.lpf @@ -158,7 +158,7 @@ IOBUF PORT "BP_SECTOR_2" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_SECTOR_1" SITE "AF13" ; # was "AF12" IOBUF PORT "BP_SECTOR_1" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_SECTOR_0" SITE "AF15" ; # was "AF11" -IOBUF PORT "BP_MODULE_0 IO_TYPE=LVTTL33 PULLMODE=UP ; +IOBUF PORT "BP_MODULE_0" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_LED" SITE "AE8" ; IOBUF PORT "BP_LED" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ; @@ -238,22 +238,22 @@ LOCATE COMP "EXT_IN_0" SITE "AB28" ; # alternative, if needed # LOCATE COMP "EXT_IN_0" SITE "P28" ; IOBUF PORT "EXT_IN_0" IO_TYPE=LVTTL33 ; -LOCATE COMP "DBG_EXP_41" SITE "T27" ; -LOCATE COMP "DBG_EXP_39" SITE "T26" ; -LOCATE COMP "DBG_EXP_37" SITE "U26" ; -LOCATE COMP "DBG_EXP_35" SITE "V25" ; -LOCATE COMP "DBG_EXP_33" SITE "W25" ; -LOCATE COMP "DBG_EXP_31" SITE "W26" ; -LOCATE COMP "DBG_EXP_29" SITE "Y26" ; -LOCATE COMP "DBG_EXP_27" SITE "Y27" ; -LOCATE COMP "DBG_EXP_25" SITE "AB26" ; -LOCATE COMP "DBG_EXP_23" SITE "AC27" ; -LOCATE COMP "DBG_EXP_21" SITE "U25" ; -LOCATE COMP "DBG_EXP_19" SITE "U28" ; -LOCATE COMP "DBG_EXP_17" SITE "U27" ; -LOCATE COMP "DBG_EXP_5" SITE "R28" ; -LOCATE COMP "DBG_EXP_3" SITE "R27" ; -LOCATE COMP "DBG_EXP_1" SITE "T28" ; +# LOCATE COMP "DBG_EXP_41" SITE "T27" ; +# LOCATE COMP "DBG_EXP_39" SITE "T26" ; +# LOCATE COMP "DBG_EXP_37" SITE "U26" ; +# LOCATE COMP "DBG_EXP_35" SITE "V25" ; +# LOCATE COMP "DBG_EXP_33" SITE "W25" ; +# LOCATE COMP "DBG_EXP_31" SITE "W26" ; +# LOCATE COMP "DBG_EXP_29" SITE "Y26" ; +# LOCATE COMP "DBG_EXP_27" SITE "Y27" ; +# LOCATE COMP "DBG_EXP_25" SITE "AB26" ; +# LOCATE COMP "DBG_EXP_23" SITE "AC27" ; +# LOCATE COMP "DBG_EXP_21" SITE "U25" ; +# LOCATE COMP "DBG_EXP_19" SITE "U28" ; +# LOCATE COMP "DBG_EXP_17" SITE "U27" ; +# LOCATE COMP "DBG_EXP_5" SITE "R28" ; +# LOCATE COMP "DBG_EXP_3" SITE "R27" ; +# LOCATE COMP "DBG_EXP_1" SITE "T28" ; LOCATE COMP "UC_REBOOT" SITE "Y28" ; # was UC_FPGA3 IOBUF PORT "UC_REBOOT" IO_TYPE=LVTTL33 ; # LOCATE COMP "UC_FPGA_2" SITE "W27" ; @@ -311,34 +311,34 @@ IOBUF PORT "UC_RESET" IO_TYPE=LVTTL33 ; # I/O bank 2 - 3.30V # SFP control, LEDs, 1Wire ID, debug pins (SMC50) ###################################################################### -LOCATE COMP "DBG_EXP_43" SITE "R26" ; -LOCATE COMP "DBG_EXP_42" SITE "P25" ; -LOCATE COMP "DBG_EXP_40" SITE "P26" ; -LOCATE COMP "DBG_EXP_38" SITE "N25" ; -LOCATE COMP "DBG_EXP_36" SITE "M25" ; -LOCATE COMP "DBG_EXP_34" SITE "M26" ; -LOCATE COMP "DBG_EXP_32" SITE "L25" ; -LOCATE COMP "DBG_EXP_30" SITE "L26" ; -LOCATE COMP "DBG_EXP_28" SITE "K25" ; -LOCATE COMP "DBG_EXP_26" SITE "J26" ; -LOCATE COMP "DBG_EXP_24" SITE "H25" ; -LOCATE COMP "DBG_EXP_22" SITE "H26" ; -LOCATE COMP "DBG_EXP_20" SITE "H24" ; -LOCATE COMP "DBG_EXP_18" SITE "G26" ; -LOCATE COMP "DBG_EXP_16" SITE "G25" ; -LOCATE COMP "DBG_EXP_15" SITE "L27" ; -LOCATE COMP "DBG_EXP_14" SITE "L28" ; -LOCATE COMP "DBG_EXP_13" SITE "M28" ; -LOCATE COMP "DBG_EXP_12" SITE "K24" ; -LOCATE COMP "DBG_EXP_11" SITE "M27" ; -LOCATE COMP "DBG_EXP_10" SITE "M30" ; -LOCATE COMP "DBG_EXP_9" SITE "N26" ; -LOCATE COMP "DBG_EXP_8" SITE "M29" ; -LOCATE COMP "DBG_EXP_7" SITE "P27" ; -LOCATE COMP "DBG_EXP_6" SITE "L30" ; -LOCATE COMP "DBG_EXP_4" SITE "L29" ; -LOCATE COMP "DBG_EXP_2" SITE "K30" ; -LOCATE COMP "DBG_EXP_0" SITE "K29" ; +# LOCATE COMP "DBG_EXP_43" SITE "R26" ; +# LOCATE COMP "DBG_EXP_42" SITE "P25" ; +# LOCATE COMP "DBG_EXP_40" SITE "P26" ; +# LOCATE COMP "DBG_EXP_38" SITE "N25" ; +# LOCATE COMP "DBG_EXP_36" SITE "M25" ; +# LOCATE COMP "DBG_EXP_34" SITE "M26" ; +# LOCATE COMP "DBG_EXP_32" SITE "L25" ; +# LOCATE COMP "DBG_EXP_30" SITE "L26" ; +# LOCATE COMP "DBG_EXP_28" SITE "K25" ; +# LOCATE COMP "DBG_EXP_26" SITE "J26" ; +# LOCATE COMP "DBG_EXP_24" SITE "H25" ; +# LOCATE COMP "DBG_EXP_22" SITE "H26" ; +# LOCATE COMP "DBG_EXP_20" SITE "H24" ; +# LOCATE COMP "DBG_EXP_18" SITE "G26" ; +# LOCATE COMP "DBG_EXP_16" SITE "G25" ; +# LOCATE COMP "DBG_EXP_15" SITE "L27" ; +# LOCATE COMP "DBG_EXP_14" SITE "L28" ; +# LOCATE COMP "DBG_EXP_13" SITE "M28" ; +# LOCATE COMP "DBG_EXP_12" SITE "K24" ; +# LOCATE COMP "DBG_EXP_11" SITE "M27" ; +# LOCATE COMP "DBG_EXP_10" SITE "M30" ; +# LOCATE COMP "DBG_EXP_9" SITE "N26" ; +# LOCATE COMP "DBG_EXP_8" SITE "M29" ; +# LOCATE COMP "DBG_EXP_7" SITE "P27" ; +# LOCATE COMP "DBG_EXP_6" SITE "L30" ; +# LOCATE COMP "DBG_EXP_4" SITE "L29" ; +# LOCATE COMP "DBG_EXP_2" SITE "K30" ; +# LOCATE COMP "DBG_EXP_0" SITE "K29" ; LOCATE COMP "FPGA_LED_6" SITE "G28" ; IOBUF PORT "FPGA_LED_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ; LOCATE COMP "FPGA_LED_5" SITE "G27" ; @@ -444,8 +444,8 @@ IOBUF PORT "BP_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ; # simplify IO definitions ###################################################################### # Debug header (50pin SMC connector) -DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ; -IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN SLEWRATE=FAST ; +# DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ; +# IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=4 SLEWRATE=FAST ; # LED drivers # DEFINE PORT GROUP "led_output_group" "FPGA_LED*" ; diff --git a/adcmv3.p2t b/adcmv3.p2t new file mode 100644 index 0000000..9f1cba2 --- /dev/null +++ b/adcmv3.p2t @@ -0,0 +1,11 @@ +-w +-i 2 +-l 5 +-n 2 +-t 10 +-s 1 +-c 1 +-e 2 +-stopzero +-m nodelist.txt +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/adcmv3.prj b/adcmv3.prj old mode 100644 new mode 100755 index ee7a2ef..393b5c1 --- a/adcmv3.prj +++ b/adcmv3.prj @@ -5,128 +5,122 @@ # add_file options add_file -vhdl -lib work "version.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" -add_file -vhdl -lib work "source/adcmv3_components.vhd" -add_file -vhdl -lib work "source/adcmv3_components2.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "design/adcmv3_components.vhd" # ADCMv3 design files -# Top level entity -add_file -vhdl -lib work "adcmv3.vhd" - -add_file -vhdl -lib work "source/dbg_reg.vhd" -add_file -vhdl -lib work "source/reset_handler.vhd" -add_file -vhdl -lib work "source/reboot_handler.vhd" -add_file -vhdl -lib work "source/pulse_sync.vhd" -add_file -vhdl -lib work "source/state_sync.vhd" -add_file -vhdl -lib work "source/apv_sync_handler.vhd" -add_file -vhdl -lib work "source/apv_trg_handler.vhd" -add_file -vhdl -lib work "source/eds_buf.vhd" -add_file -vhdl -lib work "source/max_data.vhd" -add_file -vhdl -lib work "source/real_trg_handler.vhd" -add_file -vhdl -lib work "source/pulse_stretch.vhd" -add_file -vhdl -lib work "source/apv_trgctrl.vhd" -add_file -vhdl -lib work "source/adc_channel_select.vhd" -add_file -vhdl -lib work "source/adc_crossover.vhd" -add_file -vhdl -lib work "source/adc_twochannels.vhd" -add_file -vhdl -lib work "source/adc_data_handler.vhd" -add_file -vhdl -lib work "source/apv_raw_buffer.vhd" -add_file -vhdl -lib work "source/apv_lock_sm.vhd" -add_file -vhdl -lib work "source/apv_digital.vhd" -add_file -vhdl -lib work "source/apv_locker.vhd" -add_file -vhdl -lib work "source/raw_buf_stage.vhd" -add_file -vhdl -lib work "source/apv_pc_nc_alu.vhd" -add_file -vhdl -lib work "source/buf_toc.vhd" -add_file -vhdl -lib work "source/ref_row_sel.vhd" -add_file -vhdl -lib work "source/frmctr_check.vhd" -add_file -vhdl -lib work "source/ped_corr_ctrl.vhd" -add_file -vhdl -lib work "source/ipu_fifo_stage.vhd" -add_file -vhdl -lib work "source/slv_register.vhd" -add_file -vhdl -lib work "source/slv_adc_snoop.vhd" -add_file -vhdl -lib work "source/slv_half_register.vhd" -add_file -vhdl -lib work "source/slv_status.vhd" -add_file -vhdl -lib work "source/slv_status_bank.vhd" -add_file -vhdl -lib work "source/slv_register_bank.vhd" -add_file -vhdl -lib work "source/spi_real_slim.vhd" -add_file -vhdl -lib work "source/spi_adc_master.vhd" -add_file -vhdl -lib work "source/onewire_master.vhd" -add_file -vhdl -lib work "source/slv_onewire_memory.vhd" -add_file -vhdl -lib work "source/i2c_gstart.vhd" -add_file -vhdl -lib work "source/i2c_sendb.vhd" -add_file -vhdl -lib work "source/i2c_slim.vhd" -add_file -vhdl -lib work "source/i2c_master.vhd" -add_file -vhdl -lib work "source/slv_ped_thr_mem.vhd" -add_file -vhdl -lib work "source/slave_bus.vhd" -add_file -vhdl -lib work "source/rich_trb.vhd" - -# Addons -add_file -vhdl -lib work "source/debug_multiplexer.vhd" - -# Core files -add_file -vhdl -lib work "cores/adc_ch_in.vhd" -add_file -vhdl -lib work "cores/eds_buffer_dpram.vhd" -add_file -vhdl -lib work "cores/crossover.vhd" -add_file -vhdl -lib work "cores/frame_status_mem.vhd" -add_file -vhdl -lib work "cores/input_bram.vhd" -add_file -vhdl -lib work "cores/decoder_8bit.vhd" -add_file -vhdl -lib work "cores/adc_apv_map_mem.vhd" -add_file -vhdl -lib work "cores/fifo_1kx18.vhd" -add_file -vhdl -lib work "cores/fifo_2kx27.vhd" -add_file -vhdl -lib work "cores/adc_snoop_mem.vhd" -add_file -vhdl -lib work "cores/apv_adc_map_mem.vhd" -add_file -vhdl -lib work "cores/onewire_spare_one.vhd" -add_file -vhdl -lib work "cores/adc_onewire_map_mem.vhd" -add_file -vhdl -lib work "cores/ped_thr_true.vhd" -add_file -vhdl -lib work "cores/sync_pll_40m.vhd" -add_file -vhdl -lib work "cores/dll_100m.vhd" -add_file -vhdl -lib work "cores/pll_40m.vhd" -add_file -vhdl -lib work "cores/slv_onewire_dpram.vhd" +add_file -vhdl -lib work "design/adcmv3.vhd" +add_file -vhdl -lib work "design/dbg_reg.vhd" +add_file -vhdl -lib work "design/reset_handler.vhd" +add_file -vhdl -lib work "design/reboot_handler.vhd" +add_file -vhdl -lib work "design/pulse_sync.vhd" +add_file -vhdl -lib work "design/adc_ch_in.vhd" +add_file -vhdl -lib work "design/state_sync.vhd" +add_file -vhdl -lib work "design/apv_sync_handler.vhd" +add_file -vhdl -lib work "design/apv_trg_handler.vhd" +add_file -vhdl -lib work "design/eds_buffer_dpram.vhd" +add_file -vhdl -lib work "design/eds_buf.vhd" +add_file -vhdl -lib work "design/max_data.vhd" +add_file -vhdl -lib work "design/real_trg_handler.vhd" +add_file -vhdl -lib work "design/pulse_stretch.vhd" +add_file -vhdl -lib work "design/apv_trgctrl.vhd" +add_file -vhdl -lib work "design/adc_channel_select.vhd" +add_file -vhdl -lib work "design/crossover.vhd" +add_file -vhdl -lib work "design/adc_crossover.vhd" +add_file -vhdl -lib work "design/adc_twochannels.vhd" +add_file -vhdl -lib work "design/adc_data_handler.vhd" +add_file -vhdl -lib work "design/frame_status_mem.vhd" +add_file -vhdl -lib work "design/input_bram.vhd" +add_file -vhdl -lib work "design/apv_raw_buffer.vhd" +add_file -vhdl -lib work "design/apv_lock_sm.vhd" +add_file -vhdl -lib work "design/apv_digital.vhd" +add_file -vhdl -lib work "design/apv_locker.vhd" +add_file -vhdl -lib work "design/raw_buf_stage.vhd" +add_file -vhdl -lib work "design/decoder_8bit.vhd" +add_file -vhdl -lib work "design/apv_pc_nc_alu.vhd" +add_file -vhdl -lib work "design/buf_toc.vhd" +add_file -vhdl -lib work "design/ref_row_sel.vhd" +add_file -vhdl -lib work "design/frmctr_check.vhd" +add_file -vhdl -lib work "design/ped_corr_ctrl.vhd" +add_file -vhdl -lib work "design/adc_apv_map_mem.vhd" +add_file -vhdl -lib work "design/fifo_1kx18.vhd" +add_file -vhdl -lib work "design/fifo_2kx27.vhd" +add_file -vhdl -lib work "design/ipu_fifo_stage.vhd" +add_file -vhdl -lib work "design/slv_register.vhd" +add_file -vhdl -lib work "design/adc_snoop_mem.vhd" +add_file -vhdl -lib work "design/slv_adc_snoop.vhd" +add_file -vhdl -lib work "design/slv_half_register.vhd" +add_file -vhdl -lib work "design/slv_status.vhd" +add_file -vhdl -lib work "design/slv_status_bank.vhd" +add_file -vhdl -lib work "design/apv_adc_map_mem.vhd" +add_file -vhdl -lib work "design/slv_register_bank.vhd" +add_file -vhdl -lib work "design/spi_real_slim.vhd" +add_file -vhdl -lib work "design/spi_adc_master.vhd" +add_file -vhdl -lib work "design/slv_onewire_dpram.vhd" +add_file -vhdl -lib work "design/onewire_master.vhd" +add_file -vhdl -lib work "design/onewire_spare_one.vhd" +add_file -vhdl -lib work "design/adc_onewire_map_mem.vhd" +add_file -vhdl -lib work "design/slv_onewire_memory.vhd" +add_file -vhdl -lib work "design/i2c_gstart.vhd" +add_file -vhdl -lib work "design/i2c_sendb.vhd" +add_file -vhdl -lib work "design/i2c_slim.vhd" +add_file -vhdl -lib work "design/i2c_master.vhd" +add_file -vhdl -lib work "design/ped_thr_true.vhd" +add_file -vhdl -lib work "design/slv_ped_thr_mem.vhd" +add_file -vhdl -lib work "design/slave_bus.vhd" +add_file -vhdl -lib work "design/rich_trb.vhd" +add_file -vhdl -lib work "design/sync_pll_40m.vhd" +add_file -vhdl -lib work "design/dll_100m.vhd" +add_file -vhdl -lib work "design/pll_40m.vhd" # TrbNet design files -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" -# add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd" -# add_file -vhdl -lib work "source/sfp_rx_handler.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" + +# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd" +# add_file -vhdl -lib work "design/sfp_rx_handler.vhd" # implementation: "workdir" impl -add workdir -type fpga + # device options set_option -technology LATTICE-ECP2M set_option -part LFE2M100E @@ -165,4 +159,3 @@ project -result_file "workdir/adcmv3.edf" set_option -vlog_std v2001 set_option -project_relative_includes 1 impl -active "workdir" - diff --git a/constraints_adcmv3.lpf b/adcmv3_constraints.lpf old mode 100644 new mode 100755 similarity index 100% rename from constraints_adcmv3.lpf rename to adcmv3_constraints.lpf diff --git a/cleanup_workdir.sh b/cleanup_workdir.sh deleted file mode 100755 index fe88ea6..0000000 --- a/cleanup_workdir.sh +++ /dev/null @@ -1,18 +0,0 @@ -#!/bin/sh -TOPNAME=adcmv3 - -rm -f workdir/${TOPNAME}.alt -rm -f workdir/${TOPNAME}.bgn -rm -f workdir/${TOPNAME}.bit -rm -f workdir/${TOPNAME}.edf -rm -f workdir/${TOPNAME}.fse -rm -f workdir/${TOPNAME}.mrp -rm -f workdir/${TOPNAME}.ncd -rm -f workdir/${TOPNAME}.ngd -rm -f workdir/${TOPNAME}.ngo -rm -f workdir/${TOPNAME}.ngy -rm -f workdir/${TOPNAME}.pad -rm -f workdir/${TOPNAME}.par -rm -f workdir/${TOPNAME}.sr? -rm -f workdir/${TOPNAME}.tlg -rm -f workdir/${TOPNAME}.twr* diff --git a/compile.pl b/compile.pl new file mode 100755 index 0000000..e8ad213 --- /dev/null +++ b/compile.pl @@ -0,0 +1,216 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +########################################### + +# You need the tunnels before! + +use Data::Dumper; +use warnings; +use strict; + +# Path settings for ispLEVER tools +my $lattice_path = '/usr/local/opt/synplify/8/isptools'; + +# Path settings for SynplifyPRO +my $synplify_path = '/usr/local/opt/synplify/premier'; +# my $synplify_path = '/scratch/rich/synplify/D-2009.12'; + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}="27000\@localhost"; + +# Design top level entity +my $TOPNAME="adcmv3"; + +# FPGA chip description +my $FAMILYNAME="LATTICEECP2M"; +my $DEVICENAME="LFE2M100E"; +my $PACKAGE="FPBGA900"; +my $SPEEDGRADE="6"; + +# benchmarking +my $CTIME_String = localtime(time); +print "Script started: $CTIME_String\n"; +system("echo $CTIME_String > workdir/benchmark.txt"); + +# cleanup in workdir +system("rm workdir/$TOPNAME.alt"); +system("rm workdir/$TOPNAME.bgn"); +system("rm workdir/$TOPNAME.bit"); +system("rm workdir/$TOPNAME.edf"); +system("rm workdir/$TOPNAME.fse"); +system("rm workdir/$TOPNAME.mrp"); +system("rm workdir/$TOPNAME.ncd"); +system("rm workdir/$TOPNAME.ngd"); +system("rm workdir/$TOPNAME.ngo"); +system("rm workdir/$TOPNAME.ngy"); +system("rm workdir/$TOPNAME.pad"); +system("rm workdir/$TOPNAME.par"); +system("rm workdir/$TOPNAME.sr?"); +system("rm workdir/$TOPNAME.tlg"); +system("rm workdir/$TOPNAME.twr*"); + +# Create full lpf file +system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf"); + +# Generate timestamp for slowcontrol readback +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +# Run Synplify on the design +system("env| grep LM_"); +my $r = ""; +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj"; +$r=execute($c, "do_not_exit" ); + +# Check for errors +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +foreach (@a) +{ + if(/\@E:/) + { + $c="cat $TOPNAME.srr"; + system($c); + print "ERROR_ERROR_ERROR_ERROR_ERROR\n"; + exit 129; + } +} + +# ispLEVER design flow starts here +# new license file must be given +$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de"; + +# EDIF2NGD +$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +# NGDBUILD +$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +# MAP +my $tpmap = $TOPNAME . "_map" ; +$c=qq|$lattice_path/ispfpga/bin/lin/map -noinferGSR -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf" -tdm -td_pack|; +execute($c); + +system("rm $TOPNAME.ncd"); + +# MULTIPAR + +my $fh2 = new FileHandle(">$TOPNAME.p2t"); +die "could not open file" if (! defined $fh2); +print $fh2 <close; + +###################################################################### +# -w # overwrite files +# -i 15 # maximum number of routing attempts +# -l 5 # effort level (1-5) +# -n 1 # starting cost table (n=0 loop) +# -y # delay summary report +# -s 12 # number of best results to save +# -t 1 # start placement with cost table X +# -c 1 # number of cost-based cleanup passes of the router +# -e 2 # number of delay-based cleanup passes of the router +# -m nodelist.txt # +# -exp parCDP=1 # +# -exp parCDR=1 # +# -exp parPlcInLimit=0 # +# -exp parPlcInNeighborSize=1 # +# -exp parPathBased=ON # +# -exp parHold=ON # +# -exp parHoldLimit=10000 # +# -exp paruseNBR=1 # +###################################################################### + +# real multipar +$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +execute($c); + +# IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +# TWR Timing Report (setup) +$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# TWR Timing Report (hold) +$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +# BitGen +#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +chdir ".."; + +$CTIME_String = localtime(time); +print "Script ended: $CTIME_String\n"; +system("echo $CTIME_String >> workdir/benchmark.txt"); + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/constraints_adcmv3_BACK.lpf b/constraints_adcmv3_BACK.lpf old mode 100644 new mode 100755 diff --git a/debug_pin.txt b/debug_pin.txt old mode 100644 new mode 100755 diff --git a/cores/adc_apv_map_mem.lpc b/design/adc_apv_map_mem.lpc similarity index 100% rename from cores/adc_apv_map_mem.lpc rename to design/adc_apv_map_mem.lpc diff --git a/cores/adc_apv_map_mem.srp b/design/adc_apv_map_mem.srp similarity index 100% rename from cores/adc_apv_map_mem.srp rename to design/adc_apv_map_mem.srp diff --git a/cores/adc_apv_map_mem.vhd b/design/adc_apv_map_mem.vhd similarity index 100% rename from cores/adc_apv_map_mem.vhd rename to design/adc_apv_map_mem.vhd diff --git a/cores/adc_apv_map_mem_generate.log b/design/adc_apv_map_mem_generate.log similarity index 100% rename from cores/adc_apv_map_mem_generate.log rename to design/adc_apv_map_mem_generate.log diff --git a/cores/adc_apv_map_mem_tmpl.vhd b/design/adc_apv_map_mem_tmpl.vhd similarity index 100% rename from cores/adc_apv_map_mem_tmpl.vhd rename to design/adc_apv_map_mem_tmpl.vhd diff --git a/source/adc_apv_mapping.mem b/design/adc_apv_mapping.mem similarity index 100% rename from source/adc_apv_mapping.mem rename to design/adc_apv_mapping.mem diff --git a/cores/adc_ch_in.lpc b/design/adc_ch_in.lpc similarity index 100% rename from cores/adc_ch_in.lpc rename to design/adc_ch_in.lpc diff --git a/cores/adc_ch_in.srp b/design/adc_ch_in.srp similarity index 100% rename from cores/adc_ch_in.srp rename to design/adc_ch_in.srp diff --git a/cores/adc_ch_in.vhd b/design/adc_ch_in.vhd similarity index 100% rename from cores/adc_ch_in.vhd rename to design/adc_ch_in.vhd diff --git a/cores/adc_ch_in_tmpl.vhd b/design/adc_ch_in_tmpl.vhd similarity index 100% rename from cores/adc_ch_in_tmpl.vhd rename to design/adc_ch_in_tmpl.vhd diff --git a/source/adc_channel_select.vhd b/design/adc_channel_select.vhd similarity index 100% rename from source/adc_channel_select.vhd rename to design/adc_channel_select.vhd diff --git a/source/adc_crossover.vhd b/design/adc_crossover.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/adc_crossover.vhd rename to design/adc_crossover.vhd diff --git a/source/adc_data_handler.vhd b/design/adc_data_handler.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/adc_data_handler.vhd rename to design/adc_data_handler.vhd diff --git a/cores/adc_onewire_map_mem.lpc b/design/adc_onewire_map_mem.lpc similarity index 100% rename from cores/adc_onewire_map_mem.lpc rename to design/adc_onewire_map_mem.lpc diff --git a/cores/adc_onewire_map_mem.srp b/design/adc_onewire_map_mem.srp similarity index 100% rename from cores/adc_onewire_map_mem.srp rename to design/adc_onewire_map_mem.srp diff --git a/cores/adc_onewire_map_mem.vhd b/design/adc_onewire_map_mem.vhd similarity index 100% rename from cores/adc_onewire_map_mem.vhd rename to design/adc_onewire_map_mem.vhd diff --git a/cores/adc_onewire_map_mem_generate.log b/design/adc_onewire_map_mem_generate.log similarity index 100% rename from cores/adc_onewire_map_mem_generate.log rename to design/adc_onewire_map_mem_generate.log diff --git a/cores/adc_onewire_map_mem_tmpl.vhd b/design/adc_onewire_map_mem_tmpl.vhd similarity index 100% rename from cores/adc_onewire_map_mem_tmpl.vhd rename to design/adc_onewire_map_mem_tmpl.vhd diff --git a/source/adc_onewire_mapping.mem b/design/adc_onewire_mapping.mem similarity index 100% rename from source/adc_onewire_mapping.mem rename to design/adc_onewire_mapping.mem diff --git a/cores/adc_pll.lpc b/design/adc_pll.lpc similarity index 100% rename from cores/adc_pll.lpc rename to design/adc_pll.lpc diff --git a/cores/adc_pll.vhd b/design/adc_pll.vhd similarity index 100% rename from cores/adc_pll.vhd rename to design/adc_pll.vhd diff --git a/cores/adc_pll_tmpl.vhd b/design/adc_pll_tmpl.vhd similarity index 100% rename from cores/adc_pll_tmpl.vhd rename to design/adc_pll_tmpl.vhd diff --git a/cores/adc_snoop_mem.lpc b/design/adc_snoop_mem.lpc similarity index 100% rename from cores/adc_snoop_mem.lpc rename to design/adc_snoop_mem.lpc diff --git a/cores/adc_snoop_mem.srp b/design/adc_snoop_mem.srp similarity index 100% rename from cores/adc_snoop_mem.srp rename to design/adc_snoop_mem.srp diff --git a/cores/adc_snoop_mem.vhd b/design/adc_snoop_mem.vhd similarity index 100% rename from cores/adc_snoop_mem.vhd rename to design/adc_snoop_mem.vhd diff --git a/cores/adc_snoop_mem_generate.log b/design/adc_snoop_mem_generate.log similarity index 100% rename from cores/adc_snoop_mem_generate.log rename to design/adc_snoop_mem_generate.log diff --git a/cores/adc_snoop_mem_tmpl.vhd b/design/adc_snoop_mem_tmpl.vhd similarity index 100% rename from cores/adc_snoop_mem_tmpl.vhd rename to design/adc_snoop_mem_tmpl.vhd diff --git a/source/adc_twochannels.vhd b/design/adc_twochannels.vhd similarity index 100% rename from source/adc_twochannels.vhd rename to design/adc_twochannels.vhd diff --git a/adcmv3.vhd b/design/adcmv3.vhd old mode 100644 new mode 100755 similarity index 96% rename from adcmv3.vhd rename to design/adcmv3.vhd index f8f11da..518cc63 --- a/adcmv3.vhd +++ b/design/adcmv3.vhd @@ -83,9 +83,9 @@ port( U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM U_SPI_SCK : out std_logic; -- OK -- clock U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM - U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM + U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM -- Debug connections - DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header +-- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header ); end; @@ -215,6 +215,11 @@ type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0); signal adc_ctrl_reg : reg_16bit_t; signal adc_stat_reg : reg_16bit_t; signal raw_buf_dbg : reg_16bit_t; + +--signal debug : std_logic_vector(42 downto 0); +--signal debug_q : std_logic_vector(42 downto 0); +--signal debug_qq : std_logic_vector(42 downto 0); +--signal debug_clk : std_logic; -- LVL1 application interface signal lvl1_trg_type : std_logic_vector(3 downto 0); @@ -287,30 +292,9 @@ signal fe_error : std_logic; signal tick_10s : std_logic; --- Debug Multiplexer -signal debug_o : std_logic_vector(33 downto 0); - begin -------------------------------------------------------------------------------- --- Debug Out -------------------------------------------------------------------------------- - - DEBUG: for I in 0 to 15 generate - debug_o(2 * I) <= sysclk; - debug_o(2 * I + 1) <= not sysclk; - end generate DEBUG; - debug_o(32) <= sysclk; - debug_o(33) <= not sysclk; - - DBG_EXP(31 downto 0) <= debug_o(31 downto 0); - DBG_EXP(37 downto 32) <= (others => '0'); - DBG_EXP(38) <= debug_o(32); - DBG_EXP(41 downto 49) <= (others => '0'); - DBG_EXP(42) <= debug_o(33); - DBG_EXP(43) <= '0'; - ---------------------------------------- -- Async reset assignment -- ---------------------------------------- @@ -778,6 +762,7 @@ apv_reset <= apv0_reset or apv1_reset or frontend_reset; GEN_ADC_LVDS_ON: for i in 0 to 15 generate adc_on(i) <= adc_ctrl_reg(i)(0); lvds_on(i) <= adc_ctrl_reg(i)(1); +-- adc_stat_reg(i) <= raw_buf_dbg(i); adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4)); broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit apv_error(i) <= buf_data(i)(26); -- APV error frame bit diff --git a/design/adcmv3.vhd~ b/design/adcmv3.vhd~ new file mode 100755 index 0000000..9243d76 --- /dev/null +++ b/design/adcmv3.vhd~ @@ -0,0 +1,1394 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +--use ieee.std_logic_unsigned.all; + +library work; +use work.trb_net_std.all; +use work.adcmv3_components.all; + +library ecp2m; +use ecp2m.components.all; + +entity adcmv3 is +port( + CLK100M : in std_logic; -- OK -- 100MHz LVDS clock + -- trigger inputs + EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers + -- APV stuff + APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock + APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock + APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out + APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out + APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active + APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA + APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL + ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers + APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock + APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock + APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out + APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out + APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active + APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA + APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL + ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers + -- ADC0 stuff + ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL + ADC0_RST : out std_logic; -- OK -- ADC reset signal + ADC0_PD : out std_logic; -- OK -- ADC powerdown signal + ADC0_CS : out std_logic; -- OK -- ADC /CS signal + ADC0_SDI : out std_logic; -- OK -- ADC serial data in + ADC0_SCK : out std_logic; -- OK -- ADC serial clock + ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock + ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock + ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams + -- ADC1 stuff + ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL + ADC1_RST : out std_logic; -- OK -- ADC reset signal + ADC1_PD : out std_logic; -- OK -- ADC powerdown signal + ADC1_CS : out std_logic; -- OK -- ADC /CS signal + ADC1_SDI : out std_logic; -- OK -- ADC serial data in + ADC1_SCK : out std_logic; -- OK -- ADC serial clock + ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock + ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock + ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams + -- uC connections + UC_RESET : in std_logic; -- OK -- uC reset, high active + UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot + -- SerDes pins + HDINN2 : in std_logic; -- highspeed INPUT + HDINP2 : in std_logic; -- + HDOUTN2 : out std_logic; -- highspeed OUTPUT + HDOUTP2 : out std_logic; -- + SD_PRESENT : in std_logic; -- OK -- Present signal from SFP + SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP + SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable + ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM + -- Backplane sense wires + BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane + BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane + BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane + BP_LED : out std_logic; -- OK -- backplane LED + -- LEDs + FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS + FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2) + FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1) + FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0) + FPGA_LED_PLL : out std_logic; -- OK -- PLL locked + FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED + -- 1Wire chips on APV FEs + APV0_1W : inout std_logic_vector(7 downto 0); + APV1_1W : inout std_logic_vector(7 downto 0); + -- SPI FlashROM connections + U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM + U_SPI_SCK : out std_logic; -- OK -- clock + U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM + U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM + -- Debug connections +-- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header +); +end; + +architecture adcmv3 of adcmv3 is + +-- Signals +-- Clock related signals +signal clk100m_locked : std_logic; -- not needed at the moment +signal sysclk : std_logic; -- clean 100MHz for distribution + +signal adc0_ce : std_logic; +signal adc0_valid : std_logic; +signal adc0_swap : std_logic; +signal adc0_reset : std_logic; +signal adc0_powerdown : std_logic; +signal adc1_ce : std_logic; +signal adc1_valid : std_logic; +signal adc1_swap : std_logic; +signal adc1_reset : std_logic; +signal adc1_powerdown : std_logic; + +signal clk_adc : std_logic; -- 40MHz for ADC operation +signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!) +signal clk40m_locked : std_logic; +signal clk40m_reset : std_logic; + +signal async_reset : std_logic; + +-- APV related signals +signal apv_sda_out : std_logic; -- APV SDA +signal apv_sda_in : std_logic; +signal apv_scl_out : std_logic; -- APV SCL +signal apv_scl_in : std_logic; +signal apv_trg : std_logic; -- real APV trigger signal +signal apv_sync : std_logic; -- artificial signal +signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame +signal apv0_reset : std_logic; +signal apv1_reset : std_logic; +signal frontend_reset : std_logic; +signal apv_reset : std_logic; +signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] +signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] + +-- Control signals +signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register +signal status_pll : std_logic_vector(15 downto 0); -- PLL status register +signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register +signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register + +signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header +signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header +signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting +signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting + +signal maximum_trg : std_logic_vector(3 downto 0); + +signal raw_buf_full : std_logic; +signal eds_buf_full : std_logic; +signal eds_buf_level : std_logic_vector(4 downto 0); + +-- regIO data bus +signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); +signal regio_read_enable : std_logic; +signal regio_write_enable : std_logic; +signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); +signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); +signal regio_dataready : std_logic; +signal regio_no_more_data : std_logic; +signal regio_write_ack : std_logic; +signal regio_unknown_addr : std_logic; +signal regio_timeout : std_logic; + +-- common status / control registers from RegIO +signal common_stat_reg : std_logic_vector(63 downto 0); +signal common_ctrl_reg : std_logic_vector(95 downto 0); + +-- user defined "quick'n'dirty" registers +signal simple_status : std_logic_vector(127 downto 0); +signal simple_control : std_logic_vector(63 downto 0); + +-- debug signals +signal test_reg : std_logic_vector(31 downto 0); +signal trgctrl_debug : std_logic_vector(63 downto 0); +signal raw_buf_debug : std_logic_vector(63 downto 0); +--signal trbrich_debug : std_logic_vector(63 downto 0); +--signal slave_debug : std_logic_vector(63 downto 0); +--signal fifo_debug : std_logic_vector(63 downto 0); + +-- EDS / BUFFER signals (raw buf -> ped corr) +signal eds_data : std_logic_vector(39 downto 0); +signal eds_avail : std_logic; +signal eds_done : std_logic; +signal buf_addr : std_logic_vector(6 downto 0); +signal buf_done : std_logic; +signal buf_tick : std_logic_vector(15 downto 0); +signal buf_start : std_logic_vector(15 downto 0); +signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging! + +type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0); +signal buf_data : reg_38bit_t; + +signal thr_addr : std_logic_vector(6 downto 0); +type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0); +signal thr_data : reg_18bit_t; +signal ped_data : reg_18bit_t; + +-- FIFO / DHDR signals (ped corr -> ipu stage) +signal dhdr_data : std_logic_vector(31 downto 0); +signal dhdr_length : std_logic_vector(15 downto 0); +signal dhdr_store : std_logic; +signal dhdr_buf_full : std_logic; + +signal fifo_start : std_logic; +signal fifo_done : std_logic; +signal fifo_we : std_logic_vector(15 downto 0); +signal fifo_space_req : std_logic_vector(11 downto 0); +type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0); +signal fifo_data : reg_40bit_t; +type reg_32bit_t is array (0 to 15) of std_logic_vector(31 downto 0); +signal fifo_status : reg_32bit_t; + +signal ipu_handler_status : std_logic_vector(31 downto 0); +signal lvl1_release_status : std_logic_vector(31 downto 0); + +-- APV control / status signals +type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0); +signal adc_ctrl_reg : reg_16bit_t; +signal adc_stat_reg : reg_16bit_t; + +--signal debug : std_logic_vector(42 downto 0); +--signal debug_q : std_logic_vector(42 downto 0); +--signal debug_qq : std_logic_vector(42 downto 0); +--signal debug_clk : std_logic; + +-- LVL1 application interface +signal lvl1_trg_type : std_logic_vector(3 downto 0); +signal lvl1_trg_received : std_logic; +signal lvl1_trg_number : std_logic_vector(15 downto 0); +signal lvl1_trg_code : std_logic_vector(7 downto 0); +signal lvl1_trg_information : std_logic_vector(23 downto 0); +signal lvl1_error_pattern : std_logic_vector(31 downto 0); +signal lvl1_trg_release : std_logic; +signal lvl1_trg_missing : std_logic; +signal lvl1_int_trg_number : std_logic_vector(15 downto 0); +signal lvl1_int_trg_update : std_logic; +signal timing_trg_found : std_logic; +signal timing_trg_too_long : std_logic; + +-- IPU application interface +signal ipu_number : std_logic_vector(15 downto 0); +signal ipu_information : std_logic_vector(7 downto 0); +signal ipu_start_readout : std_logic; +signal ipu_data : std_logic_vector(31 downto 0); +signal ipu_dataready : std_logic; +signal ipu_readout_finished : std_logic; +signal ipu_read : std_logic; +signal ipu_length : std_logic_vector(15 downto 0); +signal ipu_error_pattern : std_logic_vector(31 downto 0); +signal ipu_last_num : std_logic_vector(31 downto 0); + +signal local_lvl1_counter : std_logic_vector(15 downto 0); +signal local_lvl2_counter : std_logic_vector(15 downto 0); + +-- ADC signals +type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0); +signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain +signal adc_data : reg_12bit_t; -- common APV clock domain + +signal adc1_testdata : std_logic_vector(11 downto 0); +signal adc0_testdata : std_logic_vector(11 downto 0); +signal adc1_select : std_logic_vector(2 downto 0); +signal adc0_select : std_logic_vector(2 downto 0); + +-- input synchronizing +signal bp_sector_q : std_logic_vector(3 downto 0); +signal bp_sector_qq : std_logic_vector(3 downto 0); +signal bp_module_q : std_logic_vector(3 downto 0); +signal bp_module_qq : std_logic_vector(3 downto 0); + +signal lsm_state_bits : std_logic_vector(3 downto 0); +signal reset_by_trb : std_logic; +signal global_sync_reset : std_logic; + +signal adc0_iodelay : std_logic_vector(3 downto 0); +signal adc1_iodelay : std_logic_vector(3 downto 0); + +signal cts_clk40m : std_logic; +signal cts_clk40m_locked : std_logic; +signal test_reg40m : std_logic; + +signal serious_error_flag : std_logic; +signal error_flag : std_logic; +signal warning_flag : std_logic; +signal note_flag : std_logic; + +signal broken_buf : std_logic_vector(15 downto 0); +signal next_not_configured : std_logic; +signal not_configured : std_logic; + +signal apv_error : std_logic_vector(15 downto 0); +signal next_fe_error : std_logic; +signal fe_error : std_logic; + +signal tick_10s : std_logic; + +begin + + +---------------------------------------- +-- Async reset assignment -- +---------------------------------------- +async_reset <= uc_reset; -- uC reset pin + + +---------------------------------------- +-- Reset handler / spike surpression -- +---------------------------------------- +THE_RESET_HANDLER: reset_handler +generic map ( + RESET_DELAY => x"00ff" +) +port map ( + CLEAR_IN => async_reset, + CLEAR_N_IN => '1', -- unused + CLK_IN => clk100m, + SYSCLK_IN => sysclk, + PLL_LOCKED_IN => clk100m_locked, + RESET_IN => common_ctrl_reg(3), + TRB_RESET_IN => reset_by_trb, + CLEAR_OUT => open, + RESET_OUT => global_sync_reset, + DEBUG_OUT => open +); + + +---------------------------------------- +-- Reboot handler (pulse triggered) -- +---------------------------------------- +THE_REBOOT_HANDLER: reboot_handler +port map( + RESET_IN => reset_by_trb, + CLK_IN => sysclk, + START_IN => common_ctrl_reg(15), + REBOOT_OUT => uc_reboot, + DEBUG_OUT => open +); + + +---------------------------------------- +-- 100MHz PLL -> 40MHz / 100MHz -- +---------------------------------------- +-- 100MHz PLL, generating 40MHz and phase shifted 40MHz +THE_40M_PLL: PLL_40M +port map( + CLK => clk100m, + RESET => clk40m_reset, + DPAMODE => '1', -- dynamic control + DPHASE0 => ctrl_pll(0), + DPHASE1 => ctrl_pll(1), + DPHASE2 => ctrl_pll(2), + DPHASE3 => ctrl_pll(3), + CLKOP => clk_apv, -- fixed phase, used for logic + CLKOS => clk_adc, -- phase adjustable, for ODDRXC only + LOCK => clk40m_locked +); +clk40m_reset <= ctrl_pll(7); + +-- 100MHz DLL, used for clock injection delay removal +THE_100M_DLL: dll_100m +port map( + CLK => clk100m, + RESETN => '1', + ALUHOLD => '0', + CLKOP => sysclk, + CLKOS => open, + LOCK => clk100m_locked +); + +-- 40MHz PLL, takes central clock distributed by CTS +THE_SYNC_PLL: sync_pll_40m +port map( + CLK => ext_in(3), + RESET => ctrl_pll(4), + CLKOP => cts_clk40m, + LOCK => cts_clk40m_locked +); + +THE_TEST_REG: process( cts_clk40m, cts_clk40m_locked ) +begin + if( cts_clk40m_locked = '0' ) then + test_reg40m <= '0'; + else + if( rising_edge(cts_clk40m) ) then + test_reg40m <= not test_reg40m; + end if; + end if; +end process THE_TEST_REG; + +---------------------------------------- +-- TRB endpoint -- +---------------------------------------- +THE_RICH_TRB: rich_trb +port map( + CLK100M_IN => clk100m, -- SerDes exclusive clock + SYSCLK_IN => sysclk, -- fabric clock + RESET_IN => global_sync_reset, + SD_RXD_P_IN => hdinp2, + SD_RXD_N_IN => hdinn2, + SD_TXD_P_OUT => hdoutp2, + SD_TXD_N_OUT => hdoutn2, + SD_PRESENT_IN => sd_present, + SD_TXDIS_OUT => sd_txdis, + SD_LOS_IN => sd_los, + ONEWIRE_INOUT => adcm_onewire, + -- common regIO status / control registers + COMMON_STAT_REG_IN => common_stat_reg, + COMMON_CTRL_REG_OUT => common_ctrl_reg, + -- status register input to regIO / control register output from regIO + CONTROL_OUT => simple_control, + STATUS_IN => simple_status, + -- LVL1 signals + LVL1_TRG_TYPE_OUT => lvl1_trg_type, + LVL1_TRG_RECEIVED_OUT => lvl1_trg_received, + LVL1_TRG_NUMBER_OUT => lvl1_trg_number, + LVL1_TRG_CODE_OUT => lvl1_trg_code, + LVL1_TRG_INFORMATION_OUT => lvl1_trg_information, + LVL1_ERROR_PATTERN_IN => lvl1_error_pattern, + LVL1_TRG_RELEASE_IN => lvl1_trg_release, + LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number, -- internal trigger counter + LVL1_INT_TRG_UPDATE_OUT => lvl1_int_trg_update, -- update on internal trigger counter + TIMING_TRG_FOUND_IN => timing_trg_found, + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT => ipu_number, + IPU_INFORMATION_OUT => ipu_information, + IPU_START_READOUT_OUT => ipu_start_readout, + IPU_DATA_IN => ipu_data, + IPU_DATAREADY_IN => ipu_dataready, + IPU_READOUT_FINISHED_IN => ipu_readout_finished, + IPU_READ_OUT => ipu_read, + IPU_LENGTH_IN => ipu_length, + IPU_ERROR_PATTERN_IN => ipu_error_pattern, + -- regIO bus + REGIO_ADDR_OUT => regio_addr, + REGIO_READ_ENABLE_OUT => regio_read_enable, + REGIO_WRITE_ENABLE_OUT => regio_write_enable, + REGIO_DATA_OUT => regio_data_wr, + REGIO_DATA_IN => regio_data_rd, + REGIO_DATAREADY_IN => regio_dataready, + REGIO_NO_MORE_DATA_IN => regio_no_more_data, + REGIO_WRITE_ACK_IN => regio_write_ack, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr, + REGIO_TIMEOUT_OUT => regio_timeout, + -- status LEDs + LED_LINK_STAT => fpga_led_link, + LED_LINK_TXD => fpga_led_txd, + LED_LINK_RXD => fpga_led_rxd, + LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits + RESET_OUT => reset_by_trb, + TICK_10S_OUT => tick_10s, + -- Debug + DEBUG => open --trbrich_debug +); + +-- common control register bit definitions +-- [31:24] --- +-- [23:16] fake timing trigger +-- [15] reboot FPGA +-- [14:11] --- +-- [10] reset sequence counter +-- [9:4] --- +-- [3] master reset, reset the whole endpoint +-- [2] empty IPU chain, reset IPU logic +-- [1] reset trigger logic +-- [0] reset frontends + +-- LVL1 error pattern, to be sent back to CTS with each trigger +lvl1_error_pattern(31 downto 24) <= (others => '0'); -- reserved +lvl1_error_pattern(23) <= fe_error; -- frontend error +lvl1_error_pattern(22) <= not_configured; -- not configured +lvl1_error_pattern(21) <= '0'; -- buffers almost full +lvl1_error_pattern(20) <= '0'; -- buffers half full +lvl1_error_pattern(19 downto 18) <= (others => '0'); -- reserved +lvl1_error_pattern(17) <= lvl1_trg_missing; -- missing timing trigger (done by Jan) +lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan) +lvl1_error_pattern(15 downto 0) <= (others => '0'); -- reserved for common status bits + + +---------------------------------------------- +-- mixed status and control bit definitions -- +---------------------------------------------- + +-- Common status register +-- CSR1 +common_stat_reg(63 downto 48) <= ipu_last_num(15 downto 0); -- LVL2 counter +common_stat_reg(47 downto 32) <= local_lvl1_counter; -- LVL1 counter +-- CSR0 +common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor +common_stat_reg(19 downto 14) <= (others => '0'); -- was (19 downto 13) +common_stat_reg(13) <= timing_trg_too_long; -- NOT STANDARDIZED!!!! +common_stat_reg(12) <= '0'; -- IPU: single broken event +common_stat_reg(11) <= '0'; -- IPU: severe problem +common_stat_reg(10) <= '0'; -- IPU: partially not found +common_stat_reg(9) <= ipu_error_pattern(20); -- IPU: not found +common_stat_reg(8) <= lvl1_trg_missing; -- LVL1: timing trigger missing +common_stat_reg(7) <= fe_error; -- LVL1: frontend error +common_stat_reg(6) <= not_configured; -- LVL1: not configured +common_stat_reg(5) <= '0'; -- LVL2 counter mismatch (not implemented) +common_stat_reg(4) <= '0'; -- LVL1 trigger counter mismatch (reserved) +common_stat_reg(3) <= note_flag; -- note flag +common_stat_reg(2) <= warning_flag; -- warning flag +common_stat_reg(1) <= error_flag; -- error flag +common_stat_reg(0) <= serious_error_flag; -- serious error flag + +serious_error_flag <= lvl1_trg_missing or fe_error or not_configured; +error_flag <= ipu_error_pattern(20); +warning_flag <= '0'; +note_flag <= '0'; + +-- Control register bit padding +ctrl_bithigh <= ctrl_lvl(31 downto 24) & x"0"; +ctrl_bitlow <= ctrl_lvl(23 downto 16) & x"0"; +ctrl_flathigh <= ctrl_lvl(15 downto 8) & x"0"; +ctrl_flatlow <= ctrl_lvl(7 downto 0) & x"0"; + +-- LVDS driver enable +ena_lvds(0) <= adc_on(4) or lvds_on(4); +ena_lvds(1) <= adc_on(3) or lvds_on(3); +ena_lvds(2) <= adc_on(5) or lvds_on(5); +ena_lvds(3) <= adc_on(2) or lvds_on(2); +ena_lvds(4) <= adc_on(6) or lvds_on(6); +ena_lvds(5) <= adc_on(1) or lvds_on(1); +ena_lvds(6) <= adc_on(7) or lvds_on(7); +ena_lvds(7) <= adc_on(0) or lvds_on(0); + +enb_lvds(0) <= adc_on(13) or lvds_on(13); +enb_lvds(1) <= adc_on(10) or lvds_on(10); +enb_lvds(2) <= adc_on(12) or lvds_on(12); +enb_lvds(3) <= adc_on(11) or lvds_on(11); +enb_lvds(4) <= adc_on(15) or lvds_on(15); +enb_lvds(5) <= adc_on(8) or lvds_on(8); +enb_lvds(6) <= adc_on(14) or lvds_on(14); +enb_lvds(7) <= adc_on(9) or lvds_on(9); + +bp_led <= cts_clk40m_locked; -- LED is against GND! + + +---------------------------------------- +-- internal slave bus -> slow control -- +---------------------------------------- +THE_SLAVE_BUS: slave_bus +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + -- RegIO signals + REGIO_ADDR_IN => regio_addr, + REGIO_DATA_IN => regio_data_wr, + REGIO_DATA_OUT => regio_data_rd, + REGIO_READ_ENABLE_IN => regio_read_enable, + REGIO_WRITE_ENABLE_IN => regio_write_enable, + REGIO_TIMEOUT_IN => regio_timeout, + REGIO_DATAREADY_OUT => regio_dataready, + REGIO_WRITE_ACK_OUT => regio_write_ack, + REGIO_NO_MORE_DATA_OUT => regio_no_more_data, + REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr, + -- I2C connections + SDA_IN => apv_sda_in, + SDA_OUT => apv_sda_out, + SCL_IN => apv_scl_in, + SCL_OUT => apv_scl_out, + -- 1Wire connections + ONEWIRE_START_IN => '0', -- not used yet + ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0), + ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0), + BP_ONEWIRE_INOUT => bp_onewire, + -- SPI connections + SPI_CS_OUT => u_spi_cs, + SPI_SCK_OUT => u_spi_sck, + SPI_SDI_IN => u_spi_sdo, + SPI_SDO_OUT => u_spi_sdi, + -- ADC 0 SPI connections + SPI_ADC0_CS_OUT => adc0_cs, + SPI_ADC0_SCK_OUT => adc0_sck, + SPI_ADC0_SDO_OUT => adc0_sdi, + ADC0_PLL_LOCKED_IN => adc0_valid, + ADC0_PD_OUT => adc0_powerdown, + ADC0_RST_OUT => adc0_reset, + ADC0_DEL_OUT => adc0_iodelay, + ADC0_CLK_IN => clk_apv, + ADC0_DATA_IN => adc0_testdata, + ADC0_SEL_OUT => adc0_select, + APV0_RST_OUT => apv0_reset, + -- ADC 0 SPI connections + SPI_ADC1_CS_OUT => adc1_cs, + SPI_ADC1_SCK_OUT => adc1_sck, + SPI_ADC1_SDO_OUT => adc1_sdi, + ADC1_PLL_LOCKED_IN => adc1_valid, + ADC1_PD_OUT => adc1_powerdown, + ADC1_RST_OUT => adc1_reset, + ADC1_DEL_OUT => adc1_iodelay, + ADC1_CLK_IN => clk_apv, + ADC1_DATA_IN => adc1_testdata, + ADC1_SEL_OUT => adc1_select, + APV1_RST_OUT => apv1_reset, + -- backplane identifier + BACKPLANE_IN => bp_module_qq(2 downto 0), + -- pedestal interface + PED_ADDR_IN => buf_addr, + PED_DATA_0_OUT => ped_data(0), + PED_DATA_1_OUT => ped_data(1), + PED_DATA_2_OUT => ped_data(2), + PED_DATA_3_OUT => ped_data(3), + PED_DATA_4_OUT => ped_data(4), + PED_DATA_5_OUT => ped_data(5), + PED_DATA_6_OUT => ped_data(6), + PED_DATA_7_OUT => ped_data(7), + PED_DATA_8_OUT => ped_data(8), + PED_DATA_9_OUT => ped_data(9), + PED_DATA_10_OUT => ped_data(10), + PED_DATA_11_OUT => ped_data(11), + PED_DATA_12_OUT => ped_data(12), + PED_DATA_13_OUT => ped_data(13), + PED_DATA_14_OUT => ped_data(14), + PED_DATA_15_OUT => ped_data(15), + -- threshold interface + THR_ADDR_IN => thr_addr, + THR_DATA_0_OUT => thr_data(0), + THR_DATA_1_OUT => thr_data(1), + THR_DATA_2_OUT => thr_data(2), + THR_DATA_3_OUT => thr_data(3), + THR_DATA_4_OUT => thr_data(4), + THR_DATA_5_OUT => thr_data(5), + THR_DATA_6_OUT => thr_data(6), + THR_DATA_7_OUT => thr_data(7), + THR_DATA_8_OUT => thr_data(8), + THR_DATA_9_OUT => thr_data(9), + THR_DATA_10_OUT => thr_data(10), + THR_DATA_11_OUT => thr_data(11), + THR_DATA_12_OUT => thr_data(12), + THR_DATA_13_OUT => thr_data(13), + THR_DATA_14_OUT => thr_data(14), + THR_DATA_15_OUT => thr_data(15), + -- APV control / status + CTRL_0_OUT => adc_ctrl_reg(0), + CTRL_1_OUT => adc_ctrl_reg(1), + CTRL_2_OUT => adc_ctrl_reg(2), + CTRL_3_OUT => adc_ctrl_reg(3), + CTRL_4_OUT => adc_ctrl_reg(4), + CTRL_5_OUT => adc_ctrl_reg(5), + CTRL_6_OUT => adc_ctrl_reg(6), + CTRL_7_OUT => adc_ctrl_reg(7), + CTRL_8_OUT => adc_ctrl_reg(8), + CTRL_9_OUT => adc_ctrl_reg(9), + CTRL_10_OUT => adc_ctrl_reg(10), + CTRL_11_OUT => adc_ctrl_reg(11), + CTRL_12_OUT => adc_ctrl_reg(12), + CTRL_13_OUT => adc_ctrl_reg(13), + CTRL_14_OUT => adc_ctrl_reg(14), + CTRL_15_OUT => adc_ctrl_reg(15), + STAT_0_IN => adc_stat_reg(0), + STAT_1_IN => adc_stat_reg(1), + STAT_2_IN => adc_stat_reg(2), + STAT_3_IN => adc_stat_reg(3), + STAT_4_IN => adc_stat_reg(4), + STAT_5_IN => adc_stat_reg(5), + STAT_6_IN => adc_stat_reg(6), + STAT_7_IN => adc_stat_reg(7), + STAT_8_IN => adc_stat_reg(8), + STAT_9_IN => adc_stat_reg(9), + STAT_10_IN => adc_stat_reg(10), + STAT_11_IN => adc_stat_reg(11), + STAT_12_IN => adc_stat_reg(12), + STAT_13_IN => adc_stat_reg(13), + STAT_14_IN => adc_stat_reg(14), + STAT_15_IN => adc_stat_reg(15), + -- FIFO status + FIFO_STATUS_0_IN => fifo_status(0), + FIFO_STATUS_1_IN => fifo_status(1), + FIFO_STATUS_2_IN => fifo_status(2), + FIFO_STATUS_3_IN => fifo_status(3), + FIFO_STATUS_4_IN => fifo_status(4), + FIFO_STATUS_5_IN => fifo_status(5), + FIFO_STATUS_6_IN => fifo_status(6), + FIFO_STATUS_7_IN => fifo_status(7), + FIFO_STATUS_8_IN => fifo_status(8), + FIFO_STATUS_9_IN => fifo_status(9), + FIFO_STATUS_10_IN => fifo_status(10), + FIFO_STATUS_11_IN => fifo_status(11), + FIFO_STATUS_12_IN => fifo_status(12), + FIFO_STATUS_13_IN => fifo_status(13), + FIFO_STATUS_14_IN => fifo_status(14), + FIFO_STATUS_15_IN => fifo_status(15), + IPU_STATUS_IN => ipu_handler_status, + RELEASE_STATUS_IN => lvl1_release_status, + -- some control signals + CTRL_LVL_OUT => ctrl_lvl, + CTRL_TRG_OUT => ctrl_trg, + CTRL_PLL_OUT => ctrl_pll, + STATUS_PLL_IN => status_pll, + -- temporary stuff + TEST_REG_IN => test_reg, -- short cut + TEST_REG_OUT => test_reg, + -- Debug + DEBUG_OUT => open, --slave_debug, + STAT => open +); + +-- PLL status register +status_pll(15) <= clk100m_locked; +status_pll(14) <= clk40m_locked; +status_pll(13) <= adc1_valid; +status_pll(12) <= adc0_valid; +status_pll(11) <= adc1_swap; +status_pll(10) <= adc0_swap; +status_pll(9) <= test_reg40m; --'0'; +status_pll(8) <= cts_clk40m_locked; +status_pll(7) <= '0'; -- make it human readable +status_pll(6 downto 4) <= bp_sector_qq(2 downto 0); -- given by backplane DIP switch, for readback only +status_pll(3) <= '0'; -- make it human readable +status_pll(2 downto 0) <= bp_module_qq(2 downto 0); -- given by backplane DIP switch, for readback only + +-- Common status register, do not use. +simple_status(127 downto 104) <= (others => '0'); +simple_status(103 downto 96) <= trgctrl_debug(39 downto 32); +simple_status(95 downto 64) <= trgctrl_debug(31 downto 0); +simple_status(63 downto 32) <= (others => '0'); +simple_status(31 downto 16) <= local_lvl2_counter; +simple_status(15 downto 0) <= local_lvl1_counter; + +-- all APVs are reset together, including the common FE reset +THE_APV_PULSE_STRETCH: pulse_stretch +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + START_IN => common_ctrl_reg(0), + PULSE_OUT => frontend_reset, + DEBUG_OUT => open +); + +apv_reset <= apv0_reset or apv1_reset or frontend_reset; + +-- APV status registers +-- "ADC on" bits +-- "LVDS ON" bits +GEN_ADC_LVDS_ON: for i in 0 to 15 generate + adc_on(i) <= adc_ctrl_reg(i)(0); + lvds_on(i) <= adc_ctrl_reg(i)(1); + adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4)); + broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit + apv_error(i) <= buf_data(i)(26); -- APV error frame bit +end generate GEN_ADC_LVDS_ON; + +next_not_configured <= '1' when (broken_buf /= x"0000") else '0'; +next_fe_error <= '1' when (apv_error /= x"0000") else '0'; + +---------------------------------------- +-- IPU endpoint for data transport -- +---------------------------------------- +THE_IPU_STAGE: ipu_fifo_stage +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + IPU_RESET_IN => common_ctrl_reg(2), + -- Slow control signals + SECTOR_IN => bp_sector_qq(2 downto 0), + MODULE_IN => bp_module_qq(2 downto 0), + -- IPU channel connections + IPU_NUMBER_IN => ipu_number, + IPU_INFORMATION_IN => ipu_information, + IPU_START_READOUT_IN => ipu_start_readout, + IPU_DATA_OUT => ipu_data, + IPU_DATAREADY_OUT => ipu_dataready, + IPU_READOUT_FINISHED_OUT => ipu_readout_finished, + IPU_READ_IN => ipu_read, + IPU_LENGTH_OUT => ipu_length, + IPU_ERROR_PATTERN_OUT => ipu_error_pattern, + IPU_LAST_NUM_OUT => ipu_last_num, + LVL2_COUNTER_OUT => local_lvl2_counter, + -- DHDR buffer input + DHDR_DATA_IN => dhdr_data, + DHDR_LENGTH_IN => dhdr_length, + DHDR_STORE_IN => dhdr_store, + DHDR_BUF_FULL_OUT => dhdr_buf_full, + -- processed data input + FIFO_SPACE_REQ_IN => fifo_space_req, + FIFO_START_IN => fifo_start, + FIFO_0_DATA_IN => fifo_data(0), + FIFO_1_DATA_IN => fifo_data(1), + FIFO_2_DATA_IN => fifo_data(2), + FIFO_3_DATA_IN => fifo_data(3), + FIFO_4_DATA_IN => fifo_data(4), + FIFO_5_DATA_IN => fifo_data(5), + FIFO_6_DATA_IN => fifo_data(6), + FIFO_7_DATA_IN => fifo_data(7), + FIFO_8_DATA_IN => fifo_data(8), + FIFO_9_DATA_IN => fifo_data(9), + FIFO_10_DATA_IN => fifo_data(10), + FIFO_11_DATA_IN => fifo_data(11), + FIFO_12_DATA_IN => fifo_data(12), + FIFO_13_DATA_IN => fifo_data(13), + FIFO_14_DATA_IN => fifo_data(14), + FIFO_15_DATA_IN => fifo_data(15), + FIFO_WE_IN => fifo_we, + FIFO_DONE_IN => fifo_done, + FIFO_0_STATUS_OUT => fifo_status(0), + FIFO_1_STATUS_OUT => fifo_status(1), + FIFO_2_STATUS_OUT => fifo_status(2), + FIFO_3_STATUS_OUT => fifo_status(3), + FIFO_4_STATUS_OUT => fifo_status(4), + FIFO_5_STATUS_OUT => fifo_status(5), + FIFO_6_STATUS_OUT => fifo_status(6), + FIFO_7_STATUS_OUT => fifo_status(7), + FIFO_8_STATUS_OUT => fifo_status(8), + FIFO_9_STATUS_OUT => fifo_status(9), + FIFO_10_STATUS_OUT => fifo_status(10), + FIFO_11_STATUS_OUT => fifo_status(11), + FIFO_12_STATUS_OUT => fifo_status(12), + FIFO_13_STATUS_OUT => fifo_status(13), + FIFO_14_STATUS_OUT => fifo_status(14), + FIFO_15_STATUS_OUT => fifo_status(15), + IPU_STATUS_OUT => ipu_handler_status, + RELEASE_STATUS_OUT => lvl1_release_status, + -- Debug signals + DBG_BSM_OUT => open, + DBG_OUT => open --fifo_debug +); + + +---------------------------------------- +-- Data processing unit -- +---------------------------------------- +THE_PED_CORR_STAGE: ped_corr_ctrl +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + VERBOSE_IN => common_ctrl_reg(94), -- CCR2-30 + EDS_DATA_IN => eds_data, + EDS_AVAIL_IN => eds_avail, + EDS_DONE_OUT => eds_done, + -- DHDR information -- to next stage + DHDR_DATA_OUT => dhdr_data, + DHDR_LENGTH_OUT => dhdr_length, + DHDR_STORE_OUT => dhdr_store, + DHDR_BUF_FULL_IN => dhdr_buf_full, + FIFO_SPACE_REQ_OUT => fifo_space_req, + -- data buffers -- from raw_buf_stage + BUF_ADDR_OUT => buf_addr, + BUF_DONE_OUT => buf_done, + BUF_TICK_IN => buf_tick, + BUF_START_IN => buf_start, + -- raw data + BUF_0_DATA_IN => buf_data(0), + BUF_1_DATA_IN => buf_data(1), + BUF_2_DATA_IN => buf_data(2), + BUF_3_DATA_IN => buf_data(3), + BUF_4_DATA_IN => buf_data(4), + BUF_5_DATA_IN => buf_data(5), + BUF_6_DATA_IN => buf_data(6), + BUF_7_DATA_IN => buf_data(7), + BUF_8_DATA_IN => buf_data(8), + BUF_9_DATA_IN => buf_data(9), + BUF_10_DATA_IN => buf_data(10), + BUF_11_DATA_IN => buf_data(11), + BUF_12_DATA_IN => buf_data(12), + BUF_13_DATA_IN => buf_data(13), + BUF_14_DATA_IN => buf_data(14), + BUF_15_DATA_IN => buf_data(15), + -- Pedestal data + PED_ADDR_OUT => open, -- BUGBUGBUG + PED_0_DATA_IN => ped_data(0), + PED_1_DATA_IN => ped_data(1), + PED_2_DATA_IN => ped_data(2), + PED_3_DATA_IN => ped_data(3), + PED_4_DATA_IN => ped_data(4), + PED_5_DATA_IN => ped_data(5), + PED_6_DATA_IN => ped_data(6), + PED_7_DATA_IN => ped_data(7), + PED_8_DATA_IN => ped_data(8), + PED_9_DATA_IN => ped_data(9), + PED_10_DATA_IN => ped_data(10), + PED_11_DATA_IN => ped_data(11), + PED_12_DATA_IN => ped_data(12), + PED_13_DATA_IN => ped_data(13), + PED_14_DATA_IN => ped_data(14), + PED_15_DATA_IN => ped_data(15), + -- Threshold data + THR_ADDR_OUT => thr_addr, + THR_0_DATA_IN => thr_data(0), + THR_1_DATA_IN => thr_data(1), + THR_2_DATA_IN => thr_data(2), + THR_3_DATA_IN => thr_data(3), + THR_4_DATA_IN => thr_data(4), + THR_5_DATA_IN => thr_data(5), + THR_6_DATA_IN => thr_data(6), + THR_7_DATA_IN => thr_data(7), + THR_8_DATA_IN => thr_data(8), + THR_9_DATA_IN => thr_data(9), + THR_10_DATA_IN => thr_data(10), + THR_11_DATA_IN => thr_data(11), + THR_12_DATA_IN => thr_data(12), + THR_13_DATA_IN => thr_data(13), + THR_14_DATA_IN => thr_data(14), + THR_15_DATA_IN => thr_data(15), + -- processed data + FIFO_START_OUT => fifo_start, + FIFO_0_DATA_OUT => fifo_data(0), + FIFO_1_DATA_OUT => fifo_data(1), + FIFO_2_DATA_OUT => fifo_data(2), + FIFO_3_DATA_OUT => fifo_data(3), + FIFO_4_DATA_OUT => fifo_data(4), + FIFO_5_DATA_OUT => fifo_data(5), + FIFO_6_DATA_OUT => fifo_data(6), + FIFO_7_DATA_OUT => fifo_data(7), + FIFO_8_DATA_OUT => fifo_data(8), + FIFO_9_DATA_OUT => fifo_data(9), + FIFO_10_DATA_OUT => fifo_data(10), + FIFO_11_DATA_OUT => fifo_data(11), + FIFO_12_DATA_OUT => fifo_data(12), + FIFO_13_DATA_OUT => fifo_data(13), + FIFO_14_DATA_OUT => fifo_data(14), + FIFO_15_DATA_OUT => fifo_data(15), + FIFO_WE_OUT => fifo_we, + FIFO_DONE_OUT => fifo_done, + -- Debug signals + DBG_BSM_OUT => open, + DBG_OUT => open +); + + +------------------------------------------ +-- Raw data processing and storage unit -- +------------------------------------------ +THE_RAW_BUF_STAGE: raw_buf_stage +port map( + CLK_IN => sysclk, + CLK_APV_IN => clk_apv, + RESET_IN => reset_by_trb, + -- trigger related signals + APV_RESET_IN => apv_reset, -- (100MHz clock) + APV_SYNC_IN => apv_sync, -- (40MHz APV clock) + APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock) + -- ADC0 signals + ADC0_VALID_IN => adc0_valid, + ADC0_0_DATA_IN => adc_data(0), + ADC0_1_DATA_IN => adc_data(1), + ADC0_2_DATA_IN => adc_data(2), + ADC0_3_DATA_IN => adc_data(3), + ADC0_4_DATA_IN => adc_data(4), + ADC0_5_DATA_IN => adc_data(5), + ADC0_6_DATA_IN => adc_data(6), + ADC0_7_DATA_IN => adc_data(7), + -- ADC1 signals + ADC1_VALID_IN => adc1_valid, + ADC1_0_DATA_IN => adc_data(8), + ADC1_1_DATA_IN => adc_data(9), + ADC1_2_DATA_IN => adc_data(10), + ADC1_3_DATA_IN => adc_data(11), + ADC1_4_DATA_IN => adc_data(12), + ADC1_5_DATA_IN => adc_data(13), + ADC1_6_DATA_IN => adc_data(14), + ADC1_7_DATA_IN => adc_data(15), + -- Slow control registers + MAX_TRG_NUM_IN => maximum_trg, -- automatically determined + BIT_LOW_IN => ctrl_bitlow, -- from slow control + BIT_HIGH_IN => ctrl_bithigh, -- from slow control + FL_LOW_IN => ctrl_flatlow, -- from slow control + FL_HIGH_IN => ctrl_flathigh, -- from slow control + APV_ON_IN => adc_on, + -- 100MHZ synchronous interface + -- APV raw buffers + BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW + BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl + BUF_DONE_IN => buf_done, -- from ped_corr_ctrl + BUF_TICK_OUT => buf_tick, + BUF_START_OUT => buf_start, + BUF_READY_OUT => buf_ready, + BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl + BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl + BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl + BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl + BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl + BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl + BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl + BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl + BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl + BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl + BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl + BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl + BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl + BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl + BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl + BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl + -- Debug signals + DEBUG_OUT => raw_buf_debug --open +); + + +---------------------------------------- +-- ADC1 data handler -- +---------------------------------------- +THE_ADC1_HANDLER: adc_data_handler +port map( + RESET_IN => reset_by_trb, + ADC_LCLK_IN => adc1_lclk, + ADC_ADCLK_IN => adc1_adclk, + ADC_CHNL_IN => adc1_out, + PLL_CTRL_IN => adc1_iodelay, + ADC_DATA7_OUT => adc_raw_data(15), + ADC_DATA6_OUT => adc_raw_data(14), + ADC_DATA5_OUT => adc_raw_data(13), + ADC_DATA4_OUT => adc_raw_data(12), + ADC_DATA3_OUT => adc_raw_data(11), + ADC_DATA2_OUT => adc_raw_data(10), + ADC_DATA1_OUT => adc_raw_data(9), + ADC_DATA0_OUT => adc_raw_data(8), + ADC_CE_OUT => adc1_ce, + ADC_VALID_OUT => adc1_valid, + ADC_SWAP_OUT => adc1_swap, + DEBUG_OUT => open +); + + +---------------------------------------- +-- ADC1 clock domain crossover -- +---------------------------------------- +THE_ADC1_CROSSOVER: adc_crossover +port map( + CLK_APV_IN => clk_apv, + RESET_IN => global_sync_reset, + -- ADC clock domain signals + ADC_CLK_IN => adc1_lclk, + ADC_CE_IN => adc1_ce, + ADC_DATA_VALID_IN => adc1_valid, + ADC_DATA_7_IN => adc_raw_data(15), + ADC_DATA_6_IN => adc_raw_data(14), + ADC_DATA_5_IN => adc_raw_data(13), + ADC_DATA_4_IN => adc_raw_data(12), + ADC_DATA_3_IN => adc_raw_data(11), + ADC_DATA_2_IN => adc_raw_data(10), + ADC_DATA_1_IN => adc_raw_data(9), + ADC_DATA_0_IN => adc_raw_data(8), + LEVEL_WR_OUT => open, + -- APV clock domain signals + APV_DATA_7_OUT => adc_data(15), + APV_DATA_6_OUT => adc_data(14), + APV_DATA_5_OUT => adc_data(13), + APV_DATA_4_OUT => adc_data(12), + APV_DATA_3_OUT => adc_data(11), + APV_DATA_2_OUT => adc_data(10), + APV_DATA_1_OUT => adc_data(9), + APV_DATA_0_OUT => adc_data(8), + APV_DATA_VALID_OUT => open, + LEVEL_RD_OUT => open, + -- Debug signals + DEBUG_OUT => open +); + + +---------------------------------------- +-- ADC1 test data multiplexer -- +---------------------------------------- +THE_ADC_1_SELECT: adc_channel_select +port map( + RESET_IN => reset_by_trb, + ADC_CLK_IN => clk_apv, + ADC_SEL_IN => adc1_select, + ADC_7_IN => adc_data(15), + ADC_6_IN => adc_data(14), + ADC_5_IN => adc_data(13), + ADC_4_IN => adc_data(12), + ADC_3_IN => adc_data(11), + ADC_2_IN => adc_data(10), + ADC_1_IN => adc_data(9), + ADC_0_IN => adc_data(8), + ADC_CH_OUT => adc1_testdata, + DEBUG_OUT => open +); + + +---------------------------------------- +-- ADC0 data handler -- +---------------------------------------- +THE_ADC0_HANDLER: adc_data_handler +port map( + RESET_IN => reset_by_trb, + ADC_LCLK_IN => adc0_lclk, + ADC_ADCLK_IN => adc0_adclk, + ADC_CHNL_IN => adc0_out, + PLL_CTRL_IN => adc0_iodelay, + ADC_DATA7_OUT => adc_raw_data(7), + ADC_DATA6_OUT => adc_raw_data(6), + ADC_DATA5_OUT => adc_raw_data(5), + ADC_DATA4_OUT => adc_raw_data(4), + ADC_DATA3_OUT => adc_raw_data(3), + ADC_DATA2_OUT => adc_raw_data(2), + ADC_DATA1_OUT => adc_raw_data(1), + ADC_DATA0_OUT => adc_raw_data(0), + ADC_CE_OUT => adc0_ce, + ADC_VALID_OUT => adc0_valid, + ADC_SWAP_OUT => adc0_swap, + DEBUG_OUT => open +); + + +---------------------------------------- +-- ADC0 clock domain crossover -- +---------------------------------------- +THE_ADC0_CROSSOVER: adc_crossover +port map( + CLK_APV_IN => clk_apv, + RESET_IN => global_sync_reset, + -- ADC clock domain signals + ADC_CLK_IN => adc0_lclk, + ADC_CE_IN => adc0_ce, + ADC_DATA_VALID_IN => adc0_valid, + ADC_DATA_7_IN => adc_raw_data(7), + ADC_DATA_6_IN => adc_raw_data(6), + ADC_DATA_5_IN => adc_raw_data(5), + ADC_DATA_4_IN => adc_raw_data(4), + ADC_DATA_3_IN => adc_raw_data(3), + ADC_DATA_2_IN => adc_raw_data(2), + ADC_DATA_1_IN => adc_raw_data(1), + ADC_DATA_0_IN => adc_raw_data(0), + LEVEL_WR_OUT => open, + -- APV clock domain signals + APV_DATA_7_OUT => adc_data(7), + APV_DATA_6_OUT => adc_data(6), + APV_DATA_5_OUT => adc_data(5), + APV_DATA_4_OUT => adc_data(4), + APV_DATA_3_OUT => adc_data(3), + APV_DATA_2_OUT => adc_data(2), + APV_DATA_1_OUT => adc_data(1), + APV_DATA_0_OUT => adc_data(0), + APV_DATA_VALID_OUT => open, + LEVEL_RD_OUT => open, + -- Debug signals + DEBUG_OUT => open +); + + +---------------------------------------- +-- ADC0 test data multiplexer -- +---------------------------------------- +THE_ADC_0_SELECT: adc_channel_select +port map( + RESET_IN => reset_by_trb, + ADC_CLK_IN => clk_apv, + ADC_SEL_IN => adc0_select, + ADC_7_IN => adc_data(7), + ADC_6_IN => adc_data(6), + ADC_5_IN => adc_data(5), + ADC_4_IN => adc_data(4), + ADC_3_IN => adc_data(3), + ADC_2_IN => adc_data(2), + ADC_1_IN => adc_data(1), + ADC_0_IN => adc_data(0), + ADC_CH_OUT => adc0_testdata, + DEBUG_OUT => open +); + + +---------------------------------------- +-- Trigger handler (APV specific) -- +---------------------------------------- +THE_APV_TRGCTRL: apv_trgctrl +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + CLK_APV_IN => clk_apv, + -- Triggers + SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse + TIME_TRG_IN => ext_in, -- external trigger inputs + TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers + STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers. + TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint + TRG_TOO_LONG_OUT => timing_trg_too_long, -- only for TRG0 channel + SECTOR_IN => bp_sector_qq(2 downto 0), + -- slow control settings + TRG_MAX_OUT => maximum_trg, + TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control + TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control + TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control + TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control + TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control + TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control + TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control + TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control + TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control + -- TRB LVL1 signals + TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint + TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint + TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint + TRB_TINFO_IN => lvl1_trg_information, -- from TRB LVL1 endpoint + TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint + TRB_MISSING_OUT => lvl1_trg_missing, -- missing timing trigger + TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint + TRB_COUNTER_OUT => local_lvl1_counter, -- own trigger counter + TRB_COUNTER_IN => lvl1_int_trg_number, -- official TRB trigger counter + TRB_LD_COUNTER_IN => lvl1_int_trg_update, -- load TRB counter value + -- EDS signals + EDS_DATA_OUT => eds_data, -- to ped_corr_stage + EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage + EDS_DONE_IN => eds_done, -- from ped_corr_stage + EDS_FULL_OUT => eds_buf_full, + EDS_LEVEL_OUT => eds_buf_level, + FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock) + -- APV signals + APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock) + APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock) + DEBUG_OUT => trgctrl_debug +); + + +---------------------------------------- +-- ADC signals -- +---------------------------------------- +adc1_rst <= adc1_reset; +adc1_pd <= adc1_powerdown; + +THE_ADC1CLK_OUT: ODDRXC +port map( + DA => '1', + DB => '0', + CLK => clk_adc, + RST => '0', + Q => adc1_clk +); + +adc0_rst <= adc0_reset; +adc0_pd <= adc0_powerdown; + +THE_ADC0CLK_OUT: ODDRXC +port map( + DA => '1', + DB => '0', + CLK => clk_adc, + RST => '0', + Q => adc0_clk +); + + +---------------------------------------- +-- APV signals -- +---------------------------------------- +-- SDA line output +apv0_sda <= '0' when (apv_sda_out = '0') else 'Z'; +apv1_sda <= '0' when (apv_sda_out = '0') else 'Z'; +-- SDA line input (wired OR negative logic) +apv_sda_in <= apv0_sda and apv1_sda; + +-- SCL line output +apv0_scl <= '0' when (apv_scl_out = '0') else 'Z'; +apv1_scl <= '0' when (apv_scl_out = '0') else 'Z'; +-- SCL line input (wired OR negative logic) +apv_scl_in <= apv0_scl and apv1_scl; + +-- Reset signal with correct polarity +apv0_rst <= not apv_reset; +apv1_rst <= not apv_reset; + +-- CLK and TRG signal +-- CLK is shifted to meet timing constraints of APV +THE_APV0ACLK_OUT: ODDRXC +port map( + DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv0a_clk +); + +THE_APV0BCLK_OUT: ODDRXC +port map( + DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv0b_clk +); + +THE_APV1ACLK_OUT: ODDRXC +port map( + DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv1a_clk +); + +THE_APV1BCLK_OUT: ODDRXC +port map( + DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv1b_clk +); + +THE_APV0ATRG_OUT: ODDRXC +port map( + DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv0a_trg +); +THE_APV0BTRG_OUT: ODDRXC +port map( + DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv0b_trg +); +THE_APV1ATRG_OUT: ODDRXC +port map( + DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv1a_trg +); +THE_APV1BTRG_OUT: ODDRXC +port map( + DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv1b_trg +); + + +---------------------------------------- +-- DIP switch input registers -- +---------------------------------------- +-- switch "OFF" => '1', switch "ON" => '0'; so invert it +THE_SYNC_PROC: process( sysclk ) +begin + if( rising_edge(sysclk) ) then + bp_module_qq <= bp_module_q; + bp_module_q <= not bp_module; + bp_sector_qq <= bp_sector_q; + bp_sector_q <= not bp_sector; + not_configured <= next_not_configured; -- status bit + fe_error <= next_fe_error; -- status bit + end if; +end process THE_SYNC_PROC; + + +---------------------------------------- +-- LED drivers -- +---------------------------------------- +fpga_led_adc(1) <= not adc1_valid; +fpga_led_adc(0) <= not adc0_valid; +fpga_led(6) <= not lsm_state_bits(0); -- LED "0" +fpga_led(5) <= not lsm_state_bits(1); -- LED "1" +fpga_led(4) <= not lsm_state_bits(2); -- LED "2" +fpga_led(3) <= not lsm_state_bits(3); -- LED "3" +fpga_led_pll <= not clk40m_locked; + + +---------------------------------------- +-- FPGA debug header driver -- +---------------------------------------- + +-- NOT USED, USE EPIC EDITOR INSTEAD! + +------------------------------------------------------------------ +-- ORIGINAL STUFF +------------------------------------------------------------------ +--debug(42 downto 39) <= (others => '0'); +---- IPU signals +--debug(38 downto 35) <= ipu_number(3 downto 0); +--debug(34) <= ipu_start_readout; +--debug(33) <= ipu_dataready; +--debug(32) <= ipu_read; +--debug(31) <= ipu_readout_finished; +---- FIFO signals +--debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage) +--debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0) +--debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs +--debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU +--debug(26) <= dhdr_buf_full; -- ipu_stage -> +---- EventDataSheet / buffer signals +--debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed +--debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks +--debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last +--debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start +--debug(21 downto 17) <= buf_data(0)(34 downto 30); +--debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full +--debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry +--debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available +--debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full +--debug(12 downto 8) <= eds_buf_level; +---- timing trigger signals +--debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived +--debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived +--debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found +--debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy +--debug(3 downto 0) <= lvl1_trg_number(3 downto 0); + + +---------------------------------------- +-- "unused" pins -- +---------------------------------------- + +end adcmv3; diff --git a/source/adcmv3_components.vhd b/design/adcmv3_components.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/adcmv3_components.vhd rename to design/adcmv3_components.vhd diff --git a/design/adcmv3_components.vhd~ b/design/adcmv3_components.vhd~ new file mode 100755 index 0000000..df71455 --- /dev/null +++ b/design/adcmv3_components.vhd~ @@ -0,0 +1,1688 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.ALL; +--use IEEE.numeric_std.ALL; +--use IEEE.std_logic_UNSIGNED.ALL; + + +package adcmv3_components is + +component dbg_reg is +generic( + WIDTH : integer := 1 +); +port( + DEBUG_IN : in std_logic_vector(WIDTH-1 downto 0); + DEBUG_OUT : out std_logic_vector(WIDTH-1 downto 0) +); +end component dbg_reg; + +component reset_handler is +generic( + RESET_DELAY : std_logic_vector(15 downto 0) := x"1fff" +); +port( + CLEAR_IN : in std_logic; -- reset input (high active, async) + CLEAR_N_IN : in std_logic; -- reset input (low active, async) + CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN : in std_logic; -- PLL/DLL remastered clock + PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async) + RESET_IN : in std_logic; -- general reset signal (SYSCLK) + TRB_RESET_IN : in std_logic; -- TRBnet reset signal (SYSCLK) + CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE! + RESET_OUT : out std_logic; -- synchronous reset out (SYSCLK) + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component reset_handler; + +component sync_pll_40m is +port( + CLK : in std_logic; + RESET : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic +); +end component sync_pll_40m; + +component raw_buf_stage is +port( + CLK_IN : in std_logic; -- 100MHz local clock + CLK_APV_IN : in std_logic; -- 40MHz APV clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- trigger related signals + APV_RESET_IN : in std_logic; -- APV reset signal (100MHz) + APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz) + APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz) + -- ADC0 signals + ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0 + ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1 + ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2 + ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3 + ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4 + ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5 + ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6 + ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7 + -- ADC1 signals + ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0 + ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1 + ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2 + ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3 + ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4 + ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5 + ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6 + ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7 + -- Slow control registers + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold + FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold + APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control + -- 100MHZ synchronous interface + -- APV raw buffers + BUF_FULL_OUT : out std_logic; + BUF_ADDR_IN : in std_logic_vector(6 downto 0); + BUF_DONE_IN : in std_logic; + BUF_TICK_OUT : out std_logic_vector(15 downto 0); + BUF_START_OUT : out std_logic_vector(15 downto 0); + BUF_READY_OUT : out std_logic_vector(15 downto 0); + BUF_0_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_1_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_2_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_3_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_4_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_5_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_6_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_7_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_8_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_9_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_10_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_11_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_12_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_13_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_14_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_15_DATA_OUT : out std_logic_vector(37 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component raw_buf_stage; + +component adc_data_handler is +port( + RESET_IN : in std_logic; + ADC_LCLK_IN : in std_logic; -- LCLK from ADC + ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC + ADC_CHNL_IN : in std_logic_vector(7 downto 0); + PLL_CTRL_IN : in std_logic_vector(3 downto 0); + ADC_DATA7_OUT : out std_logic_vector(11 downto 0); + ADC_DATA6_OUT : out std_logic_vector(11 downto 0); + ADC_DATA5_OUT : out std_logic_vector(11 downto 0); + ADC_DATA4_OUT : out std_logic_vector(11 downto 0); + ADC_DATA3_OUT : out std_logic_vector(11 downto 0); + ADC_DATA2_OUT : out std_logic_vector(11 downto 0); + ADC_DATA1_OUT : out std_logic_vector(11 downto 0); + ADC_DATA0_OUT : out std_logic_vector(11 downto 0); + ADC_CE_OUT : out std_logic; + ADC_VALID_OUT : out std_logic; + ADC_SWAP_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component adc_data_handler; + +component adc_crossover is +port( + CLK_APV_IN : in std_logic; -- APV 40MHz local clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- ADC clock domain signals + ADC_CLK_IN : in std_logic; + ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse... + ADC_DATA_VALID_IN : in std_logic; + ADC_DATA_7_IN : in std_logic_vector(11 downto 0); + ADC_DATA_6_IN : in std_logic_vector(11 downto 0); + ADC_DATA_5_IN : in std_logic_vector(11 downto 0); + ADC_DATA_4_IN : in std_logic_vector(11 downto 0); + ADC_DATA_3_IN : in std_logic_vector(11 downto 0); + ADC_DATA_2_IN : in std_logic_vector(11 downto 0); + ADC_DATA_1_IN : in std_logic_vector(11 downto 0); + ADC_DATA_0_IN : in std_logic_vector(11 downto 0); + LEVEL_WR_OUT : out std_logic_vector(4 downto 0); + -- APV clock domain signals + APV_DATA_7_OUT : out std_logic_vector(11 downto 0); + APV_DATA_6_OUT : out std_logic_vector(11 downto 0); + APV_DATA_5_OUT : out std_logic_vector(11 downto 0); + APV_DATA_4_OUT : out std_logic_vector(11 downto 0); + APV_DATA_3_OUT : out std_logic_vector(11 downto 0); + APV_DATA_2_OUT : out std_logic_vector(11 downto 0); + APV_DATA_1_OUT : out std_logic_vector(11 downto 0); + APV_DATA_0_OUT : out std_logic_vector(11 downto 0); + APV_DATA_VALID_OUT : out std_logic; + LEVEL_RD_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component adc_crossover; + +component crossover is +port( + DATA : in std_logic_vector(95 downto 0); + WRCLOCK : in std_logic; + RDCLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; -- asynchronous reset! + RPRESET : in std_logic; + Q : out std_logic_vector(95 downto 0); + WCNT : out std_logic_vector(4 downto 0); + RCNT : out std_logic_vector(4 downto 0); + EMPTY : out std_logic; + FULL : out std_logic +); +end component crossover; + +component slv_adc_la is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_adc_la; + +-- NOT USED YET +component logic_analyzer is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- control signals + ARM_IN : in std_logic; -- arm the machine + TRG_IN : in std_logic; -- trigger the data acquisition + MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); + -- status signals + SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses + SM_CE_OUT : out std_logic; + SM_WE_OUT : out std_logic; -- write enable for sample RAM + CLEAR_OUT : out std_logic; -- sample memory is being cleared + RUN_OUT : out std_logic; -- ready for trigger + SAMPLE_OUT : out std_logic; -- data acquisition running + READY_OUT : out std_logic; -- data acquisition is finished + LAST_OUT : out std_logic; -- last data word of sampling + -- Status lines + BSM_OUT : out std_logic_vector(3 downto 0); + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component logic_analyzer; + +component onewire_spare_one is +port( + ADDRESS : in std_logic_vector(2 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component onewire_spare_one; + +component adc_onewire_map_mem is +port( + ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component adc_onewire_map_mem; + +component adc_channel_select is +port( + RESET_IN : in std_logic; + ADC_CLK_IN : in std_logic; + ADC_SEL_IN : in std_logic_vector(2 downto 0); + ADC_7_IN : in std_logic_vector(11 downto 0); + ADC_6_IN : in std_logic_vector(11 downto 0); + ADC_5_IN : in std_logic_vector(11 downto 0); + ADC_4_IN : in std_logic_vector(11 downto 0); + ADC_3_IN : in std_logic_vector(11 downto 0); + ADC_2_IN : in std_logic_vector(11 downto 0); + ADC_1_IN : in std_logic_vector(11 downto 0); + ADC_0_IN : in std_logic_vector(11 downto 0); + ADC_CH_OUT : out std_logic_vector(11 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component adc_channel_select; + +component slv_adc_snoop is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_adc_snoop; + +component adc_snoop_mem is +port( + WRADDRESS : in std_logic_vector(9 downto 0); + RDADDRESS : in std_logic_vector(9 downto 0); + DATA : in std_logic_vector(15 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(15 downto 0) +); +end component adc_snoop_mem; + +component max_data is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TODO_3_IN : in std_logic_vector(3 downto 0); + TODO_2_IN : in std_logic_vector(3 downto 0); + TODO_1_IN : in std_logic_vector(3 downto 0); + TODO_0_IN : in std_logic_vector(3 downto 0); + TODO_MAX_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component max_data; + +component slv_register_bank is +generic( + RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(3 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + BACKPLANE_IN : in std_logic_vector(2 downto 0); + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_register_bank; + +component slv_status is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + STATUS_IN : in std_logic_vector(31 downto 0) +); +end component slv_status; + +component slv_status_bank is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(3 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + STAT_0_IN : in std_logic_vector(31 downto 0); + STAT_1_IN : in std_logic_vector(31 downto 0); + STAT_2_IN : in std_logic_vector(31 downto 0); + STAT_3_IN : in std_logic_vector(31 downto 0); + STAT_4_IN : in std_logic_vector(31 downto 0); + STAT_5_IN : in std_logic_vector(31 downto 0); + STAT_6_IN : in std_logic_vector(31 downto 0); + STAT_7_IN : in std_logic_vector(31 downto 0); + STAT_8_IN : in std_logic_vector(31 downto 0); + STAT_9_IN : in std_logic_vector(31 downto 0); + STAT_10_IN : in std_logic_vector(31 downto 0); + STAT_11_IN : in std_logic_vector(31 downto 0); + STAT_12_IN : in std_logic_vector(31 downto 0); + STAT_13_IN : in std_logic_vector(31 downto 0); + STAT_14_IN : in std_logic_vector(31 downto 0); + STAT_15_IN : in std_logic_vector(31 downto 0) +); +end component slv_status_bank; + +component pulse_stretch is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + PULSE_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component pulse_stretch; + +component apv_adc_map_mem is +port( + ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component apv_adc_map_mem; + +component adc_apv_map_mem is +port( + ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component adc_apv_map_mem; + +component ped_thr_true is +port( + DATAINA : in std_logic_vector(17 downto 0); + DATAINB : in std_logic_vector(17 downto 0); + ADDRESSA : in std_logic_vector(6 downto 0); + ADDRESSB : in std_logic_vector(6 downto 0); + CLOCKA : in std_logic; + CLOCKB : in std_logic; + CLOCKENA : in std_logic; + CLOCKENB : in std_logic; + WRA : in std_logic; + WRB : in std_logic; + RESETA : in std_logic; + RESETB : in std_logic; + QA : out std_logic_vector(17 downto 0); + QB : out std_logic_vector(17 downto 0) +); +end component ped_thr_true; + +component slv_ped_thr_mem is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(10 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(6 downto 0); + MEM_0_D_OUT : out std_logic_vector(17 downto 0); + MEM_1_D_OUT : out std_logic_vector(17 downto 0); + MEM_2_D_OUT : out std_logic_vector(17 downto 0); + MEM_3_D_OUT : out std_logic_vector(17 downto 0); + MEM_4_D_OUT : out std_logic_vector(17 downto 0); + MEM_5_D_OUT : out std_logic_vector(17 downto 0); + MEM_6_D_OUT : out std_logic_vector(17 downto 0); + MEM_7_D_OUT : out std_logic_vector(17 downto 0); + MEM_8_D_OUT : out std_logic_vector(17 downto 0); + MEM_9_D_OUT : out std_logic_vector(17 downto 0); + MEM_10_D_OUT : out std_logic_vector(17 downto 0); + MEM_11_D_OUT : out std_logic_vector(17 downto 0); + MEM_12_D_OUT : out std_logic_vector(17 downto 0); + MEM_13_D_OUT : out std_logic_vector(17 downto 0); + MEM_14_D_OUT : out std_logic_vector(17 downto 0); + MEM_15_D_OUT : out std_logic_vector(17 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_ped_thr_mem; + +component pll_40m is +port( + CLK : in std_logic; + RESET : in std_logic; + DPAMODE : in std_logic; + DPHASE0 : in std_logic; + DPHASE1 : in std_logic; + DPHASE2 : in std_logic; + DPHASE3 : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic +); +end component pll_40m; + +component dll_100m is +port( + CLK : in std_logic; + RESETN : in std_logic; + ALUHOLD : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic +); +end component dll_100m; + +component state_sync is +port( + STATE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + STATE_B_OUT : out std_logic + ); +end component state_sync; + +component pulse_sync is +port( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic +); +end component pulse_sync; + +component rich_trb is +port( + CLK100M_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_PRESENT_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; + SD_LOS_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic; + -- common regIO status / control registers +-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI +-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(3*32-1 downto 0); -- common control register, bit definitions like in WIKI + -- status register input to regIO / control register output from regIO + CONTROL_OUT : out std_logic_vector(63 downto 0); + STATUS_IN : in std_logic_vector(127 downto 0); + -- LVL1 signals + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_IN : in std_logic; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_INT_TRG_UPDATE_OUT : out std_logic; + TIMING_TRG_FOUND_IN : in std_logic; + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_OUT : out std_logic; -- gimme data! + IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_IN : in std_logic; -- data is valid + IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM + IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle + IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern + -- regIO bus +-- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; +-- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); +-- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0); + REGIO_DATAREADY_IN : in std_logic; + REGIO_NO_MORE_DATA_IN : in std_logic; + REGIO_WRITE_ACK_IN : in std_logic; + REGIO_UNKNOWN_ADDR_IN : in std_logic; + REGIO_TIMEOUT_OUT : out std_logic; + -- status LEDs + LED_LINK_STAT : out std_logic; + LED_LINK_TXD : out std_logic; + LED_LINK_RXD : out std_logic; + LINK_BSM_OUT : out std_logic_vector(3 downto 0); + RESET_OUT : out std_logic; + TICK_10S_OUT : out std_logic; + -- Debug + DEBUG : out std_logic_vector(63 downto 0) +); +end component rich_trb; + +component slave_bus is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- RegIO signals + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus + REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint + REGIO_READ_ENABLE_IN : in std_logic; -- read pulse + REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse + REGIO_TIMEOUT_IN : in std_logic; -- access timed out + REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested + REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted + REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now + REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- 1Wire connections + ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse) + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); -- 1Wire ID on APV FEs + BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + -- ADC 0 SPI connections + SPI_ADC0_CS_OUT : out std_logic; + SPI_ADC0_SCK_OUT : out std_logic; + SPI_ADC0_SDO_OUT : out std_logic; + ADC0_PLL_LOCKED_IN : in std_logic; + ADC0_PD_OUT : out std_logic; + ADC0_RST_OUT : out std_logic; + ADC0_DEL_OUT : out std_logic_vector(3 downto 0); + ADC0_CLK_IN : in std_logic; + ADC0_DATA_IN : in std_logic_vector(11 downto 0); + ADC0_SEL_OUT : out std_logic_vector(2 downto 0); + APV0_RST_OUT : out std_logic; + -- ADC 0 SPI connections + SPI_ADC1_CS_OUT : out std_logic; + SPI_ADC1_SCK_OUT : out std_logic; + SPI_ADC1_SDO_OUT : out std_logic; + ADC1_PLL_LOCKED_IN : in std_logic; + ADC1_PD_OUT : out std_logic; + ADC1_RST_OUT : out std_logic; + ADC1_DEL_OUT : out std_logic_vector(3 downto 0); + ADC1_CLK_IN : in std_logic; + ADC1_DATA_IN : in std_logic_vector(11 downto 0); + ADC1_SEL_OUT : out std_logic_vector(2 downto 0); + APV1_RST_OUT : out std_logic; + -- User specific inputs / outputs + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- pedestal interface + PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers + PED_DATA_0_OUT : out std_logic_vector(17 downto 0); + PED_DATA_1_OUT : out std_logic_vector(17 downto 0); + PED_DATA_2_OUT : out std_logic_vector(17 downto 0); + PED_DATA_3_OUT : out std_logic_vector(17 downto 0); + PED_DATA_4_OUT : out std_logic_vector(17 downto 0); + PED_DATA_5_OUT : out std_logic_vector(17 downto 0); + PED_DATA_6_OUT : out std_logic_vector(17 downto 0); + PED_DATA_7_OUT : out std_logic_vector(17 downto 0); + PED_DATA_8_OUT : out std_logic_vector(17 downto 0); + PED_DATA_9_OUT : out std_logic_vector(17 downto 0); + PED_DATA_10_OUT : out std_logic_vector(17 downto 0); + PED_DATA_11_OUT : out std_logic_vector(17 downto 0); + PED_DATA_12_OUT : out std_logic_vector(17 downto 0); + PED_DATA_13_OUT : out std_logic_vector(17 downto 0); + PED_DATA_14_OUT : out std_logic_vector(17 downto 0); + PED_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- threshold interface + THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers + THR_DATA_0_OUT : out std_logic_vector(17 downto 0); + THR_DATA_1_OUT : out std_logic_vector(17 downto 0); + THR_DATA_2_OUT : out std_logic_vector(17 downto 0); + THR_DATA_3_OUT : out std_logic_vector(17 downto 0); + THR_DATA_4_OUT : out std_logic_vector(17 downto 0); + THR_DATA_5_OUT : out std_logic_vector(17 downto 0); + THR_DATA_6_OUT : out std_logic_vector(17 downto 0); + THR_DATA_7_OUT : out std_logic_vector(17 downto 0); + THR_DATA_8_OUT : out std_logic_vector(17 downto 0); + THR_DATA_9_OUT : out std_logic_vector(17 downto 0); + THR_DATA_10_OUT : out std_logic_vector(17 downto 0); + THR_DATA_11_OUT : out std_logic_vector(17 downto 0); + THR_DATA_12_OUT : out std_logic_vector(17 downto 0); + THR_DATA_13_OUT : out std_logic_vector(17 downto 0); + THR_DATA_14_OUT : out std_logic_vector(17 downto 0); + THR_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- APV control / status + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- FIFO status + FIFO_STATUS_0_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_1_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_2_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_3_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_4_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_5_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_6_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_7_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_8_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_9_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_10_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_11_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_12_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_13_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_14_IN : in std_logic_vector(31 downto 0); + FIFO_STATUS_15_IN : in std_logic_vector(31 downto 0); + IPU_STATUS_IN : in std_logic_vector(31 downto 0); + RELEASE_STATUS_IN : in std_logic_vector(31 downto 0); + -- some control signals + CTRL_LVL_OUT : out std_logic_vector(31 downto 0); + CTRL_TRG_OUT : out std_logic_vector(31 downto 0); + CTRL_PLL_OUT : out std_logic_vector(15 downto 0); + STATUS_PLL_IN : in std_logic_vector(15 downto 0); + -- temporary stuff + TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing! + TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing! + -- Debug + DEBUG_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) +); +end component slave_bus; + + +component apv_trgctrl is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + -- Triggers + SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow + TRG_FOUND_OUT : out std_logic; -- trigger found + TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel + SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number + -- slow control settings + TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + -- TRB LVL1 signals + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type + TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- TRB LVL1 trigger information + TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received + TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger + TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel + TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); + TRB_COUNTER_IN : in std_logic_vector(15 downto 0); + TRB_LD_COUNTER_IN : in std_logic; + -- EDS signals + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word + EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done + EDS_DONE_IN : in std_logic; -- release current EDS buffer + EDS_FULL_OUT : out std_logic; -- EDS buffer is full + EDS_LEVEL_OUT : out std_logic_vector(4 downto 0); + FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement) + -- APV signals + APV_TRG_OUT : out std_logic; + APV_SYNC_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component apv_trgctrl; + +component ped_corr_ctrl is +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control registers + VERBOSE_IN : in std_logic; -- add debug words for each APV + -- EDS buffer -- back to previous source stage + EDS_DATA_IN : in std_logic_vector(39 downto 0); + EDS_AVAIL_IN : in std_logic; + EDS_DONE_OUT : out std_logic; + -- DHDR information -- to next stage + DHDR_DATA_OUT : out std_logic_vector(31 downto 0); + DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0); + DHDR_STORE_OUT : out std_logic; + DHDR_BUF_FULL_IN : in std_logic; + FIFO_SPACE_REQ_OUT : out std_logic_vector(11 downto 0); + -- data buffers -- from raw_buf_stage + BUF_ADDR_OUT : out std_logic_vector(6 downto 0); + BUF_DONE_OUT : out std_logic; + BUF_TICK_IN : in std_logic_vector(15 downto 0); + BUF_START_IN : in std_logic_vector(15 downto 0); + -- raw data + BUF_0_DATA_IN : in std_logic_vector(37 downto 0); + BUF_1_DATA_IN : in std_logic_vector(37 downto 0); + BUF_2_DATA_IN : in std_logic_vector(37 downto 0); + BUF_3_DATA_IN : in std_logic_vector(37 downto 0); + BUF_4_DATA_IN : in std_logic_vector(37 downto 0); + BUF_5_DATA_IN : in std_logic_vector(37 downto 0); + BUF_6_DATA_IN : in std_logic_vector(37 downto 0); + BUF_7_DATA_IN : in std_logic_vector(37 downto 0); + BUF_8_DATA_IN : in std_logic_vector(37 downto 0); + BUF_9_DATA_IN : in std_logic_vector(37 downto 0); + BUF_10_DATA_IN : in std_logic_vector(37 downto 0); + BUF_11_DATA_IN : in std_logic_vector(37 downto 0); + BUF_12_DATA_IN : in std_logic_vector(37 downto 0); + BUF_13_DATA_IN : in std_logic_vector(37 downto 0); + BUF_14_DATA_IN : in std_logic_vector(37 downto 0); + BUF_15_DATA_IN : in std_logic_vector(37 downto 0); + -- Pedestal data + PED_ADDR_OUT : out std_logic_vector(6 downto 0); + PED_0_DATA_IN : in std_logic_vector(17 downto 0); + PED_1_DATA_IN : in std_logic_vector(17 downto 0); + PED_2_DATA_IN : in std_logic_vector(17 downto 0); + PED_3_DATA_IN : in std_logic_vector(17 downto 0); + PED_4_DATA_IN : in std_logic_vector(17 downto 0); + PED_5_DATA_IN : in std_logic_vector(17 downto 0); + PED_6_DATA_IN : in std_logic_vector(17 downto 0); + PED_7_DATA_IN : in std_logic_vector(17 downto 0); + PED_8_DATA_IN : in std_logic_vector(17 downto 0); + PED_9_DATA_IN : in std_logic_vector(17 downto 0); + PED_10_DATA_IN : in std_logic_vector(17 downto 0); + PED_11_DATA_IN : in std_logic_vector(17 downto 0); + PED_12_DATA_IN : in std_logic_vector(17 downto 0); + PED_13_DATA_IN : in std_logic_vector(17 downto 0); + PED_14_DATA_IN : in std_logic_vector(17 downto 0); + PED_15_DATA_IN : in std_logic_vector(17 downto 0); + -- Threshold data + THR_ADDR_OUT : out std_logic_vector(6 downto 0); + THR_0_DATA_IN : in std_logic_vector(17 downto 0); + THR_1_DATA_IN : in std_logic_vector(17 downto 0); + THR_2_DATA_IN : in std_logic_vector(17 downto 0); + THR_3_DATA_IN : in std_logic_vector(17 downto 0); + THR_4_DATA_IN : in std_logic_vector(17 downto 0); + THR_5_DATA_IN : in std_logic_vector(17 downto 0); + THR_6_DATA_IN : in std_logic_vector(17 downto 0); + THR_7_DATA_IN : in std_logic_vector(17 downto 0); + THR_8_DATA_IN : in std_logic_vector(17 downto 0); + THR_9_DATA_IN : in std_logic_vector(17 downto 0); + THR_10_DATA_IN : in std_logic_vector(17 downto 0); + THR_11_DATA_IN : in std_logic_vector(17 downto 0); + THR_12_DATA_IN : in std_logic_vector(17 downto 0); + THR_13_DATA_IN : in std_logic_vector(17 downto 0); + THR_14_DATA_IN : in std_logic_vector(17 downto 0); + THR_15_DATA_IN : in std_logic_vector(17 downto 0); + -- processed data + FIFO_START_OUT : out std_logic; + FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_WE_OUT : out std_logic_vector(15 downto 0); + FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component ped_corr_ctrl; + +component ipu_fifo_stage is +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + IPU_RESET_IN : in std_logic; -- requested by TRBnet standard + -- Slow control signals + SECTOR_IN : in std_logic_vector(2 downto 0); + MODULE_IN : in std_logic_vector(2 downto 0); + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + IPU_LAST_NUM_OUT : out std_logic_vector(31 downto 0); -- last number received / readout + LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter + -- DHDR buffer input + DHDR_DATA_IN : in std_logic_vector(31 downto 0); + DHDR_LENGTH_IN : in std_logic_vector(15 downto 0); + DHDR_STORE_IN : in std_logic; + DHDR_BUF_FULL_OUT : out std_logic; + -- processed data input + FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0); + FIFO_START_IN : in std_logic; + FIFO_0_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_1_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_2_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_3_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_4_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_5_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_6_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_7_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_8_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_9_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_10_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_11_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_12_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_13_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_14_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_15_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_WE_IN : in std_logic_vector(15 downto 0); + FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs + -- data buffer status + FIFO_0_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_1_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_2_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_3_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_4_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_5_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_6_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_7_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_8_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_9_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_10_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_11_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_12_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_13_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_14_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_15_STATUS_OUT : out std_logic_vector(31 downto 0); + IPU_STATUS_OUT : out std_logic_vector(31 downto 0); + RELEASE_STATUS_OUT : out std_logic_vector(31 downto 0); + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) +); +end component ipu_fifo_stage; + +component ipu_dummy is +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control signals + MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value + MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value + CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + -- DHDR buffer + LVL1_FIFO_RD_OUT : out std_logic; + LVL1_FIFO_EMPTY_IN : in std_logic; + LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0); + LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0); + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) +); +end component ipu_dummy; + +component reboot_handler is +port( + RESET_IN : in std_logic; + CLK_IN : in std_logic; + START_IN : in std_logic; + REBOOT_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component reboot_handler; + +component real_trg_handler is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse) + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint + TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel + SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type + TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information + TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB + TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger + LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); -- LVL1 counter + LVL1_COUNTER_IN : in std_logic_vector(15 downto 0); + LVL1_LD_COUNTER_IN : in std_logic; + BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator + APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine + APV_TRGSTART_OUT : out std_logic; -- start one APV trigger state machine + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data + EDS_WE_OUT : out std_logic; -- EDS write enable (general interface) + EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level + EDS_READY_OUT : out std_logic; -- APV trigger sequence done, TERMinate the TRB LVL1 trigger + DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component real_trg_handler; + +component apv_trg_handler is +port( + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- synced reset signal (100MHz) + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers + APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished + APV_TRG_OUT : out std_logic; + APV_TRGSENT_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_trg_handler; + +component apv_sync_handler is +port( + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- synced reset signal (100MHz) + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished + APV_TRG_OUT : out std_logic; + APV_SYNC_OUT : out std_logic; -- signal for statemachines + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_sync_handler; + +component eds_buf is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + -- EDS input, all synced to CLK_IN + EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input + EDS_WE_IN : in std_logic; -- EDS write enable + EDS_DONE_IN : in std_logic; -- release EDS + EDS_DATA_OUT : out std_logic_vector(39 downto 0); + EDS_AVAILABLE_OUT : out std_logic; + -- trigger busy information + BUF_FULL_OUT : out std_logic; + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component eds_buf; + +component adc_pll is +port( + CLK : in std_logic; + RESET : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic +); +end component adc_pll; + +component adc_ch_in is +port( + DEL : in std_logic_vector(3 downto 0); + ECLK : in std_logic; + SCLK : in std_logic; + RST : in std_logic; + DATA : in std_logic_vector(0 downto 0); + Q : out std_logic_vector(1 downto 0) +); +End component adc_ch_in; + +component adc_twochannels is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLOCK_IN : in std_logic_vector(1 downto 0); -- DDR bit clock + DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one + DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two + DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one + DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two + STORE_OUT : out std_logic; + SWAP_OUT : out std_logic; + CLOCK_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component adc_twochannels; + +component apv_locker is +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to ADC_CLK_IN + ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid + SYNC_IN : in std_logic; -- sync trigger input + APV_ON_IN : in std_logic; -- this APV channel is switched on + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0' + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1' + FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline + STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off) + STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet + STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid + STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully + STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong + STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully + STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected + STATUS_TICKMARK_OUT : out std_logic; + FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header + FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header + FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?) + FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow + FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow + FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames + APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID + APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high + APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low + APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data + APV_ANALOG_OUT : out std_logic; -- APV analog data is valid + APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer + APV_LAST_OUT : out std_logic; -- last APV channel of dataframe + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_locker; + +component apv_raw_buffer is +port( + CLK_APV_IN : in std_logic; -- write clock from APV handling stage + RESET_IN : in std_logic; + FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event + ADC_ANALOG_IN : in std_logic; -- write enable for ADC data + ADC_START_IN : in std_logic; -- data frame detected, block the buffer page + ADC_LAST_IN : in std_logic; -- last channel signal + ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID + ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR + ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV + ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame + BUF_CLK_IN : in std_logic; -- read clock + BUF_RESET_IN : in std_logic; -- 100MHz reset + BUF_START_OUT : out std_logic; -- one block starts writing + BUF_READY_OUT : out std_logic; -- one block has been written + BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer + BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer) + BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer + BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output + BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output + BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation + BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation + BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer + BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler + BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set! + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_raw_buffer; + +-- moved to trb_net_components.vhd +-- +--component slv_register is +--generic( +-- RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" +--); +--port( +-- CLK_IN : in std_logic; +-- RESET_IN : in std_logic; +-- BUSY_IN : in std_logic; +-- -- Slave bus +-- SLV_READ_IN : in std_logic; +-- SLV_WRITE_IN : in std_logic; +-- SLV_BUSY_OUT : out std_logic; +-- SLV_ACK_OUT : out std_logic; +-- SLV_DATA_IN : in std_logic_vector(31 downto 0); +-- SLV_DATA_OUT : out std_logic_vector(31 downto 0); +-- -- I/O to the backend +-- REG_DATA_IN : in std_logic_vector(31 downto 0); +-- REG_DATA_OUT : out std_logic_vector(31 downto 0); +-- -- Status lines +-- STAT : out std_logic_vector(31 downto 0) -- DEBUG +--); +--end component slv_register; + +component slv_half_register is +generic( + RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + STATUS_REG_IN : in std_logic_vector(15 downto 0); + CTRL_REG_OUT : out std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_half_register; + +component i2c_master is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component i2c_master; + +component slv_onewire_memory is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(5 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- 1Wire lines + ONEWIRE_START_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); + BP_ONEWIRE_INOUT : inout std_logic; + -- Status lines + STAT : out std_logic_vector(63 downto 0) -- DEBUG +); +end component slv_onewire_memory; + +component spi_real_slim is +port( + SYSCLK : in std_logic; -- 100MHz sysclock + RESET : in std_logic; -- synchronous reset + -- Command interface + START_IN : in std_logic; -- one start pulse + BUSY_OUT : out std_logic; -- SPI transactions are ongoing + CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte + -- SPI interface + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + -- DEBUG + CLK_EN_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component spi_real_slim; + +component spi_adc_master is +generic( + RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + -- ADC connections + ADC_LOCKED_IN : in std_logic; + ADC_PD_OUT : out std_logic; + ADC_RST_OUT : out std_logic; + ADC_DEL_OUT : out std_logic_vector(3 downto 0); + -- APV connections + APV_RST_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component spi_adc_master; + +component i2c_slim is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- I2C command / setup + I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions + ACTION_IN : in std_logic; -- '0' -> write, '1' -> read + I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined) + I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) + I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command + I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command + STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits + I2C_BUSY_OUT : out std_logic; + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Debug + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component i2c_slim; + +component i2c_gstart is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + DOSTART_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector(7 downto 0); + SDONE_OUT : out std_logic; + SOK_OUT : out std_logic; + SDA_IN : in std_logic; + SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0) +); +end component i2c_gstart; + +component i2c_sendb is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + DOBYTE_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector(7 downto 0); + I2C_BYTE_IN : in std_logic_vector(8 downto 0); + I2C_BACK_OUT : out std_logic_vector(8 downto 0); + SDA_IN : in std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; +-- SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + BDONE_OUT : out std_logic; + BOK_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0) +); +end component i2c_sendb; + +component onewire_master is +generic( + CLK_PERIOD : integer := 10 -- clock perion in nanoseconds +); +port( + CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic; + -- connection to 1-wire interface (16 APV FEs) + ONEWIRE : inout std_logic_vector(15 downto 0); + BP_ONEWIRE : inout std_logic; + -- connection to external DPRAM for slow control readout + BP_DATA_OUT : out std_logic_vector(15 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(6 downto 0); + WRITE_OUT : out std_logic; + BUSY_OUT : out std_logic; + -- debug + BSM_OUT : out std_logic_vector(7 downto 0); + STAT : out std_logic_vector(15 downto 0) +); +end component onewire_master; + +component slv_onewire_dpram +port( + WRADDRESS : in std_logic_vector(6 downto 0); + RDADDRESS : in std_logic_vector(5 downto 0); + DATA : in std_logic_vector(15 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(31 downto 0) +); +end component slv_onewire_dpram; + +component fifo_2kx27 is +port( + DATA : in std_logic_vector(26 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(26 downto 0); + WCNT : out std_logic_vector(11 downto 0); + EMPTY : out std_logic; + FULL : out std_logic +); +end component fifo_2kx27; + +component fifo_1kx18 is +port( + DATA : in std_logic_vector(17 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(10 downto 0); + EMPTY : out std_logic; + ALMOSTFULL : out std_logic; + FULL : out std_logic +); +end component fifo_1kx18; + +component decoder_8bit is +port( + ADDRESS : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component decoder_8bit; + +component buf_toc is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUF_TICK_IN : in std_logic; -- tickmark from raw buffer + BUF_START_IN : in std_logic; -- start of frame from raw buffer + WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode + FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS + BUF_LVL_IN : in std_logic_vector(7 downto 0); + GOODDATA_OUT : out std_logic; + BADDATA_OUT : out std_logic; + NODATA_OUT : out std_logic; + READY_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component buf_toc; + +component ref_row_sel is +port( + CLK_IN : in std_logic; + READY_IN : in std_logic_vector(15 downto 0); + GOODDATA_IN : in std_logic_vector(15 downto 0); + FRAME_0_IN : in std_logic_vector(11 downto 0); + FRAME_1_IN : in std_logic_vector(11 downto 0); + FRAME_2_IN : in std_logic_vector(11 downto 0); + FRAME_3_IN : in std_logic_vector(11 downto 0); + FRAME_4_IN : in std_logic_vector(11 downto 0); + FRAME_5_IN : in std_logic_vector(11 downto 0); + FRAME_6_IN : in std_logic_vector(11 downto 0); + FRAME_7_IN : in std_logic_vector(11 downto 0); + FRAME_8_IN : in std_logic_vector(11 downto 0); + FRAME_9_IN : in std_logic_vector(11 downto 0); + FRAME_10_IN : in std_logic_vector(11 downto 0); + FRAME_11_IN : in std_logic_vector(11 downto 0); + FRAME_12_IN : in std_logic_vector(11 downto 0); + FRAME_13_IN : in std_logic_vector(11 downto 0); + FRAME_14_IN : in std_logic_vector(11 downto 0); + FRAME_15_IN : in std_logic_vector(11 downto 0); + VALID_BUFS_OUT : out std_logic; + READY_OUT : out std_logic; + ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong + APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit + APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0); + REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component ref_row_sel; + +component frmctr_check is +port( + CLK_IN : in std_logic; + GOODDATA_IN : in std_logic_vector(15 downto 0); + FRAMECOUNTER_IN : in std_logic_vector(3 downto 0); + FRM_NR_0_IN : in std_logic_vector(3 downto 0); + FRM_NR_1_IN : in std_logic_vector(3 downto 0); + FRM_NR_2_IN : in std_logic_vector(3 downto 0); + FRM_NR_3_IN : in std_logic_vector(3 downto 0); + FRM_NR_4_IN : in std_logic_vector(3 downto 0); + FRM_NR_5_IN : in std_logic_vector(3 downto 0); + FRM_NR_6_IN : in std_logic_vector(3 downto 0); + FRM_NR_7_IN : in std_logic_vector(3 downto 0); + FRM_NR_8_IN : in std_logic_vector(3 downto 0); + FRM_NR_9_IN : in std_logic_vector(3 downto 0); + FRM_NR_10_IN : in std_logic_vector(3 downto 0); + FRM_NR_11_IN : in std_logic_vector(3 downto 0); + FRM_NR_12_IN : in std_logic_vector(3 downto 0); + FRM_NR_13_IN : in std_logic_vector(3 downto 0); + FRM_NR_14_IN : in std_logic_vector(3 downto 0); + FRM_NR_15_IN : in std_logic_vector(3 downto 0); + FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component frmctr_check; + +component apv_pc_nc_alu is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + START_IN : in std_logic; + MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested + CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number + LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + EDS_DATA_IN : in std_logic_vector(39 downto 0); -- DEBUG !!! + BUF_GOOD_IN : in std_logic; + BUF_BAD_IN : in std_logic; + BUF_IGNORE_IN : in std_logic; + ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers + DO_HEADER_IN : in std_logic; + DO_ERROR_IN : in std_logic; + SUPPRESS_IN : in std_logic; + VERBOSE_IN : in std_logic; + EVT_TYPE_IN : in std_logic_vector(2 downto 0); + RAW_ADDR_IN : in std_logic_vector(6 downto 0); + RAW_DATA_IN : in std_logic_vector(37 downto 0); + PED_DATA_IN : in std_logic_vector(17 downto 0); + THR_DATA_IN : in std_logic_vector(17 downto 0); + FRAME_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0] + WE_OUT : out std_logic; + COUNT_OUT : out std_logic_vector(9 downto 0); + ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_pc_nc_alu; + +component input_bram is +port( + WRADDRESS : in std_logic_vector(10 downto 0); + RDADDRESS : in std_logic_vector(10 downto 0); + DATA : in std_logic_vector(17 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(17 downto 0) +); +end component input_bram; + +component frame_status_mem is +port( + WRADDRESS : in std_logic_vector(3 downto 0); + DATA : in std_logic_vector(11 downto 0); + WRCLOCK : in std_logic; + WE : in std_logic; + WRCLOCKEN : in std_logic; + RDADDRESS : in std_logic_vector(3 downto 0); + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(11 downto 0) +); +end component frame_status_mem; + +component apv_lock_sm is +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + SYNC_IN : in std_logic; -- start APV synchronisation + ADC_VALID_IN : in std_logic; -- ADC delivers valid data + TIMED_IN : in std_logic; -- synchronisation timeout + MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter + LOCKED_IN : in std_logic; -- enough good tickmarks + TICK_IN : in std_logic; -- tickmark from digital parser + HEADER_IN : in std_logic; -- header from digital parser + FLATLINE_IN : in std_logic; -- flatline from digital parser + RST_PC_OUT : out std_logic; -- reset period counter + RST_TC_OUT : out std_logic; -- reset timeout counter + INC_TC_OUT : out std_logic; + RST_LC_OUT : out std_logic; -- reset lock counter + INC_LC_OUT : out std_logic; + UNKNOWN_OUT : out std_logic; + BADADC_OUT : out std_logic; -- ADC data invalid + LOCKED_OUT : out std_logic; + LOST_OUT : out std_logic; + NOSYNC_OUT : out std_logic; + NOAPV_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_lock_sm; + +component apv_digital is +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); + BIT_LOW_IN : in std_logic_vector(11 downto 0); + BIT_HIGH_IN : in std_logic_vector(11 downto 0); + FL_LOW_IN : in std_logic_vector(11 downto 0); + FL_HIGH_IN : in std_logic_vector(11 downto 0); + BIT_DATA_OUT : out std_logic_vector(11 downto 0); + BIT_VALID_OUT : out std_logic_vector(11 downto 0); + BIT_HIGH_OUT : out std_logic; + BIT_LOW_OUT : out std_logic; + TICKMARK_OUT : out std_logic; + HEADER_OUT : out std_logic; + FLAT_LINE_OUT : out std_logic +); +end component apv_digital; + +component eds_buffer_dpram is +port( + WRADDRESS : in std_logic_vector(3 downto 0); + DATA : in std_logic_vector(39 downto 0); + WRCLOCK : in std_logic; + WE : in std_logic; + WRCLOCKEN : in std_logic; + RDADDRESS : in std_logic_vector(3 downto 0); + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(39 downto 0) +); +end component eds_buffer_dpram; + +end package; + +-- Down in the Dumps... diff --git a/source/adcmv3_testfifo.vhd b/design/adcmv3_testfifo.vhd similarity index 100% rename from source/adcmv3_testfifo.vhd rename to design/adcmv3_testfifo.vhd diff --git a/cores/apv_adc_map_mem.lpc b/design/apv_adc_map_mem.lpc similarity index 100% rename from cores/apv_adc_map_mem.lpc rename to design/apv_adc_map_mem.lpc diff --git a/cores/apv_adc_map_mem.srp b/design/apv_adc_map_mem.srp similarity index 100% rename from cores/apv_adc_map_mem.srp rename to design/apv_adc_map_mem.srp diff --git a/cores/apv_adc_map_mem.vhd b/design/apv_adc_map_mem.vhd similarity index 100% rename from cores/apv_adc_map_mem.vhd rename to design/apv_adc_map_mem.vhd diff --git a/cores/apv_adc_map_mem_generate.log b/design/apv_adc_map_mem_generate.log similarity index 100% rename from cores/apv_adc_map_mem_generate.log rename to design/apv_adc_map_mem_generate.log diff --git a/cores/apv_adc_map_mem_tmpl.vhd b/design/apv_adc_map_mem_tmpl.vhd similarity index 100% rename from cores/apv_adc_map_mem_tmpl.vhd rename to design/apv_adc_map_mem_tmpl.vhd diff --git a/source/apv_adc_mapping.mem b/design/apv_adc_mapping.mem similarity index 100% rename from source/apv_adc_mapping.mem rename to design/apv_adc_mapping.mem diff --git a/source/apv_digital.vhd b/design/apv_digital.vhd similarity index 100% rename from source/apv_digital.vhd rename to design/apv_digital.vhd diff --git a/source/apv_lock_sm.vhd b/design/apv_lock_sm.vhd similarity index 100% rename from source/apv_lock_sm.vhd rename to design/apv_lock_sm.vhd diff --git a/source/apv_locker.vhd b/design/apv_locker.vhd similarity index 100% rename from source/apv_locker.vhd rename to design/apv_locker.vhd diff --git a/cores/apv_map_mem.lpc b/design/apv_map_mem.lpc similarity index 100% rename from cores/apv_map_mem.lpc rename to design/apv_map_mem.lpc diff --git a/cores/apv_map_mem.srp b/design/apv_map_mem.srp similarity index 100% rename from cores/apv_map_mem.srp rename to design/apv_map_mem.srp diff --git a/cores/apv_map_mem.vhd b/design/apv_map_mem.vhd similarity index 100% rename from cores/apv_map_mem.vhd rename to design/apv_map_mem.vhd diff --git a/cores/apv_map_mem_generate.log b/design/apv_map_mem_generate.log similarity index 100% rename from cores/apv_map_mem_generate.log rename to design/apv_map_mem_generate.log diff --git a/cores/apv_map_mem_tmpl.vhd b/design/apv_map_mem_tmpl.vhd similarity index 100% rename from cores/apv_map_mem_tmpl.vhd rename to design/apv_map_mem_tmpl.vhd diff --git a/source/apv_mapping.mem b/design/apv_mapping.mem similarity index 100% rename from source/apv_mapping.mem rename to design/apv_mapping.mem diff --git a/source/apv_pc_nc_alu.vhd b/design/apv_pc_nc_alu.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/apv_pc_nc_alu.vhd rename to design/apv_pc_nc_alu.vhd diff --git a/source/apv_raw_buffer.vhd b/design/apv_raw_buffer.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/apv_raw_buffer.vhd rename to design/apv_raw_buffer.vhd diff --git a/source/apv_sync_handler.vhd b/design/apv_sync_handler.vhd similarity index 100% rename from source/apv_sync_handler.vhd rename to design/apv_sync_handler.vhd diff --git a/source/apv_trg_handler.vhd b/design/apv_trg_handler.vhd similarity index 100% rename from source/apv_trg_handler.vhd rename to design/apv_trg_handler.vhd diff --git a/source/apv_trgctrl.vhd b/design/apv_trgctrl.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/apv_trgctrl.vhd rename to design/apv_trgctrl.vhd diff --git a/source/buf_toc.vhd b/design/buf_toc.vhd similarity index 100% rename from source/buf_toc.vhd rename to design/buf_toc.vhd diff --git a/cores/crossover.lpc b/design/crossover.lpc similarity index 100% rename from cores/crossover.lpc rename to design/crossover.lpc diff --git a/cores/crossover.srp b/design/crossover.srp similarity index 100% rename from cores/crossover.srp rename to design/crossover.srp diff --git a/cores/crossover.vhd b/design/crossover.vhd similarity index 100% rename from cores/crossover.vhd rename to design/crossover.vhd diff --git a/cores/crossover_generate.log b/design/crossover_generate.log similarity index 100% rename from cores/crossover_generate.log rename to design/crossover_generate.log diff --git a/cores/crossover_tmpl.vhd b/design/crossover_tmpl.vhd similarity index 100% rename from cores/crossover_tmpl.vhd rename to design/crossover_tmpl.vhd diff --git a/source/dbg_reg.vhd b/design/dbg_reg.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/dbg_reg.vhd rename to design/dbg_reg.vhd diff --git a/cores/decoder_8bit.lpc b/design/decoder_8bit.lpc similarity index 100% rename from cores/decoder_8bit.lpc rename to design/decoder_8bit.lpc diff --git a/cores/decoder_8bit.mem b/design/decoder_8bit.mem similarity index 100% rename from cores/decoder_8bit.mem rename to design/decoder_8bit.mem diff --git a/cores/decoder_8bit.vhd b/design/decoder_8bit.vhd similarity index 100% rename from cores/decoder_8bit.vhd rename to design/decoder_8bit.vhd diff --git a/cores/decoder_8bit_tmpl.vhd b/design/decoder_8bit_tmpl.vhd similarity index 100% rename from cores/decoder_8bit_tmpl.vhd rename to design/decoder_8bit_tmpl.vhd diff --git a/cores/dll_100m.lpc b/design/dll_100m.lpc similarity index 100% rename from cores/dll_100m.lpc rename to design/dll_100m.lpc diff --git a/cores/dll_100m.vhd b/design/dll_100m.vhd similarity index 100% rename from cores/dll_100m.vhd rename to design/dll_100m.vhd diff --git a/cores/dll_100m_tmpl.vhd b/design/dll_100m_tmpl.vhd similarity index 100% rename from cores/dll_100m_tmpl.vhd rename to design/dll_100m_tmpl.vhd diff --git a/cores/dpram_8x19.lpc b/design/dpram_8x19.lpc similarity index 100% rename from cores/dpram_8x19.lpc rename to design/dpram_8x19.lpc diff --git a/cores/dpram_8x19.srp b/design/dpram_8x19.srp similarity index 100% rename from cores/dpram_8x19.srp rename to design/dpram_8x19.srp diff --git a/cores/dpram_8x19.vhd b/design/dpram_8x19.vhd similarity index 100% rename from cores/dpram_8x19.vhd rename to design/dpram_8x19.vhd diff --git a/cores/dpram_8x19_generate.log b/design/dpram_8x19_generate.log similarity index 100% rename from cores/dpram_8x19_generate.log rename to design/dpram_8x19_generate.log diff --git a/cores/dpram_8x19_tmpl.vhd b/design/dpram_8x19_tmpl.vhd similarity index 100% rename from cores/dpram_8x19_tmpl.vhd rename to design/dpram_8x19_tmpl.vhd diff --git a/source/eds_buf.vhd b/design/eds_buf.vhd similarity index 100% rename from source/eds_buf.vhd rename to design/eds_buf.vhd diff --git a/cores/eds_buffer_dpram.lpc b/design/eds_buffer_dpram.lpc similarity index 100% rename from cores/eds_buffer_dpram.lpc rename to design/eds_buffer_dpram.lpc diff --git a/cores/eds_buffer_dpram.vhd b/design/eds_buffer_dpram.vhd similarity index 100% rename from cores/eds_buffer_dpram.vhd rename to design/eds_buffer_dpram.vhd diff --git a/cores/eds_buffer_dpram_tmpl.vhd b/design/eds_buffer_dpram_tmpl.vhd similarity index 100% rename from cores/eds_buffer_dpram_tmpl.vhd rename to design/eds_buffer_dpram_tmpl.vhd diff --git a/cores/fifo_16x11.lpc b/design/fifo_16x11.lpc similarity index 100% rename from cores/fifo_16x11.lpc rename to design/fifo_16x11.lpc diff --git a/cores/fifo_16x11.srp b/design/fifo_16x11.srp similarity index 100% rename from cores/fifo_16x11.srp rename to design/fifo_16x11.srp diff --git a/cores/fifo_16x11.vhd b/design/fifo_16x11.vhd similarity index 100% rename from cores/fifo_16x11.vhd rename to design/fifo_16x11.vhd diff --git a/cores/fifo_16x11_generate.log b/design/fifo_16x11_generate.log similarity index 100% rename from cores/fifo_16x11_generate.log rename to design/fifo_16x11_generate.log diff --git a/cores/fifo_16x11_tmpl.vhd b/design/fifo_16x11_tmpl.vhd similarity index 100% rename from cores/fifo_16x11_tmpl.vhd rename to design/fifo_16x11_tmpl.vhd diff --git a/cores/fifo_1kx18.lpc b/design/fifo_1kx18.lpc similarity index 100% rename from cores/fifo_1kx18.lpc rename to design/fifo_1kx18.lpc diff --git a/cores/fifo_1kx18.srp b/design/fifo_1kx18.srp similarity index 100% rename from cores/fifo_1kx18.srp rename to design/fifo_1kx18.srp diff --git a/cores/fifo_1kx18.vhd b/design/fifo_1kx18.vhd similarity index 100% rename from cores/fifo_1kx18.vhd rename to design/fifo_1kx18.vhd diff --git a/cores/fifo_1kx18_generate.log b/design/fifo_1kx18_generate.log similarity index 100% rename from cores/fifo_1kx18_generate.log rename to design/fifo_1kx18_generate.log diff --git a/cores/fifo_1kx18_tmpl.vhd b/design/fifo_1kx18_tmpl.vhd similarity index 100% rename from cores/fifo_1kx18_tmpl.vhd rename to design/fifo_1kx18_tmpl.vhd diff --git a/cores/fifo_2kx27.lpc b/design/fifo_2kx27.lpc similarity index 100% rename from cores/fifo_2kx27.lpc rename to design/fifo_2kx27.lpc diff --git a/cores/fifo_2kx27.vhd b/design/fifo_2kx27.vhd similarity index 100% rename from cores/fifo_2kx27.vhd rename to design/fifo_2kx27.vhd diff --git a/cores/fifo_2kx27_tmpl.vhd b/design/fifo_2kx27_tmpl.vhd similarity index 100% rename from cores/fifo_2kx27_tmpl.vhd rename to design/fifo_2kx27_tmpl.vhd diff --git a/cores/frame_status_mem.lpc b/design/frame_status_mem.lpc similarity index 100% rename from cores/frame_status_mem.lpc rename to design/frame_status_mem.lpc diff --git a/cores/frame_status_mem.srp b/design/frame_status_mem.srp similarity index 100% rename from cores/frame_status_mem.srp rename to design/frame_status_mem.srp diff --git a/cores/frame_status_mem.vhd b/design/frame_status_mem.vhd similarity index 100% rename from cores/frame_status_mem.vhd rename to design/frame_status_mem.vhd diff --git a/cores/frame_status_mem_generate.log b/design/frame_status_mem_generate.log similarity index 100% rename from cores/frame_status_mem_generate.log rename to design/frame_status_mem_generate.log diff --git a/cores/frame_status_mem_tmpl.vhd b/design/frame_status_mem_tmpl.vhd similarity index 100% rename from cores/frame_status_mem_tmpl.vhd rename to design/frame_status_mem_tmpl.vhd diff --git a/source/frmctr_check.vhd b/design/frmctr_check.vhd similarity index 100% rename from source/frmctr_check.vhd rename to design/frmctr_check.vhd diff --git a/source/i2c_gstart.vhd b/design/i2c_gstart.vhd similarity index 100% rename from source/i2c_gstart.vhd rename to design/i2c_gstart.vhd diff --git a/source/i2c_master.vhd b/design/i2c_master.vhd similarity index 100% rename from source/i2c_master.vhd rename to design/i2c_master.vhd diff --git a/source/i2c_sendb.vhd b/design/i2c_sendb.vhd similarity index 100% rename from source/i2c_sendb.vhd rename to design/i2c_sendb.vhd diff --git a/source/i2c_slim.vhd b/design/i2c_slim.vhd similarity index 100% rename from source/i2c_slim.vhd rename to design/i2c_slim.vhd diff --git a/cores/input_bram.lpc b/design/input_bram.lpc similarity index 100% rename from cores/input_bram.lpc rename to design/input_bram.lpc diff --git a/cores/input_bram.srp b/design/input_bram.srp similarity index 100% rename from cores/input_bram.srp rename to design/input_bram.srp diff --git a/cores/input_bram.vhd b/design/input_bram.vhd similarity index 100% rename from cores/input_bram.vhd rename to design/input_bram.vhd diff --git a/cores/input_bram_generate.log b/design/input_bram_generate.log similarity index 100% rename from cores/input_bram_generate.log rename to design/input_bram_generate.log diff --git a/cores/input_bram_tmpl.vhd b/design/input_bram_tmpl.vhd similarity index 100% rename from cores/input_bram_tmpl.vhd rename to design/input_bram_tmpl.vhd diff --git a/source/ipu_fifo_stage.vhd b/design/ipu_fifo_stage.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/ipu_fifo_stage.vhd rename to design/ipu_fifo_stage.vhd diff --git a/design/ipu_fifo_stage.vhd~ b/design/ipu_fifo_stage.vhd~ new file mode 100755 index 0000000..f0824e2 --- /dev/null +++ b/design/ipu_fifo_stage.vhd~ @@ -0,0 +1,708 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.adcmv3_components.all; + +-- Missing: FIFO buffer handling, full / empty checks + +entity ipu_fifo_stage is +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + IPU_RESET_IN : in std_logic; -- requested by TRBnet standard + -- Slow control signals + SECTOR_IN : in std_logic_vector(2 downto 0); + MODULE_IN : in std_logic_vector(2 downto 0); + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + IPU_LAST_NUM_OUT : out std_logic_vector(31 downto 0); -- last number received / readout + LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter + -- DHDR buffer input + DHDR_DATA_IN : in std_logic_vector(31 downto 0); + DHDR_LENGTH_IN : in std_logic_vector(15 downto 0); + DHDR_STORE_IN : in std_logic; + DHDR_BUF_FULL_OUT : out std_logic; + -- processed data input + FIFO_START_IN : in std_logic; + FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0); + FIFO_0_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_1_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_2_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_3_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_4_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_5_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_6_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_7_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_8_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_9_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_10_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_11_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_12_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_13_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_14_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_15_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_WE_IN : in std_logic_vector(15 downto 0); + FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs + -- data buffer status + FIFO_0_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_1_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_2_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_3_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_4_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_5_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_6_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_7_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_8_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_9_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_10_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_11_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_12_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_13_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_14_STATUS_OUT : out std_logic_vector(31 downto 0); + FIFO_15_STATUS_OUT : out std_logic_vector(31 downto 0); + IPU_STATUS_OUT : out std_logic_vector(31 downto 0); + RELEASE_STATUS_OUT : out std_logic_vector(31 downto 0); + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) +); +end; + +architecture behavioral of ipu_fifo_stage is + +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group"; + +-- state machine definitions +type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- signals +signal debug : std_logic_vector(63 downto 0); +signal bsm_x : std_logic_vector(7 downto 0); +signal next_trgnum_match : std_logic; +signal trgnum_match : std_logic; + +signal dhdr_fifo_in_int : std_logic_vector(47 downto 0); +signal dhdr_fifo_out_int : std_logic_vector(47 downto 0); +signal dhdr_avail : std_logic; +signal next_todo_list : std_logic_vector(15 downto 0); +signal todo_list : std_logic_vector(15 downto 0); +signal next_fifo_sel : std_logic_vector(4 downto 0); +signal fifo_sel : std_logic_vector(4 downto 0); +signal next_sel_fifo : std_logic_vector(15 downto 0); +signal sel_fifo : std_logic_vector(15 downto 0); + +signal comb_rd_dfifo : std_logic_vector(15 downto 0); +signal comb_st_data : std_logic_vector(15 downto 0); +signal comb_ack_todo : std_logic; + +signal ipu_out_data : std_logic_vector(31 downto 0); + +-- state machine signals +signal next_rd_lfifo : std_logic; +signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit) +signal next_dataready : std_logic; +signal dataready : std_logic; -- data word is available +signal next_set_hdr : std_logic; +signal set_hdr : std_logic; -- store DHDR in output register +signal next_set_data : std_logic; +signal set_data : std_logic; -- store DATA from current DATA FIFO in output register +signal next_ld_todo : std_logic; +signal ld_todo : std_logic; -- load initial TODO list +signal next_ack_todo : std_logic; +signal ack_todo : std_logic; -- remove current entry from TODO list +signal next_finished : std_logic; +signal finished : std_logic; -- readout is finished +signal next_preload : std_logic; +signal preload : std_logic; -- read first data word from DATA FIFOs + +-- generate needs arrays... +type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0); +signal fifo_in_data : fifo_data_t; +signal fifo_out_data : fifo_data_t; +type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0); +signal fifo_in_count : fifo_count_t; +type fifo_todo_t is array (0 to 15) of unsigned(9 downto 0); +signal fifo_todo : fifo_todo_t; +type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0); +signal fifo_ldata : fifo_ldata_t; +type fifo_cnt_t is array (0 to 15) of unsigned(11 downto 0); +signal fifo_data_free_x : fifo_cnt_t; +signal fifo_data_free : fifo_cnt_t; +type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0); +signal fifo_wcnt : fifo_wcnt_t; +type fifo_lunused_t is array (0 to 15) of std_logic_vector(6 downto 0); +signal fifo_lunused : fifo_lunused_t; +type fifo_status_t is array (0 to 15) of std_logic_vector(31 downto 0); +signal fifo_status : fifo_status_t; + +signal ipu_status : std_logic_vector(31 downto 0); +signal release_status : std_logic_vector(31 downto 0); + +signal dfifo_available_x : std_logic_vector(15 downto 0); +signal dfifo_available : std_logic_vector(15 downto 0); +signal dfifo_empty : std_logic_vector(15 downto 0); +signal dfifo_full : std_logic_vector(15 downto 0); + +signal lfifo_empty : std_logic_vector(15 downto 0); +signal lfifo_almostfull : std_logic_vector(15 downto 0); +signal lfifo_full : std_logic_vector(15 downto 0); + +signal next_fifo_done : std_logic_vector(15 downto 0); +signal fifo_done : std_logic_vector(15 downto 0); +signal next_fifo_last : std_logic; +signal fifo_last : std_logic; + +signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking! + +signal old_apv_num : std_logic_vector(3 downto 0); +signal new_apv_num : std_logic_vector(3 downto 0); + +signal cyclectr : unsigned(15 downto 0); -- cycle counter + +signal next_dhdr_buf_full : std_logic; +signal dhdr_buf_full : std_logic; + +signal reset_all : std_logic; + +-- Jan Michel's status bits (faked) +signal status_bits : std_logic_vector(3 downto 0); + +attribute syn_noprune : boolean; +attribute syn_noprune of THE_DBG_REG : label is true; +signal my_debug : std_logic_vector(15 downto 0); + +begin + +-------------------------------------------------------------------- +-- Test the NOPRUNE + EPIC feature +-------------------------------------------------------------------- +THE_DBG_REG: dbg_reg +generic map( + WIDTH => 16 +) +port map( + DEBUG_IN => my_debug, + DEBUG_OUT => open +); + +my_debug(15) <= next_dataready; +my_debug(14 downto 8) <= fifo_wcnt(0)(6 downto 0); +my_debug(7 downto 0) <= bsm_x; +-------------------------------------------------------------------- +-------------------------------------------------------------------- + +--------------------------------------------------------------------------- +-- Combine syncronous resets +--------------------------------------------------------------------------- +reset_all <= RESET_IN or IPU_RESET_IN; + +--------------------------------------------------------------------------- +-- Statemachine +--------------------------------------------------------------------------- + +-- state registers +STATE_MEM: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( reset_all = '1' ) then + CURRENT_STATE <= SLEEP; + rd_lfifo <= '0'; + dataready <= '0'; + set_hdr <= '0'; + set_data <= '0'; + ld_todo <= '0'; + ack_todo <= '0'; + preload <= '0'; + finished <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + rd_lfifo <= next_rd_lfifo; + dataready <= next_dataready; + set_hdr <= next_set_hdr; + set_data <= next_set_data; + ld_todo <= next_ld_todo; + ack_todo <= next_ack_todo; + preload <= next_preload; + finished <= next_finished; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, dhdr_avail, IPU_START_READOUT_IN, IPU_READ_IN, fifo_last, fifo_sel(4) ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + next_rd_lfifo <= '0'; + next_dataready <= '0'; + next_set_hdr <= '0'; + next_set_data <= '0'; + next_ld_todo <= '0'; + next_ack_todo <= '0'; + next_preload <= '0'; + next_finished <= '0'; + + case CURRENT_STATE is + when SLEEP => if( (dhdr_avail = '1') and (IPU_START_READOUT_IN = '1') ) then + NEXT_STATE <= RDLF; + next_rd_lfifo <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when RDLF => NEXT_STATE <= GETFD; + next_set_hdr <= '1'; + next_ld_todo <= '1'; + when GETFD => NEXT_STATE <= DELH; + next_preload <= '1'; + when DELH => NEXT_STATE <= WHDR; + next_dataready <= '1'; + when WHDR => if ( (IPU_READ_IN = '1') and (fifo_sel(4) = '0') ) then + NEXT_STATE <= GETD; -- there are datawords to send + next_set_data <= '1'; + next_ack_todo <= '1'; + elsif( (IPU_READ_IN = '1') and (fifo_sel(4) = '1') ) then + NEXT_STATE <= DONE; -- only DHDR, no data words + next_finished <= '1'; + else + NEXT_STATE <= WHDR; + next_dataready <= '1'; + end if; + when GETD => if( fifo_last = '1' ) then + NEXT_STATE <= DEL0; + else + NEXT_STATE <= WAITD; + next_dataready <= '1'; + end if; + when WAITD => if( ipu_read_in = '1' ) then + NEXT_STATE <= GETD; + next_set_data <= '1'; + else + NEXT_STATE <= WAITD; + next_dataready <= '1'; + end if; + when DEL0 => NEXT_STATE <= WAITDL; + next_dataready <= '1'; + when WAITDL => if ( (IPU_READ_IN = '1') and (fifo_sel(4) = '0') ) then + NEXT_STATE <= GETD; + next_set_data <= '1'; + next_ack_todo <= '1'; + elsif( (IPU_READ_IN = '1') and (fifo_sel(4) = '1') ) then + NEXT_STATE <= DONE; + next_finished <= '1'; + else + NEXT_STATE <= WAITDL; + next_dataready <= '1'; + end if; + when DONE => if( IPU_START_READOUT_IN = '0' ) then + NEXT_STATE <= SLEEP; + else + NEXT_STATE <= DONE; + end if; + + when others => NEXT_STATE <= SLEEP; + end case; +end process STATE_TRANSFORM; + +-- Handshaking to IPU data channel +IPU_DATAREADY_OUT <= dataready; +IPU_READOUT_FINISHED_OUT <= finished; + +-- length information can be simply copied +IPU_LENGTH_OUT <= dhdr_fifo_out_int(47 downto 32); + +-- IPU error pattern +IPU_ERROR_PATTERN_OUT(31 downto 24) <= (others => '0'); +IPU_ERROR_PATTERN_OUT(23) <= '0'; -- "single broken event" +IPU_ERROR_PATTERN_OUT(23) <= '0'; -- "severe problem" +IPU_ERROR_PATTERN_OUT(21) <= '0'; -- "partially not found" +IPU_ERROR_PATTERN_OUT(20) <= not trgnum_match; -- "not found" +IPU_ERROR_PATTERN_OUT(19 downto 0) <= (others => '0'); + +-- state decoding (ONLY FOR DEBUGGING!) +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm_x <= x"00"; + status_bits <= x"0"; + when RDLF => bsm_x <= x"11"; --x"01"; + status_bits <= x"1"; + when GETFD => bsm_x <= x"22"; --x"02"; + status_bits <= x"2"; + when DELH => bsm_x <= x"33"; --x"03"; + status_bits <= x"3"; + when WHDR => bsm_x <= x"f4"; --x"04"; + status_bits <= x"3"; + when GETD => bsm_x <= x"e5"; --x"05"; + status_bits <= x"4"; + when WAITD => bsm_x <= x"d6"; --x"06"; + status_bits <= x"4"; + when WAITDL => bsm_x <= x"c7"; --x"07"; + status_bits <= x"4"; + when DEL0 => bsm_x <= x"b8"; --x"08"; + status_bits <= x"4"; + when DONE => bsm_x <= x"a9"; --x"09"; + status_bits <= x"5"; + when others => bsm_x <= x"ff"; + status_bits <= x"f"; + end case; +end process STATE_DECODE; + +--------------------------------------------------------------------------- +-- Aliasing the data streams +--------------------------------------------------------------------------- +fifo_in_data(0) <= FIFO_0_DATA_IN(26 downto 0); fifo_in_count(0) <= FIFO_0_DATA_IN(37 downto 27); +fifo_in_data(1) <= FIFO_1_DATA_IN(26 downto 0); fifo_in_count(1) <= FIFO_1_DATA_IN(37 downto 27); +fifo_in_data(2) <= FIFO_2_DATA_IN(26 downto 0); fifo_in_count(2) <= FIFO_2_DATA_IN(37 downto 27); +fifo_in_data(3) <= FIFO_3_DATA_IN(26 downto 0); fifo_in_count(3) <= FIFO_3_DATA_IN(37 downto 27); +fifo_in_data(4) <= FIFO_4_DATA_IN(26 downto 0); fifo_in_count(4) <= FIFO_4_DATA_IN(37 downto 27); +fifo_in_data(5) <= FIFO_5_DATA_IN(26 downto 0); fifo_in_count(5) <= FIFO_5_DATA_IN(37 downto 27); +fifo_in_data(6) <= FIFO_6_DATA_IN(26 downto 0); fifo_in_count(6) <= FIFO_6_DATA_IN(37 downto 27); +fifo_in_data(7) <= FIFO_7_DATA_IN(26 downto 0); fifo_in_count(7) <= FIFO_7_DATA_IN(37 downto 27); +fifo_in_data(8) <= FIFO_8_DATA_IN(26 downto 0); fifo_in_count(8) <= FIFO_8_DATA_IN(37 downto 27); +fifo_in_data(9) <= FIFO_9_DATA_IN(26 downto 0); fifo_in_count(9) <= FIFO_9_DATA_IN(37 downto 27); +fifo_in_data(10) <= FIFO_10_DATA_IN(26 downto 0); fifo_in_count(10) <= FIFO_10_DATA_IN(37 downto 27); +fifo_in_data(11) <= FIFO_11_DATA_IN(26 downto 0); fifo_in_count(11) <= FIFO_11_DATA_IN(37 downto 27); +fifo_in_data(12) <= FIFO_12_DATA_IN(26 downto 0); fifo_in_count(12) <= FIFO_12_DATA_IN(37 downto 27); +fifo_in_data(13) <= FIFO_13_DATA_IN(26 downto 0); fifo_in_count(13) <= FIFO_13_DATA_IN(37 downto 27); +fifo_in_data(14) <= FIFO_14_DATA_IN(26 downto 0); fifo_in_count(14) <= FIFO_14_DATA_IN(37 downto 27); +fifo_in_data(15) <= FIFO_15_DATA_IN(26 downto 0); fifo_in_count(15) <= FIFO_15_DATA_IN(37 downto 27); + +--------------------------------------------------------------------------- +-- DATA and LENGTH FIFO for the APV data streams +--------------------------------------------------------------------------- + +-- We also store the DHDR inside the LFIFOs. They are big enough and have unused bits like hell. +dhdr_fifo_in_int <= DHDR_LENGTH_IN & DHDR_DATA_IN; + +GEN_FIFO: for i in 0 to 15 generate + THE_DFIFO: fifo_2kx27 + port map( + DATA => fifo_in_data(i), + CLOCK => CLK_IN, + WREN => FIFO_WE_IN(i), + RDEN => comb_rd_dfifo(i), + RESET => reset_all, + Q => fifo_out_data(i), + WCNT => fifo_wcnt(i), + EMPTY => dfifo_empty(i), + FULL => dfifo_full(i) + ); + + -- Combinatorial read pulse for FIFOs + comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and IPU_READ_IN and dataready) or (preload and fifo_ldata(i)(10)); + + -- Combinatorial store pulse for data (last data word need to be transfered also!) + comb_st_data(i) <= (sel_fifo(i) and IPU_READ_IN and dataready); + + -- getting the number of free entries in the data fifo by subtracting [size] - [used entries] + fifo_data_free_x(i) <= x"800" - unsigned(fifo_wcnt(i)); + + -- check if next event will still fit into data FIFO + dfifo_available_x(i) <= '1' when (fifo_data_free(i) > unsigned(FIFO_SPACE_REQ_IN)) else '0'; + + THE_SMALL_SYNCER: process( clk_in) + begin + if( rising_edge(clk_in) ) then + fifo_data_free(i) <= fifo_data_free_x(i); + dfifo_available(i) <= dfifo_available_x(i); + end if; + end process THE_SMALL_SYNCER; + + -- length fifo - stores the number of words to fetch from dfifo + THE_LFIFO: fifo_1kx18 + port map( + DATA(17 downto 15) => dhdr_fifo_in_int(i*3 + 2 downto i*3), + DATA(14 downto 11) => b"0000", -- free for other stuff! + DATA(10 downto 0) => fifo_in_count(i), + CLOCK => CLK_IN, + WREN => FIFO_DONE_IN, + RDEN => rd_lfifo, + RESET => reset_all, + Q(17 downto 11) => fifo_lunused(i), -- will be portions of DHDR + Q(10 downto 0) => fifo_ldata(i), + WCNT => open, -- BUG + EMPTY => lfifo_empty(i), -- BUG + ALMOSTFULL => lfifo_almostfull(i), -- BUG + FULL => lfifo_full(i) -- BUG + ); + next_todo_list(i) <= fifo_ldata(i)(10); + + -- reassamble the DHDR information + dhdr_fifo_out_int(i*3 + 2 downto i*3) <= fifo_lunused(i)(6 downto 4); + + -- TODO counter for all FIFOs + THE_TODO_CTR_PROC: process( clk_in ) + begin + if( rising_edge(clk_in) ) then + if( (reset_all = '1') or (rd_lfifo = '1') ) then + fifo_todo(i) <= (others => '0'); + elsif( ld_todo = '1' ) then + fifo_todo(i) <= unsigned(fifo_ldata(i)(9 downto 0)); + elsif( comb_rd_dfifo(i) = '1' ) then + fifo_todo(i) <= fifo_todo(i) - 1; + end if; + end if; + end process THE_TODO_CTR_PROC; + + next_fifo_done(i) <= '1' when ( fifo_todo(i) = b"00_0000_0000" ) else '0'; + + -- FIFO status bits, compatible with Jans data handler + fifo_status(i)(31 downto 28) <= (others => '0'); -- reserved + fifo_status(i)(27) <= '0'; --fifo_done_in; -- length FIFO write strobe (not implemented) + fifo_status(i)(26) <= lfifo_full(i); -- length FIFO full. This is an error flag. + fifo_status(i)(25) <= lfifo_almostfull(i); -- length FIFO almost full + fifo_status(i)(24) <= lfifo_empty(i); -- length FIFO empty + fifo_status(i)(23) <= '0'; -- reserved + fifo_status(i)(22) <= '0'; -- buffer state machine waiting for busy release + fifo_status(i)(21) <= '0'; -- buffer state machine busy waiting for data + fifo_status(i)(20) <= '0'; -- buffer state machine idle + fifo_status(i)(19) <= '0'; --FIFO_WE_IN(i); -- FIFO write strobe (not implemented) + fifo_status(i)(18) <= dfifo_full(i); -- FIFO full. This is an error flag. + fifo_status(i)(17) <= not dfifo_available(i); -- FIFO almost full + fifo_status(i)(16) <= dfifo_empty(i); -- FIFO empty + fifo_status(i)(15 downto 0) <= b"0000" & fifo_wcnt(i); -- current fill level of FIFO + +end generate GEN_FIFO; + +comb_ack_todo <= fifo_last and set_data; + +next_dhdr_buf_full <= '1' when (lfifo_almostfull(0) = '1') or + (dfifo_available /= b"1111_1111_1111_1111") + else '0'; +dhdr_avail <= not lfifo_empty(0); -- FAKE + +-- compare incoming trigger number with stored DHDR information +next_trgnum_match <= '1' when ( IPU_NUMBER_IN = dhdr_fifo_out_int(15 downto 0) ) else '0'; + +THE_TRGNUM_MATCH_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( reset_all = '1' ) then + trgnum_match <= '0'; + my_trg_number <= (others => '0'); + elsif( set_hdr = '1' ) then + trgnum_match <= next_trgnum_match; + my_trg_number <= IPU_NUMBER_IN & dhdr_fifo_out_int(15 downto 0); + end if; + end if; +end process THE_TRGNUM_MATCH_PROC; + + +--------------------------------------------------------------------------- +-- priority encoding is used to select the next buffer for readout +--------------------------------------------------------------------------- +THE_PRI_ENCODER_PROC: process( todo_list, fifo_done ) +begin + if ( todo_list(15 downto 15) = "1" ) then + next_fifo_sel <= "01111"; next_sel_fifo <= b"1000_0000_0000_0000"; next_fifo_last <= fifo_done(15); + elsif( todo_list(15 downto 14) = "01" ) then + next_fifo_sel <= "01110"; next_sel_fifo <= b"0100_0000_0000_0000"; next_fifo_last <= fifo_done(14); + elsif( todo_list(15 downto 13) = "001" ) then + next_fifo_sel <= "01101"; next_sel_fifo <= b"0010_0000_0000_0000"; next_fifo_last <= fifo_done(13); + elsif( todo_list(15 downto 12) = "0001" ) then + next_fifo_sel <= "01100"; next_sel_fifo <= b"0001_0000_0000_0000"; next_fifo_last <= fifo_done(12); + elsif( todo_list(15 downto 11) = "00001" ) then + next_fifo_sel <= "01011"; next_sel_fifo <= b"0000_1000_0000_0000"; next_fifo_last <= fifo_done(11); + elsif( todo_list(15 downto 10) = "000001" ) then + next_fifo_sel <= "01010"; next_sel_fifo <= b"0000_0100_0000_0000"; next_fifo_last <= fifo_done(10); + elsif( todo_list(15 downto 9) = "0000001" ) then + next_fifo_sel <= "01001"; next_sel_fifo <= b"0000_0010_0000_0000"; next_fifo_last <= fifo_done(9); + elsif( todo_list(15 downto 8) = "00000001" ) then + next_fifo_sel <= "01000"; next_sel_fifo <= b"0000_0001_0000_0000"; next_fifo_last <= fifo_done(8); + elsif( todo_list(15 downto 7) = "000000001" ) then + next_fifo_sel <= "00111"; next_sel_fifo <= b"0000_0000_1000_0000"; next_fifo_last <= fifo_done(7); + elsif( todo_list(15 downto 6) = "0000000001" ) then + next_fifo_sel <= "00110"; next_sel_fifo <= b"0000_0000_0100_0000"; next_fifo_last <= fifo_done(6); + elsif( todo_list(15 downto 5) = "00000000001" ) then + next_fifo_sel <= "00101"; next_sel_fifo <= b"0000_0000_0010_0000"; next_fifo_last <= fifo_done(5); + elsif( todo_list(15 downto 4) = "000000000001" ) then + next_fifo_sel <= "00100"; next_sel_fifo <= b"0000_0000_0001_0000"; next_fifo_last <= fifo_done(4); + elsif( todo_list(15 downto 3) = "0000000000001" ) then + next_fifo_sel <= "00011"; next_sel_fifo <= b"0000_0000_0000_1000"; next_fifo_last <= fifo_done(3); + elsif( todo_list(15 downto 2) = "00000000000001" ) then + next_fifo_sel <= "00010"; next_sel_fifo <= b"0000_0000_0000_0100"; next_fifo_last <= fifo_done(2); + elsif( todo_list(15 downto 1) = "000000000000001" ) then + next_fifo_sel <= "00001"; next_sel_fifo <= b"0000_0000_0000_0010"; next_fifo_last <= fifo_done(1); + elsif( todo_list(15 downto 0) = "0000000000000001" ) then + next_fifo_sel <= "00000"; next_sel_fifo <= b"0000_0000_0000_0001"; next_fifo_last <= fifo_done(0); + else + next_fifo_sel <= "10000"; next_sel_fifo <= b"0000_0000_0000_0000"; next_fifo_last <= '0'; + end if; +end process THE_PRI_ENCODER_PROC; + +-- We need to clear single bits during readout here!!! +THE_TODO_LIST_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( reset_all = '1' ) then + todo_list <= (others => '0'); + elsif( ld_todo = '1' ) then + todo_list <= next_todo_list; -- store initial todo list + elsif( comb_ack_todo = '1' ) then + todo_list <= todo_list and not sel_fifo; -- does this work?!? + end if; + end if; +end process THE_TODO_LIST_PROC; + + + +--------------------------------------------------------------------------- +-- synchronizing process +--------------------------------------------------------------------------- +THE_SYNC_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + fifo_sel <= next_fifo_sel; + sel_fifo <= next_sel_fifo; + fifo_done <= next_fifo_done; + fifo_last <= next_fifo_last; + dhdr_buf_full <= next_dhdr_buf_full; + end if; +end process THE_SYNC_PROC; + + +--------------------------------------------------------------------------- +-- backplane wise APV mapping +--------------------------------------------------------------------------- +old_apv_num <= fifo_sel(3 downto 0); + +THE_ADC_APV_MAP_MEM: adc_apv_map_mem +port map( ADDRESS(6 downto 4) => MODULE_IN(2 downto 0), + ADDRESS(3 downto 0) => old_apv_num, + Q => new_apv_num + ); + +--------------------------------------------------------------------------- +-- Data multiplexer +--------------------------------------------------------------------------- +THE_DATA_MUX_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if ( set_hdr = '1' ) then + ipu_out_data <= dhdr_fifo_out_int(31 downto 0); + elsif( comb_st_data(0) = '1' ) then + ipu_out_data <= fifo_out_data(0)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(0)(20 downto 0); + elsif( comb_st_data(1) = '1' ) then + ipu_out_data <= fifo_out_data(1)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(1)(20 downto 0); + elsif( comb_st_data(2) = '1' ) then + ipu_out_data <= fifo_out_data(2)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(2)(20 downto 0); + elsif( comb_st_data(3) = '1' ) then + ipu_out_data <= fifo_out_data(3)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(3)(20 downto 0); + elsif( comb_st_data(4) = '1' ) then + ipu_out_data <= fifo_out_data(4)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(4)(20 downto 0); + elsif( comb_st_data(5) = '1' ) then + ipu_out_data <= fifo_out_data(5)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(5)(20 downto 0); + elsif( comb_st_data(6) = '1' ) then + ipu_out_data <= fifo_out_data(6)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(6)(20 downto 0); + elsif( comb_st_data(7) = '1' ) then + ipu_out_data <= fifo_out_data(7)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(7)(20 downto 0); + elsif( comb_st_data(8) = '1' ) then + ipu_out_data <= fifo_out_data(8)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(8)(20 downto 0); + elsif( comb_st_data(9) = '1' ) then + ipu_out_data <= fifo_out_data(9)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(9)(20 downto 0); + elsif( comb_st_data(10) = '1' ) then + ipu_out_data <= fifo_out_data(10)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(10)(20 downto 0); + elsif( comb_st_data(11) = '1' ) then + ipu_out_data <= fifo_out_data(11)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(11)(20 downto 0); + elsif( comb_st_data(12) = '1' ) then + ipu_out_data <= fifo_out_data(12)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(12)(20 downto 0); + elsif( comb_st_data(13) = '1' ) then + ipu_out_data <= fifo_out_data(13)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(13)(20 downto 0); + elsif( comb_st_data(14) = '1' ) then + ipu_out_data <= fifo_out_data(14)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(14)(20 downto 0); + elsif( comb_st_data(15) = '1' ) then + ipu_out_data <= fifo_out_data(15)(21) & SECTOR_IN(2 downto 0) & MODULE_IN(2 downto 0) & new_apv_num & fifo_out_data(15)(20 downto 0); + end if; + end if; +end process THE_DATA_MUX_PROC; + + +--------------------------------------------------------------------------- +-- IPU cycle counter... just to be sure +--------------------------------------------------------------------------- +THE_CYCLE_COUNTER_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( reset_all = '1' ) then + cyclectr <= (others => '0'); + elsif( finished = '1' ) then + cyclectr <= cyclectr + 1; + end if; + end if; +end process THE_CYCLE_COUNTER_PROC; + +-- IPU handler status +ipu_status(31 downto 16) <= (others => '0'); -- reserved +ipu_status(15) <= '0'; -- error flag: endpoint not configured +ipu_status(14) <= '0'; -- error flag: synchronisation +ipu_status(13) <= '0'; -- error flag: event has missing data +ipu_status(12) <= not trgnum_match; -- error flag: event not found +ipu_status(11 downto 4) <= (others => '0'); -- reserved +ipu_status(3 downto 0) <= status_bits; -- IPU transfer status + +-- LVL1 and IPU channel release status +release_status(31 downto 16) <= fifo_done; +release_status(15 downto 0) <= (others => '0'); -- BUG + +--------------------------------------------------------------------------- +-- Output signals +--------------------------------------------------------------------------- +IPU_DATA_OUT <= ipu_out_data; +LVL2_COUNTER_OUT <= std_logic_vector(cyclectr); +IPU_LAST_NUM_OUT <= my_trg_number; +DHDR_BUF_FULL_OUT <= dhdr_buf_full; + +FIFO_0_STATUS_OUT <= fifo_status(0); +FIFO_1_STATUS_OUT <= fifo_status(1); +FIFO_2_STATUS_OUT <= fifo_status(2); +FIFO_3_STATUS_OUT <= fifo_status(3); +FIFO_4_STATUS_OUT <= fifo_status(4); +FIFO_5_STATUS_OUT <= fifo_status(5); +FIFO_6_STATUS_OUT <= fifo_status(6); +FIFO_7_STATUS_OUT <= fifo_status(7); +FIFO_8_STATUS_OUT <= fifo_status(8); +FIFO_9_STATUS_OUT <= fifo_status(9); +FIFO_10_STATUS_OUT <= fifo_status(10); +FIFO_11_STATUS_OUT <= fifo_status(11); +FIFO_12_STATUS_OUT <= fifo_status(12); +FIFO_13_STATUS_OUT <= fifo_status(13); +FIFO_14_STATUS_OUT <= fifo_status(14); +FIFO_15_STATUS_OUT <= fifo_status(15); +IPU_STATUS_OUT <= ipu_status; +RELEASE_STATUS_OUT <= release_status; + +--------------------------------------------------------------------------- +-- debug information +--------------------------------------------------------------------------- +debug(63 downto 48) <= todo_list; +debug(47 downto 25) <= (others => '0'); +debug(24 downto 20) <= fifo_sel; +debug(19 downto 17) <= (others => '0'); +debug(16) <= fifo_last; +debug(15 downto 0) <= fifo_done; + +--------------------------------------------------------------------------- +-- DEBUG signals +--------------------------------------------------------------------------- +DBG_BSM_OUT <= bsm_x; +DBG_OUT <= debug; + +end behavioral; + + + + + diff --git a/source/ipu_fifo_stage_BACK.vhd b/design/ipu_fifo_stage_BACK.vhd similarity index 100% rename from source/ipu_fifo_stage_BACK.vhd rename to design/ipu_fifo_stage_BACK.vhd diff --git a/source/logic_analyzer.vhd b/design/logic_analyzer.vhd similarity index 100% rename from source/logic_analyzer.vhd rename to design/logic_analyzer.vhd diff --git a/source/max_data.vhd b/design/max_data.vhd similarity index 100% rename from source/max_data.vhd rename to design/max_data.vhd diff --git a/cores/msg_file.log b/design/msg_file.log similarity index 100% rename from cores/msg_file.log rename to design/msg_file.log diff --git a/cores/mult_3x8.lpc b/design/mult_3x8.lpc similarity index 100% rename from cores/mult_3x8.lpc rename to design/mult_3x8.lpc diff --git a/cores/mult_3x8.srp b/design/mult_3x8.srp similarity index 100% rename from cores/mult_3x8.srp rename to design/mult_3x8.srp diff --git a/cores/mult_3x8.vhd b/design/mult_3x8.vhd similarity index 100% rename from cores/mult_3x8.vhd rename to design/mult_3x8.vhd diff --git a/cores/mult_3x8_generate.log b/design/mult_3x8_generate.log similarity index 100% rename from cores/mult_3x8_generate.log rename to design/mult_3x8_generate.log diff --git a/cores/mult_3x8_tmpl.vhd b/design/mult_3x8_tmpl.vhd similarity index 100% rename from cores/mult_3x8_tmpl.vhd rename to design/mult_3x8_tmpl.vhd diff --git a/source/my_sbuf.vhd b/design/my_sbuf.vhd similarity index 100% rename from source/my_sbuf.vhd rename to design/my_sbuf.vhd diff --git a/source/onewire_master.vhd b/design/onewire_master.vhd similarity index 100% rename from source/onewire_master.vhd rename to design/onewire_master.vhd diff --git a/cores/onewire_spare_one.lpc b/design/onewire_spare_one.lpc similarity index 100% rename from cores/onewire_spare_one.lpc rename to design/onewire_spare_one.lpc diff --git a/cores/onewire_spare_one.srp b/design/onewire_spare_one.srp similarity index 100% rename from cores/onewire_spare_one.srp rename to design/onewire_spare_one.srp diff --git a/cores/onewire_spare_one.vhd b/design/onewire_spare_one.vhd similarity index 100% rename from cores/onewire_spare_one.vhd rename to design/onewire_spare_one.vhd diff --git a/cores/onewire_spare_one_generate.log b/design/onewire_spare_one_generate.log similarity index 100% rename from cores/onewire_spare_one_generate.log rename to design/onewire_spare_one_generate.log diff --git a/cores/onewire_spare_one_tmpl.vhd b/design/onewire_spare_one_tmpl.vhd similarity index 100% rename from cores/onewire_spare_one_tmpl.vhd rename to design/onewire_spare_one_tmpl.vhd diff --git a/source/ped_corr_ctrl.vhd b/design/ped_corr_ctrl.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/ped_corr_ctrl.vhd rename to design/ped_corr_ctrl.vhd diff --git a/source/ped_thr_mem.mem b/design/ped_thr_mem.mem similarity index 100% rename from source/ped_thr_mem.mem rename to design/ped_thr_mem.mem diff --git a/cores/ped_thr_true.lpc b/design/ped_thr_true.lpc similarity index 100% rename from cores/ped_thr_true.lpc rename to design/ped_thr_true.lpc diff --git a/cores/ped_thr_true.srp b/design/ped_thr_true.srp similarity index 100% rename from cores/ped_thr_true.srp rename to design/ped_thr_true.srp diff --git a/cores/ped_thr_true.vhd b/design/ped_thr_true.vhd similarity index 100% rename from cores/ped_thr_true.vhd rename to design/ped_thr_true.vhd diff --git a/cores/ped_thr_true_tmpl.vhd b/design/ped_thr_true_tmpl.vhd similarity index 100% rename from cores/ped_thr_true_tmpl.vhd rename to design/ped_thr_true_tmpl.vhd diff --git a/cores/pll_40m.lpc b/design/pll_40m.lpc similarity index 100% rename from cores/pll_40m.lpc rename to design/pll_40m.lpc diff --git a/cores/pll_40m.vhd b/design/pll_40m.vhd similarity index 100% rename from cores/pll_40m.vhd rename to design/pll_40m.vhd diff --git a/cores/pll_40m_tmpl.vhd b/design/pll_40m_tmpl.vhd similarity index 100% rename from cores/pll_40m_tmpl.vhd rename to design/pll_40m_tmpl.vhd diff --git a/source/pulse_stretch.vhd b/design/pulse_stretch.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/pulse_stretch.vhd rename to design/pulse_stretch.vhd diff --git a/source/pulse_sync.vhd b/design/pulse_sync.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/pulse_sync.vhd rename to design/pulse_sync.vhd diff --git a/source/raw_buf_stage.vhd b/design/raw_buf_stage.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/raw_buf_stage.vhd rename to design/raw_buf_stage.vhd diff --git a/source/real_trg_handler.vhd b/design/real_trg_handler.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/real_trg_handler.vhd rename to design/real_trg_handler.vhd diff --git a/design/real_trg_handler.vhd~ b/design/real_trg_handler.vhd~ new file mode 100755 index 0000000..36c0dc4 --- /dev/null +++ b/design/real_trg_handler.vhd~ @@ -0,0 +1,587 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.adcmv3_components.all; + +-- Comment: better than the first version, but still a lot of optimization possible. + +-- (1) no more compare tags here. some steps in the FSM can be taken out. +-- (2) no more rst_lvl1_counter signal anymore in the CCR. to be replaced! + +entity real_trg_handler is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse) + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint + TRG_TOO_LONG_OUT : out std_logic; -- only for TRG0 channel + SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number + -- TRB LVL1 channel signals + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 4bit trigger type + TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information + TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB + TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger + LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); + LVL1_COUNTER_IN : in std_logic_vector(15 downto 0); + LVL1_LD_COUNTER_IN : in std_logic; + BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator + -- + APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine + APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data + EDS_WE_OUT : out std_logic; -- EDS write enable (general interface) + EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level + EDS_READY_OUT : out std_logic; -- APV trigger sequence done + DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end; + +architecture behavioral of real_trg_handler is + +-- state machine signals +type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS, + WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG, TTLTRG); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- normal signals +signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs +signal trg_q : std_logic_vector(3 downto 0); +signal trg_qq : std_logic_vector(3 downto 0); +signal trg_qqq : std_logic_vector(3 downto 0); +signal trg_qqqq : std_logic_vector(3 downto 0); +signal trg_edge : std_logic_vector(3 downto 0); +signal decoded_trg : std_logic_vector(3 downto 0); +signal todo_start : std_logic_vector(3 downto 0); +signal trg_found : std_logic; + +signal evtctr : unsigned(15 downto 0); -- event counter +signal ce_evtctr : std_logic; +signal next_ce_evtctr : std_logic; +signal frmctr : unsigned(3 downto 0); -- frame counter +signal ce_frmctr : std_logic; +signal next_ce_frmctr : std_logic; +signal todo_ctr : unsigned(3 downto 0); +signal next_todo_done : std_logic; +signal todo_done : std_logic; +signal next_apv_trgstart : std_logic; +signal apv_trgstart : std_logic; +signal eds_data : std_logic_vector(39 downto 0); +signal eds_start : std_logic; +signal next_eds_start : std_logic; +signal eds_we : std_logic; +signal next_eds_we : std_logic; +signal next_eds_ready : std_logic; +signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff +signal apv_trg_finished : std_logic; +signal next_accept : std_logic; -- we can accept a trigger +signal accept : std_logic; +signal next_missed_trg : std_logic; +signal missed_trg : std_logic; +signal missing_trg : std_logic; +signal next_rst_status : std_logic; +signal rst_status : std_logic; + +signal time_trg : std_logic_vector(3 downto 0); + +-- Information to be collected for the EDS +signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit) +signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit) +signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit) + +signal next_store_local : std_logic; +signal store_local : std_logic; +signal next_rst_local : std_logic; +signal rst_local : std_logic; + +signal time_trg_on : std_logic_vector(3 downto 0); +signal time_trg_inv : std_logic_vector(3 downto 0); + +signal big_event_comb : std_logic; +signal tag_sector_match_comb : std_logic; +signal suppress_data_comb : std_logic; + +signal trg_len_ctr : unsigned(8 downto 0); -- 9bit = 5.12us max +signal trg_len_rst : std_logic; +signal trg_len_ce : std_logic; +signal trg_len_done : std_logic; +signal trg_too_long : std_logic; + +signal bsm_x : std_logic_vector(7 downto 0); + +begin + +-- Aliasing the control bits +time_trg_on(3) <= TRG_SETUP_IN(7); +time_trg_inv(3) <= TRG_SETUP_IN(3); +time_trg_on(2) <= TRG_SETUP_IN(6); +time_trg_inv(2) <= TRG_SETUP_IN(2); +time_trg_on(1) <= TRG_SETUP_IN(5); +time_trg_inv(1) <= TRG_SETUP_IN(1); +time_trg_on(0) <= TRG_SETUP_IN(4); +time_trg_inv(0) <= TRG_SETUP_IN(0); + +------------------------------------------------------------ +-- Synchronize the external trigger inputs +------------------------------------------------------------ +THE_TIME_TRG_3_SYNC: state_sync +port map( + STATE_A_IN => TIME_TRG_IN(3), + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + STATE_B_OUT => time_trg(3) +); +THE_TIME_TRG_2_SYNC: state_sync +port map( + STATE_A_IN => TIME_TRG_IN(2), + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + STATE_B_OUT => time_trg(2) +); +THE_TIME_TRG_1_SYNC: state_sync +port map( + STATE_A_IN => TIME_TRG_IN(1), + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + STATE_B_OUT => time_trg(1) +); +THE_TIME_TRG_0_SYNC: state_sync +port map( + STATE_A_IN => TIME_TRG_IN(0), + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + STATE_B_OUT => time_trg(0) +); + +------------------------------------------------------------ +-- For all four possible hardware triggers we combine hardware and TRB inputs +-- TRB slow control trigger inputs are already synchronized to SYSCLK. +------------------------------------------------------------ +trg_comb(3) <= ((time_trg(3) xor time_trg_inv(3)) and time_trg_on(3)) or TRB_TRG_IN(3); +trg_comb(2) <= ((time_trg(2) xor time_trg_inv(2)) and time_trg_on(2)) or TRB_TRG_IN(2); +trg_comb(1) <= ((time_trg(1) xor time_trg_inv(1)) and time_trg_on(1)) or TRB_TRG_IN(1); +trg_comb(0) <= ((time_trg(0) xor time_trg_inv(0)) and time_trg_on(0)) or TRB_TRG_IN(0); + +-------------------------------------------------------------------------------------------------- +-- trigger length surveillance +-------------------------------------------------------------------------------------------------- +THE_TRG_LENGTH_CTR_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if ( (RESET_IN = '1') or (trg_len_rst = '1') ) then + trg_len_ctr <= (others => '0'); + elsif( trg_len_ce = '1' ) then + trg_len_ctr <= trg_len_ctr + 1; + end if; + end if; +end process THE_TRG_LENGTH_CTR_PROC; + +-- Count whenever trigger signal is high +trg_len_ce <= trg_qqqq(0); +-- Reset counter with each rising edge +trg_len_rst <= trg_edge(0); +-- Overflow of counter marks trigger length > 5us +trg_len_done <= '1' when (trg_len_ctr = b"1_1111_1111") else '0'; + +THE_TRG_TOO_LONG_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if ( (RESET_IN = '1') or (trg_len_rst = '1') ) then + trg_too_long <= '0'; + elsif( trg_len_done = '1' ) then + trg_too_long <= '1'; + end if; + end if; +end process THE_TRG_TOO_LONG_PROC; + +-------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------- + +------------------------------------------------------------ +-- Now we shift the synced signals into shift registers with four FF in a row. +-- This gives us a 16bit pattern in total to decide which trigger input was active. +------------------------------------------------------------ +THE_TRG_LENGTH_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + trg_qqqq <= (others => '0'); + trg_qqq <= (others => '0'); + trg_qq <= (others => '0'); + trg_q <= (others => '0'); + else + trg_qqqq <= trg_qqq; + trg_qqq <= trg_qq; + trg_qq <= trg_q; + trg_q <= trg_comb; + end if; + end if; +end process THE_TRG_LENGTH_PROC; + +------------------------------------------------------------ +-- Check for rising edges in the signals, with a long steady state signal following. +-- We accept only signals of three clock cycles minimum length (as sent by the TRB_TRG). +------------------------------------------------------------ +THE_RISING_EDGES_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + trg_edge <= (others => '0'); + else + trg_edge(3) <= not trg_qqqq(3) and trg_qqq(3) and trg_qq(3) and trg_q(3); + trg_edge(2) <= not trg_qqqq(2) and trg_qqq(2) and trg_qq(2) and trg_q(2); + trg_edge(1) <= not trg_qqqq(1) and trg_qqq(1) and trg_qq(1) and trg_q(1); + trg_edge(0) <= not trg_qqqq(0) and trg_qqq(0) and trg_qq(0) and trg_q(0); + end if; + end if; +end process THE_RISING_EDGES_PROC; + +-- Now we are almost done. +-- The detected edges are priorized. +THE_TRG_PRIORITY_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + decoded_trg <= (others => '0'); + todo_start <= (others => '0'); + trg_found <= '0'; + else + if( trg_edge(3) = '1' ) then + decoded_trg <= "1000"; + todo_start <= TRG_3_TODO_IN; + trg_found <= '1'; + elsif( trg_edge(3 downto 2) = "01" ) then + decoded_trg <= "0100"; + todo_start <= TRG_2_TODO_IN; + trg_found <= '1'; + elsif( trg_edge(3 downto 1) = "001" ) then + decoded_trg <= "0010"; + todo_start <= TRG_1_TODO_IN; + trg_found <= '1'; + elsif( trg_edge(3 downto 0) = "0001" ) then + decoded_trg <= "0001"; + todo_start <= TRG_0_TODO_IN; + trg_found <= '1'; + else + -- case of "timingtriggerless trigger"? + decoded_trg <= "0000"; + todo_start <= "0000"; + trg_found <= '0'; + end if; + end if; + end if; +end process THE_TRG_PRIORITY_PROC; + +-- We need to store some information for the EDS... from local counters +-- NB: after one cycle this information set is reset to zero! +-- needed for missing timing trigger handling. +THE_LOCALSTORE_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( (RESET_IN = '1') or (rst_local = '1') ) then + trg_frmctr_reg <= (others => '0'); + trg_frmnum_reg <= (others => '0'); + trg_dectrg_reg <= (others => '0'); + elsif( (accept = '1') and (trg_found = '1') ) then -- the clock cycle before local_store pulse + trg_frmctr_reg <= std_logic_vector(frmctr); + trg_frmnum_reg <= todo_start; + trg_dectrg_reg <= decoded_trg; + end if; + end if; +end process THE_LOCALSTORE_PROC; + +-- The ToDo counter: is loaded with the number of APV triggers, and counts down. +THE_TODO_COUNTER_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if ( RESET_IN = '1' ) then + todo_ctr <= (others => '0'); + elsif( store_local = '1' ) then + todo_ctr <= unsigned(trg_frmnum_reg); + elsif( ce_frmctr = '1' ) then + todo_ctr <= todo_ctr - 1; + end if; + end if; +end process THE_TODO_COUNTER_PROC; +next_todo_done <= '1' when (todo_ctr = x"0") else '0'; + +THE_TRG_SYNC_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + todo_done <= '0'; + else + todo_done <= next_todo_done; + end if; + end if; +end process THE_TRG_SYNC_PROC; + +-- We store the end pulse from the APV trigger handler, as we need to wait for +-- LVL1 in any case before we can take care of this signal. +THE_TRGDONE_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + apv_trg_finished <= '0'; + elsif( APV_TRGDONE_IN = '1' ) then + apv_trg_finished <= '1'; + elsif( eds_ready = '1' ) then + apv_trg_finished <= '0'; + end if; + end if; +end process THE_TRGDONE_PROC; + +-- A statemachine handles all actions for filling out the trigger information sheet +-- state registers +STATE_MEM: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + CURRENT_STATE <= SLEEP; + ce_evtctr <= '0'; + ce_frmctr <= '0'; + eds_ready <= '0'; + eds_we <= '0'; + eds_start <= '0'; + rst_local <= '0'; + store_local <= '0'; + apv_trgstart <= '0'; + accept <= '1'; + missed_trg <= '0'; + rst_status <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + ce_evtctr <= next_ce_evtctr; + ce_frmctr <= next_ce_frmctr; + eds_ready <= next_eds_ready; + eds_we <= next_eds_we; + eds_start <= next_eds_start; + rst_local <= next_rst_local; + store_local <= next_store_local; + apv_trgstart <= next_apv_trgstart; + accept <= next_accept; + missed_trg <= next_missed_trg; + rst_status <= next_rst_status; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, TRB_TRGRCVD_IN, apv_trg_finished, + BUSY_RELEASE_IN, TRB_TTYPE_IN(3), TRB_TINFO_IN(7) ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + next_ce_evtctr <= '0'; + next_ce_frmctr <= '0'; + next_eds_ready <= '0'; + next_eds_we <= '0'; + next_eds_start <= '0'; + next_rst_local <= '0'; + next_store_local <= '0'; + next_apv_trgstart <= '0'; + next_accept <= '0'; + next_missed_trg <= '0'; + next_rst_status <= '0'; + case CURRENT_STATE is + -- not good. if no timing trigger was received but a trb trigger arrives, we must do something! + when SLEEP => if ( trg_found = '1' ) then + -- normal way: timing trigger found + NEXT_STATE <= STORE; + next_store_local <= '1'; + next_eds_start <= '1'; + elsif( (trg_found = '0') and (TRB_TRGRCVD_IN = '1') and (TRB_TTYPE_IN(3) = '1') and (TRB_TINFO_IN(7) = '1') ) then + NEXT_STATE <= TTLTRG; + elsif( (trg_found = '0') and (TRB_TRGRCVD_IN = '1') and ((TRB_TTYPE_IN(3) = '0') or (TRB_TINFO_IN(7) = '0')) ) then + NEXT_STATE <= BADTRG; + next_missed_trg <= '1'; + else + NEXT_STATE <= SLEEP; + next_accept <= '1'; + end if; + when TTLTRG => NEXT_STATE <= TRBS; + when BADTRG => NEXT_STATE <= TRBS; + when STORE => NEXT_STATE <= START; + next_apv_trgstart <= '1'; + when START => NEXT_STATE <= CHECK; + when CHECK => if( todo_done = '1' ) then + NEXT_STATE <= WAPV; + else + NEXT_STATE <= COUNT; + next_ce_frmctr <= '1'; + end if; + when COUNT => NEXT_STATE <= RELAX; + when RELAX => NEXT_STATE <= CHECK; + when WAPV => if( apv_trg_finished = '1' ) then + NEXT_STATE <= WLVL1; + else + NEXT_STATE <= WAPV; + end if; + when WLVL1 => if( TRB_TRGRCVD_IN = '1' ) then + NEXT_STATE <= TRBS; + else + NEXT_STATE <= WLVL1; + end if; + when TRBS => NEXT_STATE <= WEDS; + next_eds_we <= '1'; + next_rst_local <= '1'; + when WEDS => NEXT_STATE <= CNTEVT; + next_ce_evtctr <= '1'; + when CNTEVT => NEXT_STATE <= WDEL0; + when WDEL0 => NEXT_STATE <= WDEL1; + when WDEL1 => NEXT_STATE <= WBUSY; + when WBUSY => if( BUSY_RELEASE_IN = '1' ) then + NEXT_STATE <= DONE; + next_eds_ready <= '1'; + else + NEXT_STATE <= WBUSY; + end if; + when DONE => if( TRB_TRGRCVD_IN = '0' ) then -- mind the state synchronizer delay!!! + NEXT_STATE <= SLEEP; + next_accept <= '1'; + next_rst_status <= '1'; + else + NEXT_STATE <= DONE; + end if; + when others => NEXT_STATE <= SLEEP; + next_accept <= '1'; + end case; +end process STATE_TRANSFORM; + +-- state decoding +STATE_DECODE: process( CURRENT_STATE ) +begin + case CURRENT_STATE is + when SLEEP => bsm_x <= x"00"; + when STORE => bsm_x <= x"01"; + when START => bsm_x <= x"02"; + when CHECK => bsm_x <= x"03"; + when COUNT => bsm_x <= x"04"; + when RELAX => bsm_x <= x"14"; + when WAPV => bsm_x <= x"05"; + when WLVL1 => bsm_x <= x"06"; + when TRBS => bsm_x <= x"07"; + when WEDS => bsm_x <= x"0b"; + when WDEL0 => bsm_x <= x"0c"; + when WDEL1 => bsm_x <= x"0d"; + when WBUSY => bsm_x <= x"0e"; + when DONE => bsm_x <= x"0f"; + when CNTEVT => bsm_x <= x"10"; + when BADTRG => bsm_x <= x"11"; + when TTLTRG => bsm_x <= x"12"; + when others => bsm_x <= x"ff"; + end case; +end process STATE_DECODE; + + +-- The event counter: is incremented with each accepted trigger +THE_EVENT_COUNTER_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if ( RESET_IN = '1' ) then + evtctr <= (others => '0'); + elsif( LVL1_LD_COUNTER_IN = '1' ) then + evtctr <= unsigned(LVL1_COUNTER_IN); -- update with value from TRBnet counter + elsif( ce_evtctr = '1' ) then + evtctr <= evtctr + 1; + end if; + end if; +end process THE_EVENT_COUNTER_PROC; + +-- The frame counter: is incremented with each 1-0-0 trigger sent to APV +THE_FRAME_COUNTER_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + frmctr <= (others => '0'); + elsif( ce_frmctr = '1' ) then + frmctr <= frmctr + 1; + end if; + end if; +end process THE_FRAME_COUNTER_PROC; + +-- If a timing trigger was missing, we simply ignore this LVL1 trigger +THE_MISSED_TRG_REG: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( (RESET_IN = '1') or (rst_status = '1') ) then + missing_trg <= '0'; + elsif( missed_trg = '1' ) then + missing_trg <= '1'; + end if; + end if; +end process THE_MISSED_TRG_REG; + +-- Now for something completely different: as we have two sectors connected +-- to one GbE hub in the final setup, we must do a trick to stay below 64kB +-- subevent size. +-- So in all cases where 128 channels per event are requested, only those ADCM +-- will produce data where the last bit of sector number and trigger number matches. +-- I.e.: odd sectors fire on odd trigger numbers, even sectors on even trigger numbers. + +-- potentially dangerous (aka big) event +big_event_comb <= '1' when (TRB_TINFO_IN(10 downto 8) = b"000") or -- RAW128 + (TRB_TINFO_IN(10 downto 8) = b"001") or -- PED128 + (TRB_TINFO_IN(10 downto 8) = b"010") or -- PED128THR + (TRB_TINFO_IN(10 downto 8) = b"100") -- NC64PED64 + else '0'; + +-- sector number matches trigger number +tag_sector_match_comb <= '1' when ( SECTOR_IN(0) = TRB_TTAG_IN(0) ) else '0'; + +-- when to drop data +suppress_data_comb <= (big_event_comb and not tag_sector_match_comb) or TRB_TINFO_IN(0); + +-- EDS bits: +eds_data(39 downto 36) <= trg_frmctr_reg; +eds_data(35 downto 32) <= trg_frmnum_reg; +eds_data(31 downto 16) <= TRB_TTAG_IN; +eds_data(15 downto 8) <= TRB_TRND_IN; +eds_data(7 downto 4) <= TRB_TTYPE_IN; +eds_data(3) <= suppress_data_comb; --trb_tinfo_in(0); -- suppress output bit +eds_data(2 downto 0) <= TRB_TINFO_IN(10 downto 8); -- RICH data configuration bits + +-- output signals +APV_TRGSTART_OUT <= apv_trgstart; +APV_TRGSEL_OUT <= trg_dectrg_reg; + +EDS_DATA_OUT <= eds_data; +EDS_START_OUT <= eds_start; +EDS_WE_OUT <= eds_we; +EDS_READY_OUT <= eds_ready; +TRB_MISSING_OUT <= missing_trg; +LVL1_COUNTER_OUT <= std_logic_vector(evtctr); +TRG_FOUND_OUT <= trg_found; +TRG_TOO_LONG_OUT <= trg_too_long; + +-- Debug signals +BSM_OUT <= bsm_x; + +DEBUG_OUT(63 downto 32) <= (others => '0'); +DEBUG_OUT(31 downto 24) <= std_logic_vector(evtctr(7 downto 0)); +DEBUG_OUT(23 downto 16) <= TRB_TTAG_IN(7 downto 0); +DEBUG_OUT(15) <= ce_evtctr; +DEBUG_OUT(14) <= '0'; +DEBUG_OUT(13) <= missing_trg; +DEBUG_OUT(12) <= accept; +DEBUG_OUT(11) <= '0'; +DEBUG_OUT(10) <= '0'; +DEBUG_OUT(9) <= TRB_TRGRCVD_IN; +DEBUG_OUT(8) <= trg_found; +DEBUG_OUT(7 downto 0) <= bsm_x; + +DBG_FRMCTR_OUT <= std_logic_vector(frmctr); + +end behavioral; + diff --git a/source/real_trg_handler_BACKUP.vhd b/design/real_trg_handler_BACKUP.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/real_trg_handler_BACKUP.vhd rename to design/real_trg_handler_BACKUP.vhd diff --git a/source/reboot_handler.vhd b/design/reboot_handler.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/reboot_handler.vhd rename to design/reboot_handler.vhd diff --git a/source/ref_row_sel.vhd b/design/ref_row_sel.vhd similarity index 100% rename from source/ref_row_sel.vhd rename to design/ref_row_sel.vhd diff --git a/source/replacement.vhd b/design/replacement.vhd similarity index 100% rename from source/replacement.vhd rename to design/replacement.vhd diff --git a/source/reset_handler.vhd b/design/reset_handler.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/reset_handler.vhd rename to design/reset_handler.vhd diff --git a/source/rich_trb.vhd b/design/rich_trb.vhd old mode 100644 new mode 100755 similarity index 96% rename from source/rich_trb.vhd rename to design/rich_trb.vhd index 8dc794e..960127c --- a/source/rich_trb.vhd +++ b/design/rich_trb.vhd @@ -24,8 +24,8 @@ port( SD_LOS_IN : in std_logic; ONEWIRE_INOUT : inout std_logic; -- common regIO status / control registers - COMMON_STAT_REG_IN : in std_logic_vector(8*32-1 downto 0); -- common status register, bit definitions like in WIKI - COMMON_CTRL_REG_OUT : out std_logic_vector(3*32-1 downto 0); -- common control register, bit definitions like in WIKI + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI -- status register input to regIO / control register output from regIO CONTROL_OUT : out std_logic_vector(63 downto 0); STATUS_IN : in std_logic_vector(127 downto 0); @@ -208,7 +208,7 @@ generic map( REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", REGIO_INIT_ENDPOINT_ID => x"0001", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), - -- REGIO_COMPILE_VERSION => x"0003", + REGIO_COMPILE_VERSION => x"0003", REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature REGIO_USE_1WIRE_INTERFACE => c_YES, TIMING_TRIGGER_RAW => c_YES, @@ -229,8 +229,7 @@ port map( MED_READ_OUT => med_read_out_int, MED_STAT_OP_IN => med_stat_op, MED_CTRL_OP_OUT => med_ctrl_op, - - -- LVL1 trigger APL + -- LVL1 trigger APL LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...) @@ -243,8 +242,7 @@ port map( LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint - - -- IPU Port + -- IPU Port IPU_NUMBER_OUT => IPU_NUMBER_OUT, IPU_READOUT_TYPE_OUT => open, -- 4bit readout type IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, @@ -255,8 +253,7 @@ port map( IPU_READ_OUT => IPU_READ_OUT, IPU_LENGTH_IN => IPU_LENGTH_IN, IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN, - - -- Slow Control Data Port + -- Slow Control Data Port REGIO_COMMON_STAT_REG_IN => common_stat_reg, REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, REGIO_REGISTERS_IN => regio_stat_regs, @@ -265,8 +262,7 @@ port map( COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number STAT_REG_STROBE => open, CTRL_REG_STROBE => open, - - --following ports only used when using internal data port + --following ports only used when using internal data port REGIO_ADDR_OUT => REGIO_ADDR_OUT, REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, @@ -277,8 +273,7 @@ port map( REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, - - --IDRAM is used if no 1-wire interface, onewire used otherwise + --IDRAM is used if no 1-wire interface, onewire used otherwise REGIO_IDRAM_DATA_IN => x"0000", -- not used REGIO_IDRAM_DATA_OUT => open, -- not used REGIO_IDRAM_ADDR_IN => "000", -- not used @@ -286,15 +281,13 @@ port map( REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT, REGIO_ONEWIRE_MONITOR_IN => '1', -- not used REGIO_ONEWIRE_MONITOR_OUT => open, -- not used - - -- New stuff + -- New stuff GLOBAL_TIME_OUT => open, LOCAL_TIME_OUT => open, TIME_SINCE_LAST_TRG_OUT => open, TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks TIMER_TICKS_OUT(0) => open, -- us ticks - - -- Status and debug + -- Status and debug STAT_DEBUG_IPU => open, STAT_DEBUG_1 => stat_debug_1, --open, STAT_DEBUG_2 => open, diff --git a/design/rich_trb.vhd~ b/design/rich_trb.vhd~ new file mode 100755 index 0000000..9325caf --- /dev/null +++ b/design/rich_trb.vhd~ @@ -0,0 +1,350 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.ALL; +use IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.version.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.adcmv3_components.all; + +entity rich_trb is +port( + CLK100M_IN : in std_logic; -- SerDes exclusive clock + SYSCLK_IN : in std_logic; -- fabric clock + RESET_IN : in std_logic; -- synchronous reset + -- SFP connections + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_PRESENT_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; + SD_LOS_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic; + -- common regIO status / control registers + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI + -- status register input to regIO / control register output from regIO + CONTROL_OUT : out std_logic_vector(63 downto 0); + STATUS_IN : in std_logic_vector(127 downto 0); + -- LVL1 signals + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_IN : in std_logic; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_INT_TRG_UPDATE_OUT : out std_logic; + TIMING_TRG_FOUND_IN : in std_logic; + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_OUT : out std_logic; -- gimme data! + IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_IN : in std_logic; -- data is valid + IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM + IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle + IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern + -- regIO bus + REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATAREADY_IN : in std_logic; + REGIO_NO_MORE_DATA_IN : in std_logic; + REGIO_WRITE_ACK_IN : in std_logic; + REGIO_UNKNOWN_ADDR_IN : in std_logic; + REGIO_TIMEOUT_OUT : out std_logic; + -- status LEDs + LED_LINK_STAT : out std_logic; + LED_LINK_TXD : out std_logic; + LED_LINK_RXD : out std_logic; + LINK_BSM_OUT : out std_logic_vector(3 downto 0); + RESET_OUT : out std_logic; + TICK_10S_OUT : out std_logic; + -- Debug + DEBUG : out std_logic_vector(63 downto 0) +); +end entity; + +architecture rich_arch of rich_trb is + +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of rich_arch : architecture is "RICH_TRB_group"; + +-- Signals +signal clk_en : std_logic; +signal med_data_in_int : std_logic_vector(c_DATA_WIDTH-1 downto 0); +signal med_packet_num_in_int : std_logic_vector(c_NUM_WIDTH-1 downto 0); +signal med_dataready_in_int : std_logic; +signal med_read_out_int : std_logic; +signal med_data_out_int : std_logic_vector(c_DATA_WIDTH-1 downto 0); +signal med_packet_num_out_int : std_logic_vector(c_NUM_WIDTH-1 downto 0); +signal med_dataready_out_int : std_logic; +signal med_read_in_int : std_logic; +signal med_stat_debug : std_logic_vector(63 downto 0); +signal med_ctrl_op : std_logic_vector(15 downto 0); +signal med_stat_op : std_logic_vector(15 downto 0); + +-- general purpose control and status registers in regIO +signal regio_ctrl_regs : std_logic_vector(32*2-1 downto 0); +signal regio_stat_regs : std_logic_vector(32*4-1 downto 0); + +signal common_stat_reg : std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); +signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); +signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + +signal debug_x : std_logic_vector(63 downto 0); + +signal stat_debug_1 : std_logic_vector(31 downto 0); + +signal tick_1ms : std_logic; +signal counter_10s : unsigned(13 downto 0); +signal next_rst_counter_10s : std_logic; +signal rst_counter_10s : std_logic; +signal ce_counter_10s : std_logic; +signal next_tick_10s : std_logic; +signal tick_10s : std_logic; + +begin + +-- Debug +debug <= debug_x; + +-- Clock assignment. We don't use CLK_EN really in our designs. +clk_en <= '1'; + +------------------------------------------------------------------------------------ +-- Serdes +------------------------------------------------------------------------------------ +THE_MEDIA_INTERFACE : trb_net16_med_ecp_sfp_gbe +generic map( + SERDES_NUM => 2 +) +port map( + CLK => CLK100M_IN, + SYSCLK => SYSCLK_IN, + RESET => RESET_IN, + CLEAR => '0', + CLK_EN => clk_en, + --Internal Connection + MED_DATA_IN => med_data_out_int, + MED_PACKET_NUM_IN => med_packet_num_out_int, + MED_DATAREADY_IN => med_dataready_out_int, + MED_READ_OUT => med_read_in_int, + MED_DATA_OUT => med_data_in_int, + MED_PACKET_NUM_OUT => med_packet_num_in_int, + MED_DATAREADY_OUT => med_dataready_in_int, + MED_READ_IN => med_read_out_int, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SD_RXD_P_IN, + SD_RXD_N_IN => SD_RXD_N_IN, + SD_TXD_P_OUT => SD_TXD_P_OUT, + SD_TXD_N_OUT => SD_TXD_N_OUT, + SD_REFCLK_P_IN => '1', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => SD_PRESENT_IN, + SD_LOS_IN => SD_LOS_IN, + SD_TXDIS_OUT => SD_TXDIS_OUT, + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, -- input + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') +); + +------------------------------------------------------------------------------------ +-- Debug signals +------------------------------------------------------------------------------------ +debug_x(63 downto 47) <= med_stat_debug(63 downto 47); +debug_x(46 downto 42) <= (others => '0'); +debug_x(41) <= med_read_out_int; -- MED_READ_IN +debug_x(40) <= med_dataready_in_int; -- MED_DATAREADY_OUT +debug_x(39 downto 37) <= med_packet_num_in_int; -- MED_PACKET_NUM_OUT +debug_x(36 downto 21) <= med_data_in_int; -- MED_DATA_OUT +debug_x(20) <= med_read_in_int; -- MED_READ_OUT +debug_x(19) <= med_dataready_out_int; -- MED_DATAREADY_IN +debug_x(18 downto 16) <= med_packet_num_out_int; -- MED_PACKET_NUM_IN +--debug_x(15 downto 0) <= med_data_out; -- MED_DATA_IN +debug_x(15 downto 7) <= (others => '0'); +debug_x(6 downto 0) <= med_stat_debug(30 downto 24); + +------------------------------------------------------------------------------------ +-- Full featured HADES endpoint +------------------------------------------------------------------------------------ +THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full +generic map( + USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), + INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before? + REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES), + REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO), + BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts + REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] + REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] + --standard values for output registers + REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000", + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS => "0000000000000001", + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", + REGIO_USE_DAT_PORT => c_YES, + REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register! + REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f", + REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + REGIO_COMPILE_VERSION => x"0003", + REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature + REGIO_USE_1WIRE_INTERFACE => c_YES, + CLOCK_FREQUENCY => 100 +) +port map( + CLK => SYSCLK_IN, + RESET => RESET_IN, + CLK_EN => clk_en, + -- Media direction port + MED_DATAREADY_OUT => med_dataready_out_int, + MED_DATA_OUT => med_data_out_int, + MED_PACKET_NUM_OUT => med_packet_num_out_int, + MED_READ_IN => med_read_in_int, + MED_DATAREADY_IN => med_dataready_in_int, + MED_DATA_IN => med_data_in_int, + MED_PACKET_NUM_IN => med_packet_num_in_int, + MED_READ_OUT => med_read_out_int, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + -- LVL1 trigger APL + LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received + LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received + LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT, + TRG_TIMING_TRG_RECEIVED_IN => TIMING_TRG_FOUND_IN, + LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT, + LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT, + LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT, + LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT, + LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, + LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, + LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint + -- IPU Port + IPU_NUMBER_OUT => IPU_NUMBER_OUT, + IPU_READOUT_TYPE_OUT => open, -- 4bit readout type + IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, + IPU_START_READOUT_OUT => IPU_START_READOUT_OUT, + IPU_DATA_IN => IPU_DATA_IN, + IPU_DATAREADY_IN => IPU_DATAREADY_IN, + IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN, + IPU_READ_OUT => IPU_READ_OUT, + IPU_LENGTH_IN => IPU_LENGTH_IN, + IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN, + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, + REGIO_REGISTERS_IN => regio_stat_regs, + REGIO_REGISTERS_OUT => regio_ctrl_regs, + COMMON_STAT_REG_STROBE => open, + COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number + STAT_REG_STROBE => open, + CTRL_REG_STROBE => open, + --following ports only used when using internal data port + REGIO_ADDR_OUT => REGIO_ADDR_OUT, + REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, + REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, + REGIO_DATA_OUT => REGIO_DATA_OUT, + REGIO_DATA_IN => REGIO_DATA_IN, + REGIO_DATAREADY_IN => REGIO_DATAREADY_IN, + REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN, + REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, + REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, + REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN => x"0000", -- not used + REGIO_IDRAM_DATA_OUT => open, -- not used + REGIO_IDRAM_ADDR_IN => "000", -- not used + REGIO_IDRAM_WR_IN => '0', -- not used + REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT, + REGIO_ONEWIRE_MONITOR_IN => '1', -- not used + REGIO_ONEWIRE_MONITOR_OUT => open, -- not used + -- New stuff + GLOBAL_TIME_OUT => open, + LOCAL_TIME_OUT => open, + TIME_SINCE_LAST_TRG_OUT => open, + TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks + TIMER_TICKS_OUT(0) => open, -- us ticks + -- Status and debug + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => stat_debug_1, --open, + STAT_DEBUG_2 => open, + MED_STAT_OP => open, + CTRL_MPLEX => x"00000000", + IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000", + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open +); + +------------------------------------------------------------------------------------ +-- 10s counter +------------------------------------------------------------------------------------ +THE_TEN_SEC_CTR_PROC: process( SYSCLK_IN ) +begin + if( rising_edge(SYSCLK_IN) ) then + if ( rst_counter_10s = '1' ) then + counter_10s <= (others => '0'); + elsif( ce_counter_10s = '1' ) then + counter_10s <= counter_10s + 1; + end if; + rst_counter_10s <= next_rst_counter_10s; + tick_10s <= next_tick_10s; + end if; +end process THE_TEN_SEC_CTR_PROC; + +ce_counter_10s <= tick_1ms; + +next_rst_counter_10s <= '1' when (((counter_10s = 9765) and (ce_counter_10s = '1')) or (RESET_IN = '1')) else '0'; + +next_tick_10s <= rst_counter_10s; + +------------------------------------------------------------------------------------ +-- Control register assignment +------------------------------------------------------------------------------------ + +-- Common status register +common_stat_reg(COMMON_STAT_REG'left downto 32) <= COMMON_STAT_REG_IN(63 downto 32); +common_stat_reg(31 downto 20) <= (others => '0'); -- already taken by TEMP of 1WID +common_stat_reg(19 downto 0) <= COMMON_STAT_REG_IN(19 downto 0); + +-- Common control register +COMMON_CTRL_REG_OUT <= common_ctrl_reg; + +-- User status register +regio_stat_regs <= STATUS_IN; +CONTROL_OUT <= regio_ctrl_regs; +LVL1_INT_TRG_UPDATE_OUT <= common_ctrl_reg_strobe(1); +LVL1_INT_TRG_NUMBER_OUT <= common_ctrl_reg(47 downto 32); + +-- FPGA LEDs +LED_LINK_STAT <= not med_stat_op(9); -- link status +LED_LINK_RXD <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive +LED_LINK_TXD <= not med_stat_op(11); -- data transmit + +-- Output signals +LINK_BSM_OUT <= med_stat_op(7 downto 4); -- LSM state bits +RESET_OUT <= med_stat_op(13); -- TRB generated reset + +end architecture; + \ No newline at end of file diff --git a/source/sbuf.vhd b/design/sbuf.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/sbuf.vhd rename to design/sbuf.vhd diff --git a/source/sfp_rx_handler.vhd b/design/sfp_rx_handler.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/sfp_rx_handler.vhd rename to design/sfp_rx_handler.vhd diff --git a/source/sfp_rx_handler_BACK2.vhd b/design/sfp_rx_handler_BACK2.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/sfp_rx_handler_BACK2.vhd rename to design/sfp_rx_handler_BACK2.vhd diff --git a/source/sfp_rx_handler_BACK_0.vhd b/design/sfp_rx_handler_BACK_0.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/sfp_rx_handler_BACK_0.vhd rename to design/sfp_rx_handler_BACK_0.vhd diff --git a/source/slave_bus.vhd b/design/slave_bus.vhd old mode 100644 new mode 100755 similarity index 72% rename from source/slave_bus.vhd rename to design/slave_bus.vhd index 93b64ca..be178b9 --- a/source/slave_bus.vhd +++ b/design/slave_bus.vhd @@ -169,16 +169,13 @@ end entity; architecture Behavioral of slave_bus is -- Signals -constant NUM_PORTS : integer := 18; -signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); -signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); +signal slv_read : std_logic_vector(18-1 downto 0); +signal slv_write : std_logic_vector(18-1 downto 0); signal slv_busy : std_logic_vector(18-1 downto 0); -signal slv_no_more_data : std_logic_vector(NUM_PORTS-1 downto 0); -signal slv_ack : std_logic_vector(NUM_PORTS-1 downto 0); -signal slv_addr : std_logic_vector(NUM_PORTS*16-1 downto 0); -signal slv_data_rd : std_logic_vector(NUM_PORTS*32-1 downto 0); -signal slv_data_wr : std_logic_vector(NUM_PORTS*32-1 downto 0); -signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0); +signal slv_ack : std_logic_vector(18-1 downto 0); +signal slv_addr : std_logic_vector(18*16-1 downto 0); +signal slv_data_rd : std_logic_vector(18*32-1 downto 0); +signal slv_data_wr : std_logic_vector(18*32-1 downto 0); -- SPI controller BRAM lines signal spi_bram_addr : std_logic_vector(7 downto 0); @@ -204,7 +201,7 @@ begin -- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus THE_BUS_HANDLER: trb_net16_regio_bus_handler generic map( - PORT_NUMBER => NUM_PORTS, + PORT_NUMBER => 18, PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories 1 => x"a800", -- threshold memories 2 => x"8040", -- I2C master @@ -242,9 +239,8 @@ generic map( 15 => 4, -- FIFO status registers 16 => 0, -- LVL1 release status register 17 => 0, -- IPU handler status register - others => 0), - PORT_MASK_ENABLE => 1 - ) + others => 0) +) port map( CLK => CLK_IN, RESET => RESET_IN, @@ -258,22 +254,185 @@ port map( DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT, DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT, DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT, - - -- All Slow Control Ports - BUS_READ_ENABLE_OUT => slv_read, - BUS_WRITE_ENABLE_OUT => slv_write, - BUS_DATA_OUT => slv_data_wr, - BUS_DATA_IN => slv_data_rd, - BUS_ADDR_OUT => slv_addr, - BUS_TIMEOUT_OUT => open, - BUS_DATAREADY_IN => slv_ack, - BUS_WRITE_ACK_IN => slv_ack, - BUS_NO_MORE_DATA_IN => slv_no_more_data, - BUS_UNKNOWN_ADDR_IN => slv_unknown_addr, - + -- pedestal memories + BUS_READ_ENABLE_OUT(0) => slv_read(0), + BUS_WRITE_ENABLE_OUT(0) => slv_write(0), + BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32), + BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), + BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16), + BUS_TIMEOUT_OUT(0) => open, + BUS_DATAREADY_IN(0) => slv_ack(0), + BUS_WRITE_ACK_IN(0) => slv_ack(0), + BUS_NO_MORE_DATA_IN(0) => slv_busy(0), + BUS_UNKNOWN_ADDR_IN(0) => '0', + -- threshold memories + BUS_READ_ENABLE_OUT(1) => slv_read(1), + BUS_WRITE_ENABLE_OUT(1) => slv_write(1), + BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32), + BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), + BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16), + BUS_TIMEOUT_OUT(1) => open, + BUS_DATAREADY_IN(1) => slv_ack(1), + BUS_WRITE_ACK_IN(1) => slv_ack(1), + BUS_NO_MORE_DATA_IN(1) => slv_busy(1), + BUS_UNKNOWN_ADDR_IN(1) => '0', + -- I2C master + BUS_READ_ENABLE_OUT(2) => slv_read(2), + BUS_WRITE_ENABLE_OUT(2) => slv_write(2), + BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), + BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), + BUS_ADDR_OUT(2*16+15 downto 2*16) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATAREADY_IN(2) => slv_ack(2), + BUS_WRITE_ACK_IN(2) => slv_ack(2), + BUS_NO_MORE_DATA_IN(2) => slv_busy(2), + BUS_UNKNOWN_ADDR_IN(2) => '0', + -- OneWire master + BUS_READ_ENABLE_OUT(3) => slv_read(3), + BUS_WRITE_ENABLE_OUT(3) => slv_write(3), + BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32), + BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), + BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16), + BUS_TIMEOUT_OUT(3) => open, + BUS_DATAREADY_IN(3) => slv_ack(3), + BUS_WRITE_ACK_IN(3) => slv_ack(3), + BUS_NO_MORE_DATA_IN(3) => slv_busy(3), + BUS_UNKNOWN_ADDR_IN(3) => '0', + -- SPI control registers + BUS_READ_ENABLE_OUT(4) => slv_read(4), + BUS_WRITE_ENABLE_OUT(4) => slv_write(4), + BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32), + BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), + BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16), + BUS_TIMEOUT_OUT(4) => open, + BUS_DATAREADY_IN(4) => slv_ack(4), + BUS_WRITE_ACK_IN(4) => slv_ack(4), + BUS_NO_MORE_DATA_IN(4) => slv_busy(4), + BUS_UNKNOWN_ADDR_IN(4) => '0', + -- SPI data memory + BUS_READ_ENABLE_OUT(5) => slv_read(5), + BUS_WRITE_ENABLE_OUT(5) => slv_write(5), + BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32), + BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), + BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16), + BUS_TIMEOUT_OUT(5) => open, + BUS_DATAREADY_IN(5) => slv_ack(5), + BUS_WRITE_ACK_IN(5) => slv_ack(5), + BUS_NO_MORE_DATA_IN(5) => slv_busy(5), + BUS_UNKNOWN_ADDR_IN(5) => '0', + -- ADC 0 SPI control registers + BUS_READ_ENABLE_OUT(6) => slv_read(6), + BUS_WRITE_ENABLE_OUT(6) => slv_write(6), + BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32), + BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32), + BUS_ADDR_OUT(6*16+15 downto 6*16) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATAREADY_IN(6) => slv_ack(6), + BUS_WRITE_ACK_IN(6) => slv_ack(6), + BUS_NO_MORE_DATA_IN(6) => slv_busy(6), + BUS_UNKNOWN_ADDR_IN(6) => '0', + -- ADC 1 SPI control registers + BUS_READ_ENABLE_OUT(7) => slv_read(7), + BUS_WRITE_ENABLE_OUT(7) => slv_write(7), + BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32), + BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32), + BUS_ADDR_OUT(7*16+15 downto 7*16) => open, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATAREADY_IN(7) => slv_ack(7), + BUS_WRITE_ACK_IN(7) => slv_ack(7), + BUS_NO_MORE_DATA_IN(7) => slv_busy(7), + BUS_UNKNOWN_ADDR_IN(7) => '0', + -- APV control / status registers + BUS_READ_ENABLE_OUT(8) => slv_read(8), + BUS_WRITE_ENABLE_OUT(8) => slv_write(8), + BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32), + BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32), + BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16), + BUS_TIMEOUT_OUT(8) => open, + BUS_DATAREADY_IN(8) => slv_ack(8), + BUS_WRITE_ACK_IN(8) => slv_ack(8), + BUS_NO_MORE_DATA_IN(8) => slv_busy(8), + BUS_UNKNOWN_ADDR_IN(8) => '0', + -- ADC / PLL / trigger ctrl register + BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9), + BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9), + BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32), + BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32), + BUS_ADDR_OUT(11*16+15 downto 9*16) => open, + BUS_TIMEOUT_OUT(11 downto 9) => open, + BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9), + BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9), + BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9), + BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'), + -- ADC0 snooper + BUS_READ_ENABLE_OUT(12) => slv_read(12), + BUS_WRITE_ENABLE_OUT(12) => slv_write(12), + BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32), + BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32), + BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16), + BUS_TIMEOUT_OUT(12) => open, + BUS_DATAREADY_IN(12) => slv_ack(12), + BUS_WRITE_ACK_IN(12) => slv_ack(12), + BUS_NO_MORE_DATA_IN(12) => slv_busy(12), + BUS_UNKNOWN_ADDR_IN(12) => '0', + -- ADC1 snooper + BUS_READ_ENABLE_OUT(13) => slv_read(13), + BUS_WRITE_ENABLE_OUT(13) => slv_write(13), + BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32), + BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32), + BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16), + BUS_TIMEOUT_OUT(13) => open, + BUS_DATAREADY_IN(13) => slv_ack(13), + BUS_WRITE_ACK_IN(13) => slv_ack(13), + BUS_NO_MORE_DATA_IN(13) => slv_busy(13), + BUS_UNKNOWN_ADDR_IN(13) => '0', + -- Test register + BUS_READ_ENABLE_OUT(14) => slv_read(14), + BUS_WRITE_ENABLE_OUT(14) => slv_write(14), + BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32), + BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32), + BUS_ADDR_OUT(14*16+15 downto 14*16) => open, + BUS_TIMEOUT_OUT(14) => open, + BUS_DATAREADY_IN(14) => slv_ack(14), + BUS_WRITE_ACK_IN(14) => slv_ack(14), + BUS_NO_MORE_DATA_IN(14) => slv_busy(14), + BUS_UNKNOWN_ADDR_IN(14) => '0', + -- data buffer status registers + BUS_READ_ENABLE_OUT(15) => slv_read(15), + BUS_WRITE_ENABLE_OUT(15) => slv_write(15), + BUS_DATA_OUT(15*32+31 downto 15*32) => slv_data_wr(15*32+31 downto 15*32), + BUS_DATA_IN(15*32+31 downto 15*32) => slv_data_rd(15*32+31 downto 15*32), + BUS_ADDR_OUT(15*16+15 downto 15*16) => slv_addr(15*16+15 downto 15*16), + BUS_TIMEOUT_OUT(15) => open, + BUS_DATAREADY_IN(15) => slv_ack(15), + BUS_WRITE_ACK_IN(15) => slv_ack(15), + BUS_NO_MORE_DATA_IN(15) => slv_busy(15), + BUS_UNKNOWN_ADDR_IN(15) => '0', + -- LVL1 release status register + BUS_READ_ENABLE_OUT(16) => slv_read(16), + BUS_WRITE_ENABLE_OUT(16) => slv_write(16), + BUS_DATA_OUT(16*32+31 downto 16*32) => slv_data_wr(16*32+31 downto 16*32), + BUS_DATA_IN(16*32+31 downto 16*32) => slv_data_rd(16*32+31 downto 16*32), + BUS_ADDR_OUT(16*16+15 downto 16*16) => slv_addr(16*16+15 downto 16*16), + BUS_TIMEOUT_OUT(16) => open, + BUS_DATAREADY_IN(16) => slv_ack(16), + BUS_WRITE_ACK_IN(16) => slv_ack(16), + BUS_NO_MORE_DATA_IN(16) => slv_busy(16), + BUS_UNKNOWN_ADDR_IN(16) => '0', + -- IPU handler status register + BUS_READ_ENABLE_OUT(17) => slv_read(17), + BUS_WRITE_ENABLE_OUT(17) => slv_write(17), + BUS_DATA_OUT(17*32+31 downto 17*32) => slv_data_wr(17*32+31 downto 17*32), + BUS_DATA_IN(17*32+31 downto 17*32) => slv_data_rd(17*32+31 downto 17*32), + BUS_ADDR_OUT(17*16+15 downto 17*16) => slv_addr(17*16+15 downto 17*16), + BUS_TIMEOUT_OUT(17) => open, + BUS_DATAREADY_IN(17) => slv_ack(17), + BUS_WRITE_ACK_IN(17) => slv_ack(17), + BUS_NO_MORE_DATA_IN(17) => slv_busy(17), + BUS_UNKNOWN_ADDR_IN(17) => '0', -- debug - STAT_DEBUG => stat - ); + STAT_DEBUG => stat +); ------------------------------------------------------------------------------------ @@ -313,7 +472,7 @@ port map( MEM_15_D_OUT => PED_DATA_15_OUT, -- Status lines STAT => open - ); +); slv_busy(0) <= '0'; ------------------------------------------------------------------------------------ @@ -795,6 +954,8 @@ port map( ); + + -- unusable pins debug(63 downto 43) <= (others => '0'); -- connected pins diff --git a/source/slv_adc_la.vhd b/design/slv_adc_la.vhd similarity index 100% rename from source/slv_adc_la.vhd rename to design/slv_adc_la.vhd diff --git a/source/slv_adc_snoop.vhd b/design/slv_adc_snoop.vhd similarity index 100% rename from source/slv_adc_snoop.vhd rename to design/slv_adc_snoop.vhd diff --git a/source/slv_half_register.vhd b/design/slv_half_register.vhd similarity index 100% rename from source/slv_half_register.vhd rename to design/slv_half_register.vhd diff --git a/source/slv_memory_true.vhd b/design/slv_memory_true.vhd similarity index 100% rename from source/slv_memory_true.vhd rename to design/slv_memory_true.vhd diff --git a/cores/slv_onewire_dpram.lpc b/design/slv_onewire_dpram.lpc similarity index 100% rename from cores/slv_onewire_dpram.lpc rename to design/slv_onewire_dpram.lpc diff --git a/cores/slv_onewire_dpram.srp b/design/slv_onewire_dpram.srp similarity index 100% rename from cores/slv_onewire_dpram.srp rename to design/slv_onewire_dpram.srp diff --git a/cores/slv_onewire_dpram.vhd b/design/slv_onewire_dpram.vhd similarity index 100% rename from cores/slv_onewire_dpram.vhd rename to design/slv_onewire_dpram.vhd diff --git a/cores/slv_onewire_dpram_generate.log b/design/slv_onewire_dpram_generate.log similarity index 100% rename from cores/slv_onewire_dpram_generate.log rename to design/slv_onewire_dpram_generate.log diff --git a/cores/slv_onewire_dpram_tmpl.vhd b/design/slv_onewire_dpram_tmpl.vhd similarity index 100% rename from cores/slv_onewire_dpram_tmpl.vhd rename to design/slv_onewire_dpram_tmpl.vhd diff --git a/source/slv_onewire_memory.vhd b/design/slv_onewire_memory.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/slv_onewire_memory.vhd rename to design/slv_onewire_memory.vhd diff --git a/source/slv_ped_thr_mem.vhd b/design/slv_ped_thr_mem.vhd similarity index 100% rename from source/slv_ped_thr_mem.vhd rename to design/slv_ped_thr_mem.vhd diff --git a/source/slv_register.vhd b/design/slv_register.vhd similarity index 100% rename from source/slv_register.vhd rename to design/slv_register.vhd diff --git a/source/slv_register_bank.vhd b/design/slv_register_bank.vhd similarity index 100% rename from source/slv_register_bank.vhd rename to design/slv_register_bank.vhd diff --git a/source/slv_status.vhd b/design/slv_status.vhd similarity index 100% rename from source/slv_status.vhd rename to design/slv_status.vhd diff --git a/source/slv_status_bank.vhd b/design/slv_status_bank.vhd similarity index 100% rename from source/slv_status_bank.vhd rename to design/slv_status_bank.vhd diff --git a/source/spare_onewire_mapping.mem b/design/spare_onewire_mapping.mem similarity index 100% rename from source/spare_onewire_mapping.mem rename to design/spare_onewire_mapping.mem diff --git a/source/spi_adc_master.vhd b/design/spi_adc_master.vhd similarity index 100% rename from source/spi_adc_master.vhd rename to design/spi_adc_master.vhd diff --git a/source/spi_real_slim.vhd b/design/spi_real_slim.vhd similarity index 100% rename from source/spi_real_slim.vhd rename to design/spi_real_slim.vhd diff --git a/source/state_sync.vhd b/design/state_sync.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/state_sync.vhd rename to design/state_sync.vhd diff --git a/cores/sync_pll_40m.lpc b/design/sync_pll_40m.lpc similarity index 100% rename from cores/sync_pll_40m.lpc rename to design/sync_pll_40m.lpc diff --git a/cores/sync_pll_40m.srp b/design/sync_pll_40m.srp similarity index 100% rename from cores/sync_pll_40m.srp rename to design/sync_pll_40m.srp diff --git a/cores/sync_pll_40m.vhd b/design/sync_pll_40m.vhd similarity index 100% rename from cores/sync_pll_40m.vhd rename to design/sync_pll_40m.vhd diff --git a/cores/sync_pll_40m_generate.log b/design/sync_pll_40m_generate.log similarity index 100% rename from cores/sync_pll_40m_generate.log rename to design/sync_pll_40m_generate.log diff --git a/cores/sync_pll_40m_tmpl.vhd b/design/sync_pll_40m_tmpl.vhd similarity index 100% rename from cores/sync_pll_40m_tmpl.vhd rename to design/sync_pll_40m_tmpl.vhd diff --git a/source/tb_count_unit.vhd b/design/tb_count_unit.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/tb_count_unit.vhd rename to design/tb_count_unit.vhd diff --git a/source/tb_count_unit.vhd.bak b/design/tb_count_unit.vhd.bak old mode 100644 new mode 100755 similarity index 100% rename from source/tb_count_unit.vhd.bak rename to design/tb_count_unit.vhd.bak diff --git a/cores/tb_test_fifo2_tmpl.vhd b/design/tb_test_fifo2_tmpl.vhd similarity index 100% rename from cores/tb_test_fifo2_tmpl.vhd rename to design/tb_test_fifo2_tmpl.vhd diff --git a/cores/test_fifo.lpc b/design/test_fifo.lpc similarity index 100% rename from cores/test_fifo.lpc rename to design/test_fifo.lpc diff --git a/cores/test_fifo.vhd b/design/test_fifo.vhd similarity index 100% rename from cores/test_fifo.vhd rename to design/test_fifo.vhd diff --git a/cores/test_fifo2.jhd b/design/test_fifo2.jhd similarity index 100% rename from cores/test_fifo2.jhd rename to design/test_fifo2.jhd diff --git a/cores/test_fifo2.lpc b/design/test_fifo2.lpc similarity index 100% rename from cores/test_fifo2.lpc rename to design/test_fifo2.lpc diff --git a/cores/test_fifo2.naf b/design/test_fifo2.naf similarity index 100% rename from cores/test_fifo2.naf rename to design/test_fifo2.naf diff --git a/cores/test_fifo2.srp b/design/test_fifo2.srp similarity index 100% rename from cores/test_fifo2.srp rename to design/test_fifo2.srp diff --git a/cores/test_fifo2.sym b/design/test_fifo2.sym similarity index 100% rename from cores/test_fifo2.sym rename to design/test_fifo2.sym diff --git a/cores/test_fifo2.vhd b/design/test_fifo2.vhd similarity index 100% rename from cores/test_fifo2.vhd rename to design/test_fifo2.vhd diff --git a/cores/test_fifo2_generate.log b/design/test_fifo2_generate.log similarity index 100% rename from cores/test_fifo2_generate.log rename to design/test_fifo2_generate.log diff --git a/cores/test_fifo2_tmpl.vhd b/design/test_fifo2_tmpl.vhd similarity index 100% rename from cores/test_fifo2_tmpl.vhd rename to design/test_fifo2_tmpl.vhd diff --git a/cores/test_fifo_tmpl.vhd b/design/test_fifo_tmpl.vhd similarity index 100% rename from cores/test_fifo_tmpl.vhd rename to design/test_fifo_tmpl.vhd diff --git a/source/test_media.vhd b/design/test_media.vhd old mode 100644 new mode 100755 similarity index 100% rename from source/test_media.vhd rename to design/test_media.vhd diff --git a/cores/testfifo.lpc b/design/testfifo.lpc similarity index 100% rename from cores/testfifo.lpc rename to design/testfifo.lpc diff --git a/cores/testfifo.vhd b/design/testfifo.vhd similarity index 100% rename from cores/testfifo.vhd rename to design/testfifo.vhd diff --git a/cores/testfifo_tmpl.vhd b/design/testfifo_tmpl.vhd similarity index 100% rename from cores/testfifo_tmpl.vhd rename to design/testfifo_tmpl.vhd diff --git a/featurelist.txt b/featurelist.txt old mode 100644 new mode 100755 diff --git a/howto_adcm_i2c.txt b/howto_adcm_i2c.txt old mode 100644 new mode 100755 diff --git a/lever/.recordref b/lever/.recordref old mode 100644 new mode 100755 diff --git a/lever/adc_apv_map_mem.jhd b/lever/adc_apv_map_mem.jhd old mode 100644 new mode 100755 diff --git a/lever/adc_ch_in.jhd b/lever/adc_ch_in.jhd old mode 100644 new mode 100755 diff --git a/lever/adc_onewire_map_mem.jhd b/lever/adc_onewire_map_mem.jhd old mode 100644 new mode 100755 diff --git a/lever/adc_snoop_mem.jhd b/lever/adc_snoop_mem.jhd old mode 100644 new mode 100755 diff --git a/lever/adcmv3.ini b/lever/adcmv3.ini old mode 100644 new mode 100755 diff --git a/lever/adcmv3.jid b/lever/adcmv3.jid old mode 100644 new mode 100755 diff --git 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a/lever/sbuf.szr b/lever/sbuf.szr old mode 100644 new mode 100755 diff --git a/lever/serdes_gbe_2.jhd b/lever/serdes_gbe_2.jhd old mode 100644 new mode 100755 diff --git a/lever/slv_onewire_dpram.jhd b/lever/slv_onewire_dpram.jhd old mode 100644 new mode 100755 diff --git a/lever/spi_dpram_32_to_8.jhd b/lever/spi_dpram_32_to_8.jhd old mode 100644 new mode 100755 diff --git a/lever/suber_12bit.jhd b/lever/suber_12bit.jhd old mode 100644 new mode 100755 diff --git a/lever/sync_pll_40m.jhd b/lever/sync_pll_40m.jhd old mode 100644 new mode 100755 diff --git a/lever/syntmp/hdlinfo.log b/lever/syntmp/hdlinfo.log old mode 100644 new mode 100755 diff --git a/lever/syntmp/hdlorder.tcl b/lever/syntmp/hdlorder.tcl old mode 100644 new mode 100755 diff --git a/lever/syntmp/sbuf.plg b/lever/syntmp/sbuf.plg old mode 100644 new mode 100755 diff --git a/lever/tb_apv_trgctrl.rsp b/lever/tb_apv_trgctrl.rsp old mode 100644 new mode 100755 diff --git a/lever/tb_apv_trgctrl_activehdl.do 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b/lever/tb_media_fifo_mb_vhdf.udo old mode 100644 new mode 100755 diff --git a/lever/tb_media_fifo_vhdf.udo b/lever/tb_media_fifo_vhdf.udo old mode 100644 new mode 100755 diff --git a/lever/tb_ped_corr_ctrl.rsp b/lever/tb_ped_corr_ctrl.rsp old mode 100644 new mode 100755 diff --git a/lever/tb_ped_corr_ctrl_activehdl.do b/lever/tb_ped_corr_ctrl_activehdl.do old mode 100644 new mode 100755 diff --git a/lever/tb_ped_corr_ctrl_activehdl2.do b/lever/tb_ped_corr_ctrl_activehdl2.do old mode 100644 new mode 100755 diff --git a/lever/tb_ped_corr_ctrl_vhdf.udo b/lever/tb_ped_corr_ctrl_vhdf.udo old mode 100644 new mode 100755 diff --git a/lever/tb_sfp_rx_handler.rsp b/lever/tb_sfp_rx_handler.rsp old mode 100644 new mode 100755 diff --git a/lever/tb_sfp_rx_handler_activehdl.do b/lever/tb_sfp_rx_handler_activehdl.do old mode 100644 new mode 100755 diff --git a/lever/tb_sfp_rx_handler_activehdl2.do b/lever/tb_sfp_rx_handler_activehdl2.do old mode 100644 new mode 100755 diff --git a/lever/tb_sfp_rx_handler_vhdf.udo b/lever/tb_sfp_rx_handler_vhdf.udo old mode 100644 new mode 100755 diff --git a/lever/tb_spi_master.fado b/lever/tb_spi_master.fado old mode 100644 new mode 100755 diff --git a/lever/tb_spi_master.rsp b/lever/tb_spi_master.rsp old mode 100644 new mode 100755 diff --git a/lever/tb_spi_master_activehdl.do b/lever/tb_spi_master_activehdl.do old mode 100644 new mode 100755 diff --git a/lever/tb_spi_master_activehdl2.do b/lever/tb_spi_master_activehdl2.do old mode 100644 new mode 100755 diff --git a/lever/tb_spi_master_vhdf.udo b/lever/tb_spi_master_vhdf.udo old mode 100644 new mode 100755 diff --git a/lever/tb_test_media.rsp b/lever/tb_test_media.rsp old mode 100644 new mode 100755 diff --git a/lever/tb_test_media_activehdl.do b/lever/tb_test_media_activehdl.do old mode 100644 new mode 100755 diff --git a/lever/tb_test_media_activehdl2.do b/lever/tb_test_media_activehdl2.do old mode 100644 new mode 100755 diff --git a/lever/tb_test_media_vhdf.udo b/lever/tb_test_media_vhdf.udo old mode 100644 new mode 100755 diff --git a/lever/test_media.vht b/lever/test_media.vht old mode 100644 new mode 100755 diff --git a/lever/udo.rsp b/lever/udo.rsp old mode 100644 new mode 100755 diff --git a/lever/work.sbuf.prj b/lever/work.sbuf.prj old mode 100644 new mode 100755 diff --git a/lever/work/0work.mgf b/lever/work/0work.mgf old mode 100644 new mode 100755 diff --git a/lever/work/1work.mgf b/lever/work/1work.mgf old mode 100644 new mode 100755 diff --git a/lever/work/3work.mgf b/lever/work/3work.mgf old mode 100644 new mode 100755 diff --git a/lever/work/Edfmap.ini b/lever/work/Edfmap.ini old mode 100644 new mode 100755 diff --git a/lever/work/compilation.order b/lever/work/compilation.order old mode 100644 new mode 100755 diff --git a/lever/work/compile.cfg b/lever/work/compile.cfg old mode 100644 new mode 100755 diff --git a/lever/work/compile/sources.sth b/lever/work/compile/sources.sth old mode 100644 new mode 100755 diff --git a/lever/work/compile/work.cmd b/lever/work/compile/work.cmd old mode 100644 new mode 100755 diff --git a/lever/work/compile/work.epr b/lever/work/compile/work.epr old mode 100644 new mode 100755 diff --git a/lever/work/compile/work.erf b/lever/work/compile/work.erf old mode 100644 new mode 100755 diff --git a/lever/work/elaboration.log b/lever/work/elaboration.log old mode 100644 new mode 100755 diff --git a/lever/work/library.cfg b/lever/work/library.cfg old mode 100644 new mode 100755 diff --git a/lever/work/log/console.log b/lever/work/log/console.log old mode 100644 new mode 100755 diff --git a/lever/work/projlib.cfg b/lever/work/projlib.cfg old mode 100644 new mode 100755 diff --git a/lever/work/work.LIB b/lever/work/work.LIB old mode 100644 new mode 100755 diff --git a/lever/work/work.adf b/lever/work/work.adf old mode 100644 new mode 100755 diff --git a/lever/work/work.aws b/lever/work/work.aws old mode 100644 new mode 100755 diff --git a/lever/work/work.wsp b/lever/work/work.wsp old mode 100644 new mode 100755 diff --git a/lever/work/work.wsw b/lever/work/work.wsw old mode 100644 new mode 100755 diff --git a/nodelist.txt b/nodelist.txt index 0c760d8..8ddb65b 100755 --- a/nodelist.txt +++ b/nodelist.txt @@ -1,50 +1,47 @@ -[pbs1] +[pbs2] system = linux corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs2] +env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ + +[pbs1] system = linux corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ + [pbs3] system = linux corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ + [pbs4] system = linux corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ + [pbs5] system = linux corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ + [pbs6] system = linux corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ + [pbs7] system = linux corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ + [pbs8] system = linux corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs9] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[pbs10] -system = linux -corenum = 2 -env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +env = /usr/local/opt/lattice_diamond/diamond/3.4/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/ADCM/adcm/workdir/ diff --git a/ports_hadeb05.txt b/ports_hadeb05.txt deleted file mode 100644 index 266e89c..0000000 --- a/ports_hadeb05.txt +++ /dev/null @@ -1,2 +0,0 @@ -/home/hadaq/license/lattice_license.log: 1:19:02 (lmgrd) lmgrd tcp-port 1702 -/home/hadaq/license/lattice_license.log: 1:19:02 (lmgrd) Started lattice (internet tcp_port 51765 pid 30916) diff --git a/ports_lxcad01.txt b/ports_lxcad01.txt deleted file mode 100644 index ebb2e69..0000000 --- a/ports_lxcad01.txt +++ /dev/null @@ -1,14 +0,0 @@ -/cad/licenses/log/ams_lm.log:15:55:49 (lmgrd) lmgrd tcp-port 26745 -/cad/licenses/log/ams_lm.log:15:55:49 (lmgrd) Started amslmd (internet tcp_port 64814 pid 21110) -/cad/licenses/log/atr_license.log:9:52:13 (lmgrd) lmgrd tcp-port 27005 -/cad/licenses/log/atr_license.log:9:52:13 (lmgrd) Started atrenta (internet tcp_port 46943 pid 18866) -/cad/licenses/log/cds_license.log:13:46:39 (lmgrd) lmgrd tcp-port 5280 -/cad/licenses/log/cds_license.log:13:46:39 (lmgrd) Started cdslmd (internet tcp_port 50309 pid 32758) -/cad/licenses/log/mentor_license.log:14:42:53 (lmgrd) lmgrd tcp-port 1710 -/cad/licenses/log/mentor_license.log:14:42:53 (lmgrd) Started mgcld (internet tcp_port 42914 pid 8237) -/cad/licenses/log/mg_license.log:13:26:04 (lmgrd) lmgrd tcp-port 1717 -/cad/licenses/log/mg_license.log:13:26:04 (lmgrd) Started mgcld (internet tcp_port 39276 pid 11086) -/cad/licenses/log/mgcld_lm.log:16:44:20 (lmgrd) lmgrd tcp-port 1710 -/cad/licenses/log/mgcld_lm.log:16:44:20 (lmgrd) Started mgcld (internet tcp_port 64863 pid 24087) -/cad/licenses/log/syn_license.log:10:29:33 (lmgrd) lmgrd tcp-port 27000 -/cad/licenses/log/syn_license.log:10:29:33 (lmgrd) Started snpslmd (internet tcp_port 54219 pid 24990) diff --git a/sim/tb_adc_apv_map_mem_tmpl.vhd b/sim/tb_adc_apv_map_mem_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_adc_cross.vhd b/sim/tb_adc_cross.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_adc_crossover.vhd b/sim/tb_adc_crossover.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_adc_handler.vhd b/sim/tb_adc_handler.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_adc_handler.vhd.bak b/sim/tb_adc_handler.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_adc_onewire_map_mem_tmpl.vhd b/sim/tb_adc_onewire_map_mem_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_apv_adc_map_mem_tmpl.vhd b/sim/tb_apv_adc_map_mem_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_apv_locker.vhd b/sim/tb_apv_locker.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_apv_map_mem_tmpl.vhd b/sim/tb_apv_map_mem_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_apv_pc_nc_alu.vhd b/sim/tb_apv_pc_nc_alu.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_apv_trgctrl.vhd b/sim/tb_apv_trgctrl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_apv_trgctrl.vhd.bak b/sim/tb_apv_trgctrl.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_apv_trgctrl_000.vhd b/sim/tb_apv_trgctrl_000.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_comp4bit_tmpl.vhd b/sim/tb_comp4bit_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_crossfifo.vhd b/sim/tb_crossfifo.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_crossfifo_tmpl.vhd b/sim/tb_crossfifo_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_crossover.vhd b/sim/tb_crossover.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_crossover_tmpl.vhd b/sim/tb_crossover_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_dpram_8x19_tmpl.vhd b/sim/tb_dpram_8x19_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_fifo_16x11_tmpl.vhd b/sim/tb_fifo_16x11_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_fifo_1kx18_tmpl.vhd b/sim/tb_fifo_1kx18_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_ipu_fifo_stage.vhd b/sim/tb_ipu_fifo_stage.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_ipu_fifo_stage.vhd.bak b/sim/tb_ipu_fifo_stage.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_ipu_fifo_stage_COPY.vhd b/sim/tb_ipu_fifo_stage_COPY.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_ipu_fifo_stage_OLD.vhd b/sim/tb_ipu_fifo_stage_OLD.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_logic_analyzer.vhd b/sim/tb_logic_analyzer.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_max_data.vhd b/sim/tb_max_data.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_media_fifo.vhd b/sim/tb_media_fifo.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_media_fifo.vhd.bak b/sim/tb_media_fifo.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_media_fifo_mb.vhd b/sim/tb_media_fifo_mb.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_media_fifo_mb.vhd.bak b/sim/tb_media_fifo_mb.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_mult_3x8.vhd b/sim/tb_mult_3x8.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_mult_3x8_tmpl.vhd b/sim/tb_mult_3x8_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_my_sbuf.vhd b/sim/tb_my_sbuf.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_onewire_master.vhd b/sim/tb_onewire_master.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_onewire_spare_one_tmpl.vhd b/sim/tb_onewire_spare_one_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_ped_corr_ctrl.vhd b/sim/tb_ped_corr_ctrl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_ped_corr_ctrl.vhd.bak b/sim/tb_ped_corr_ctrl.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_ped_corr_ctrl_OLD.vhd b/sim/tb_ped_corr_ctrl_OLD.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_pulse_stretch.vhd b/sim/tb_pulse_stretch.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_pulse_sync.vhd b/sim/tb_pulse_sync.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_raw_buf_stage.vhd b/sim/tb_raw_buf_stage.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_raw_buf_stage_new.vhd b/sim/tb_raw_buf_stage_new.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_real_trg_handler.vhd b/sim/tb_real_trg_handler.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_reboot_handler.vhd b/sim/tb_reboot_handler.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_reset_handler.vhd b/sim/tb_reset_handler.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_sfp_rx_handler.vhd b/sim/tb_sfp_rx_handler.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_sfp_rx_handler.vhd.bak b/sim/tb_sfp_rx_handler.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_slv_adc_la.vhd b/sim/tb_slv_adc_la.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_slv_adc_snoop.vhd b/sim/tb_slv_adc_snoop.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_slv_onewire_memory.vhd b/sim/tb_slv_onewire_memory.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_slv_ped_thr_mem.vhd b/sim/tb_slv_ped_thr_mem.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_slv_register_bank.vhd b/sim/tb_slv_register_bank.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_spi_master.vhd b/sim/tb_spi_master.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_spi_master.vhd.bak b/sim/tb_spi_master.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_spi_master_0.vhd b/sim/tb_spi_master_0.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_spi_real_slim.vhd b/sim/tb_spi_real_slim.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_suber_12bit_tmpl.vhd b/sim/tb_suber_12bit_tmpl.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_test_media.vhd b/sim/tb_test_media.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_test_media.vhd.bak b/sim/tb_test_media.vhd.bak old mode 100644 new mode 100755 diff --git a/sim/tb_trb_net16_ibuf2.vhd b/sim/tb_trb_net16_ibuf2.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_trb_net_sbuf2.vhd b/sim/tb_trb_net_sbuf2.vhd old mode 100644 new mode 100755 diff --git a/sim/tb_trb_net_sbuf3.vhd b/sim/tb_trb_net_sbuf3.vhd old mode 100644 new mode 100755 diff --git a/source/adcmv3_components2.vhd b/source/adcmv3_components2.vhd deleted file mode 100644 index 6496d1e..0000000 --- a/source/adcmv3_components2.vhd +++ /dev/null @@ -1,29 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package adcmv3_componets is - - type debug_array_t is array(integer range <>) of - std_logic_vector(15 downto 0); - - component debug_multiplexer - generic ( - NUM_PORTS : integer range 1 to 32); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1); - DEBUG_LINE_OUT : out std_logic_vector(15 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - ); - end component; - -end package; diff --git a/source/debug_multiplexer.vhd b/source/debug_multiplexer.vhd deleted file mode 100644 index 7b70f58..0000000 --- a/source/debug_multiplexer.vhd +++ /dev/null @@ -1,118 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.adcmv3_componets.all; - -entity debug_multiplexer is - generic ( - NUM_PORTS : integer range 1 to 32 := 1 - ); - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1); - DEBUG_LINE_OUT : out std_logic_vector(15 downto 0); - - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - - ); -end entity; - -architecture Behavioral of debug_multiplexer is - - signal port_select : std_logic_vector(7 downto 0); - signal debug_line_o : std_logic_vector(15 downto 0); - - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - -begin - - PROC_MULTIPLEXER: process(port_select, - DEBUG_LINE_IN) - begin - if (unsigned(port_select) < NUM_PORTS) then - debug_line_o <= - DEBUG_LINE_IN(to_integer(unsigned(port_select))); - elsif (unsigned(port_select) = NUM_PORTS) then - -- Checkerboard - for I in 0 to 7 loop - debug_line_o(I * 2) <= CLK_IN; - debug_line_o(I * 2 + 1) <= not CLK_IN; - end loop; - else - debug_line_o <= (others => '1'); - end if; - end process PROC_MULTIPLEXER; - - PROC_SLAVE_BUS: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - port_select <= (others => '0'); - else - slv_ack_o <= '1'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - slv_data_out_o <= (others => '0'); - - if (SLV_WRITE_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - if (unsigned(SLV_DATA_IN(7 downto 0)) < NUM_PORTS + 1) then - port_select <= SLV_DATA_IN(7 downto 0); - end if; - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - elsif (SLV_READ_IN = '1') then - case SLV_ADDR_IN is - when x"0000" => - slv_data_out_o(7 downto 0) <= port_select; - slv_data_out_o(31 downto 8) <= (others => '0'); - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; - - else - slv_ack_o <= '0'; - end if; - end if; - end if; - end process PROC_SLAVE_BUS; - - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- - - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - - DEBUG_LINE_OUT <= debug_line_o; - -end Behavioral; diff --git a/stdout.log b/stdout.log index c999375..c217a76 100644 --- a/stdout.log +++ b/stdout.log @@ -4,7 +4,7 @@ Running in Lattice mode Starting: /usr/local/opt/lattice_diamond/diamond/3.4/synpbase/linux_a_64/mbin/synbatch Install: /usr/local/opt/lattice_diamond/diamond/3.4/synpbase Hostname: brett -Date: Wed Aug 26 17:56:58 2015 +Date: Fri Aug 28 15:32:35 2015 Version: J-2014.09L Arguments: -product synplify_pro -batch adcmv3.prj @@ -16,7 +16,7 @@ CDPL_LOGDIR: /home/lmaier/.synopsys/fpga/cdpllog -log file: "/home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srr" +log file: "/home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srr" @@ -31,24 +31,24 @@ Running: Compile Process on adcmv3|workdir Running: Compile Input on adcmv3|workdir -Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srs +Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srs compiler Completed Return Code: 0 -Run Time:00h:00m:20s +Run Time:00h:00m:19s Running: Multi-srs Generator on adcmv3|workdir -Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_s.srs +Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_s.srs multi_srs_gen Completed Return Code: 0 Run Time:00h:00m:02s -Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_mult.srs to /home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srs +Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_mult.srs to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srs Complete: Compile Process on adcmv3|workdir @@ -58,7 +58,7 @@ Running: Pre-mapping on adcmv3|workdir premap Completed with warnings Return Code: 1 -Run Time:00h:00m:07s +Run Time:00h:00m:05s Complete: Compile on adcmv3|workdir @@ -68,12 +68,12 @@ Running: Map on adcmv3|workdir Running: Map & Optimize on adcmv3|workdir -Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_m.srm to /home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srm +Copied /home/rich/TRB/nXyter/ADCM/adcm/workdir/synwork/adcmv3_m.srm to /home/rich/TRB/nXyter/ADCM/adcm/workdir/adcmv3.srm fpga_mapper Completed with warnings Return Code: 1 -Run Time:00h:04m:29s +Run Time:00h:03m:47s Complete: Map on adcmv3|workdir diff --git a/test.txt b/test.txt old mode 100644 new mode 100755 diff --git a/tunnel.sh b/tunnel.sh old mode 100755 new mode 100644 diff --git a/workdir/.recordref b/workdir/.recordref deleted file mode 100644 index e69de29..0000000 diff --git a/workdir/.recordref_modgen b/workdir/.recordref_modgen deleted file mode 100644 index e69de29..0000000