From: hadeshyp Date: Tue, 29 Mar 2011 11:38:09 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=80f1127b7684588b762ce6fcfaf9f6d3d95b14b2;p=mdcoep.git *** empty log message *** --- diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl index 0241344..75be7a7 100755 --- a/compile_frankfurt.pl +++ b/compile_frankfurt.pl @@ -12,10 +12,10 @@ use Data::Dumper; use warnings; use strict; -my $lattice_path = '/d/sugar/lattice/ispLEVER8.1/isptools/'; +#my $lattice_path = '/d/sugar/lattice/ispLEVER8.1/isptools/'; +my $lattice_path = '/d/sugar/lattice/diamond/1.1'; #my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; my $synplify_path = '/d/sugar/lattice/synplify/D-2010.03/'; -#my $synplify_path = '/home/hadaq/bin/'; use FileHandle; diff --git a/constraints.lpf b/constraints.lpf index 9592385..b7f6217 100644 --- a/constraints.lpf +++ b/constraints.lpf @@ -18,4 +18,6 @@ GSR_NET NET "gsr_n"; GSR_NET NET "pll_locked"; -# MULTICYCLE FROM CELL reset 2.0 x; \ No newline at end of file +# MULTICYCLE FROM CELL reset 2.0 x; + + SYSCONFIG MCCLK_FREQ = 20; \ No newline at end of file diff --git a/design2/data_handler.vhd b/design2/data_handler.vhd index abf7788..7000016 100644 --- a/design2/data_handler.vhd +++ b/design2/data_handler.vhd @@ -9,7 +9,7 @@ use work.trb_net_components.all; entity data_handler is generic( - NUMBER_OF_STAT_WORDS : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(11,5)) + NUMBER_OF_STAT_WORDS : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(21,5)) ); port( CLK : in std_logic; @@ -47,6 +47,7 @@ entity data_handler is INC_TRUNCATED_EVENT_OUT : out std_logic; INC_SINGLE_HIT0_OUT : out std_logic; INC_SINGLE_HIT1_OUT : out std_logic; + INC_HIT_OUT : out std_logic; STAT_ADDR_OUT : out std_logic_vector(4 downto 0); STAT_DATA_IN : in std_logic_vector(23 downto 0); @@ -423,6 +424,7 @@ begin INC_TRUNCATED_WORD_OUT <= inc_truncated_word_ctr; INC_SINGLE_HIT0_OUT <= inc_single_hit0_ctr; INC_SINGLE_HIT1_OUT <= inc_single_hit1_ctr; + INC_HIT_OUT <= data_write_i; STAT_ADDR_OUT <= std_logic_vector(stat_addr_i); ------------------------------------------------------------------------------- diff --git a/design2/mdc_control.vhd b/design2/mdc_control.vhd index 693c919..5601668 100644 --- a/design2/mdc_control.vhd +++ b/design2/mdc_control.vhd @@ -58,7 +58,7 @@ entity mdc_control is STAT_READ_ENABLE_IN : in std_logic; STAT_READY_OUT : out std_logic; - STATISTIC_ADDR_IN : in std_logic_vector(3 downto 0); + STATISTIC_ADDR_IN : in std_logic_vector(4 downto 0); STATISTIC_DATA_OUT : out std_logic_vector(31 downto 0); STATISTIC_READ_IN : in std_logic; STATISTIC_READY_OUT : out std_logic; @@ -72,7 +72,9 @@ entity mdc_control is COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0); STAT_REG_OUT : out std_logic_vector(63 downto 0); CTRL_REG_IN : in std_logic_vector(127 downto 0); + STAT_TRIGGER_IN : in std_logic_vector(63 downto 0); + TIMER_TICKS_IN : in std_logic_vector(1 downto 0); DEBUG_OUT : out std_logic_vector(31 downto 0) ); end entity; @@ -160,6 +162,7 @@ architecture arch of mdc_control is signal counter_single_hit0_i : unsigned(23 downto 0); signal counter_retransmit_received_i : unsigned(11 downto 0); signal counter_retransmit_sent_i : unsigned(11 downto 0); + signal counter_hits_i : unsigned(31 downto 0); signal inc_reinit_counter : std_logic; signal inc_calib_counter : std_logic; @@ -170,9 +173,12 @@ architecture arch of mdc_control is signal inc_trunc_ctr : std_logic; signal inc_single_hit0_ctr : std_logic; signal inc_single_hit1_ctr : std_logic; + signal inc_hit_counter : std_logic; signal data_handler_stat_addr_i: std_logic_vector(4 downto 0); signal data_handler_stat_data_i: std_logic_vector(23 downto 0); + signal trigger_handler_times_i : std_logic_vector(5*32-1 downto 0); + signal force_reinit_i : std_logic; begin @@ -241,11 +247,14 @@ begin TOKEN_MISSING_IN => token_missing_i, TOKEN_BACK_IN => token_back_i, FINISHED_STORING_DATA_IN => fee_data_finished_i, + FORCE_REINIT_IN => force_reinit_i, --Statistics INC_REINIT_OUT => inc_reinit_counter, INC_CALIB_OUT => inc_calib_counter, INC_TRIGGER_OUT => inc_trigger_counter, + STAT_TIMES_OUT => trigger_handler_times_i, --debug + TIMER_TICKS_IN => TIMER_TICKS_IN, DEBUG_REGISTER => debug_trigger_handler_i ); @@ -290,6 +299,7 @@ begin INC_TRUNCATED_EVENT_OUT => inc_trunc_ctr, INC_SINGLE_HIT0_OUT => inc_single_hit0_ctr, INC_SINGLE_HIT1_OUT => inc_single_hit1_ctr, + INC_HIT_OUT => inc_hit_counter, STAT_ADDR_OUT => data_handler_stat_addr_i, STAT_DATA_IN => data_handler_stat_data_i, --Debug @@ -402,7 +412,7 @@ begin end process; proc_statistic_regs : process(CLK) - variable tmp : integer range 0 to 15; + variable tmp : integer range 0 to 31; begin if rising_edge(CLK) then STATISTIC_READY_OUT <= STATISTIC_READ_IN; @@ -421,6 +431,16 @@ begin when 9 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_single_hit0_i); when 10 => STATISTIC_DATA_OUT <= x"00" & std_logic_vector(counter_retransmit_received_i) & std_logic_vector(counter_retransmit_sent_i); + when 11 => STATISTIC_DATA_OUT <= std_logic_vector(counter_hits_i); + when 12 => STATISTIC_DATA_OUT <= x"0000" & STAT_TRIGGER_IN(15 downto 0); + when 13 => STATISTIC_DATA_OUT <= x"0000" & STAT_TRIGGER_IN(31 downto 16); + when 14 => STATISTIC_DATA_OUT <= x"0000" & STAT_TRIGGER_IN(47 downto 32); + when 15 => STATISTIC_DATA_OUT <= x"0000" & STAT_TRIGGER_IN(63 downto 48); + when 16 => STATISTIC_DATA_OUT <= trigger_handler_times_i(31 downto 0); + when 17 => STATISTIC_DATA_OUT <= trigger_handler_times_i(63 downto 32); + when 18 => STATISTIC_DATA_OUT <= trigger_handler_times_i(95 downto 64); + when 19 => STATISTIC_DATA_OUT <= trigger_handler_times_i(127 downto 96); + when 20 => STATISTIC_DATA_OUT <= trigger_handler_times_i(159 downto 128); when others => STATISTIC_DATA_OUT <= (others => '0'); end case; @@ -446,6 +466,16 @@ begin when 9 => data_handler_stat_data_i <= std_logic_vector(counter_single_hit0_i); when 10 => data_handler_stat_data_i <= std_logic_vector(counter_retransmit_received_i) & std_logic_vector(counter_retransmit_sent_i); + when 11 => data_handler_stat_data_i <= std_logic_vector(counter_hits_i(23 downto 0)); + when 12 => data_handler_stat_data_i <= x"00" & STAT_TRIGGER_IN(15 downto 0); + when 13 => data_handler_stat_data_i <= x"00" & STAT_TRIGGER_IN(31 downto 16); + when 14 => data_handler_stat_data_i <= x"00" & STAT_TRIGGER_IN(47 downto 32); + when 15 => data_handler_stat_data_i <= x"00" & STAT_TRIGGER_IN(63 downto 48); + when 16 => data_handler_stat_data_i <= trigger_handler_times_i(23 downto 0); + when 17 => data_handler_stat_data_i <= trigger_handler_times_i(55 downto 32); + when 18 => data_handler_stat_data_i <= trigger_handler_times_i(87 downto 64); + when 19 => data_handler_stat_data_i <= trigger_handler_times_i(119 downto 96); + when 20 => data_handler_stat_data_i <= trigger_handler_times_i(151 downto 128); when others => data_handler_stat_data_i <= (others => '0'); end case; @@ -507,12 +537,9 @@ counter_retransmit_sent_i <= (others => '0'); reset_statistics_i <= RESET or COMMON_CTRL_REG_IN(5); motherboard_type_i <= CTRL_REG_IN(7 downto 4); data_word_limit_i <= CTRL_REG_IN(25 downto 16); - suppress_single_hit0_i <= CTRL_REG_IN(40); - suppress_single_hit1_i <= CTRL_REG_IN(41); enable_reconfigure_i <= CTRL_REG_IN(42); dummy_data_config_i <= CTRL_REG_IN(63 downto 48); - hit0_lower_limit_i <= CTRL_REG_IN(74 downto 64); - hit1_lower_limit_i <= CTRL_REG_IN(90 downto 80); + force_reinit_i <= COMMON_CTRL_REG_IN(9); trigger_pseudo_timing <= COMMON_CTRL_REG_IN(16); trigger_begin_run <= COMMON_CTRL_REG_IN(22); data_format_i <= COMMON_CTRL_REG_IN(84); @@ -523,7 +550,22 @@ counter_retransmit_sent_i <= (others => '0'); end if; end process; - + PROC_REG_DATA_CLEANER : process(CLK) + begin + if rising_edge(CLK) then + if LVL1_TRG_TYPE_IN = x"9" and LVL1_TRG_DATA_VALID_IN = '1' then + suppress_single_hit0_i <= '0'; + suppress_single_hit1_i <= '0'; + hit0_lower_limit_i <= (others => '0'); + hit1_lower_limit_i <= (others => '0'); + elsif LVL1_TRG_DATA_VALID_IN = '0' then + suppress_single_hit0_i <= CTRL_REG_IN(40); + suppress_single_hit1_i <= CTRL_REG_IN(41); + hit0_lower_limit_i <= CTRL_REG_IN(74 downto 64); + hit1_lower_limit_i <= CTRL_REG_IN(90 downto 80); + end if; + end if; + end process; ------------------------------------------------------------------------------- -- Statistics ------------------------------------------------------------------------------- @@ -541,6 +583,7 @@ counter_retransmit_sent_i <= (others => '0'); counter_truncated_words_i <= (others => '0'); counter_single_hit1_i <= (others => '0'); counter_single_hit0_i <= (others => '0'); + counter_hits_i <= (others => '0'); else if inc_discarded_hit0_ctr = '1' then counter_discarded_hit0_i <= counter_discarded_hit0_i + to_unsigned(1,1); @@ -569,6 +612,9 @@ counter_retransmit_sent_i <= (others => '0'); if inc_single_hit1_ctr = '1' then counter_single_hit1_i <= counter_single_hit1_i + to_unsigned(1,1); end if; + if inc_hit_counter = '1' then + counter_hits_i <= counter_hits_i + to_unsigned(1,1); + end if; end if; end if; end process; diff --git a/design2/mdc_oepb_pack.vhd b/design2/mdc_oepb_pack.vhd index 2c85160..ef6fd66 100644 --- a/design2/mdc_oepb_pack.vhd +++ b/design2/mdc_oepb_pack.vhd @@ -95,7 +95,7 @@ package mdc_oepb_pack is INC_TRUNCATED_EVENT_OUT : out std_logic; INC_SINGLE_HIT0_OUT : out std_logic; INC_SINGLE_HIT1_OUT : out std_logic; - + INC_HIT_OUT : out std_logic; STAT_ADDR_OUT : out std_logic_vector(4 downto 0); STAT_DATA_IN : in std_logic_vector(23 downto 0); --Debug @@ -181,7 +181,7 @@ package mdc_oepb_pack is STAT_READ_ENABLE_IN : in std_logic; STAT_READY_OUT : out std_logic; - STATISTIC_ADDR_IN : in std_logic_vector(3 downto 0); + STATISTIC_ADDR_IN : in std_logic_vector(4 downto 0); STATISTIC_DATA_OUT : out std_logic_vector(31 downto 0); STATISTIC_READ_IN : in std_logic; STATISTIC_READY_OUT : out std_logic; @@ -195,7 +195,9 @@ package mdc_oepb_pack is COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0); STAT_REG_OUT : out std_logic_vector(63 downto 0); CTRL_REG_IN : in std_logic_vector(127 downto 0); + STAT_TRIGGER_IN : in std_logic_vector(63 downto 0); + TIMER_TICKS_IN : in std_logic_vector(1 downto 0); DEBUG_OUT : out std_logic_vector(31 downto 0) ); end component; @@ -395,12 +397,15 @@ package mdc_oepb_pack is TOKEN_MISSING_IN : in std_logic; --token timeout - not received back TOKEN_BACK_IN : in std_logic; --token back, readout finished FINISHED_STORING_DATA_IN : in std_logic; --data_handler finished writing data to buffer + FORCE_REINIT_IN : in std_logic; --Statistics INC_REINIT_OUT : out std_logic; INC_CALIB_OUT : out std_logic; INC_TRIGGER_OUT : out std_logic; + STAT_TIMES_OUT : out std_logic_vector(32*5-1 downto 0); --debug + TIMER_TICKS_IN : in std_logic_vector(1 downto 0); DEBUG_REGISTER : out std_logic_vector(31 downto 0) ); end component; diff --git a/design2/trigger_handler.vhd b/design2/trigger_handler.vhd index 81d0ff2..8f15ebc 100644 --- a/design2/trigger_handler.vhd +++ b/design2/trigger_handler.vhd @@ -45,11 +45,14 @@ entity trigger_handler is TOKEN_MISSING_IN : in std_logic; --token timeout - not received back TOKEN_BACK_IN : in std_logic; --token back, readout finished FINISHED_STORING_DATA_IN : in std_logic; --data_handler finished writing data to buffer + FORCE_REINIT_IN : in std_logic; --Statistics INC_REINIT_OUT : out std_logic; INC_CALIB_OUT : out std_logic; INC_TRIGGER_OUT : out std_logic; + STAT_TIMES_OUT : out std_logic_vector(32*5-1 downto 0); + TIMER_TICKS_IN : in std_logic_vector(1 downto 0); --debug DEBUG_REGISTER : out std_logic_vector(31 downto 0) ); @@ -86,6 +89,14 @@ architecture trigger_handle_trg_arch of trigger_handler is signal reset_mbo_i : std_logic; signal mbo_configured_i : std_logic; + signal time_idle : unsigned(31 downto 0); + signal time_begrun : unsigned(31 downto 0); + signal time_calib : unsigned(31 downto 0); + signal time_readout : unsigned(31 downto 0); + signal time_waiting : unsigned(31 downto 0); + + signal force_reinit : std_logic; + begin @@ -182,21 +193,21 @@ begin end if; when DO_READOUT => - if TOKEN_BACK_IN = '1' then - current_state <= WAIT_FOR_FINISHED_STORING; - finished_readout_i <= '1'; - elsif TOKEN_MISSING_IN = '1' then + if TOKEN_MISSING_IN = '1' or (TOKEN_BACK_IN = '1' and force_reinit = '1') then finished_readout_i <= '1'; if ENABLE_REINIT_IN = '1' then mbo_configured_i <= '0'; reinit_running <= '1'; - inc_reinit_counter <= '1'; + inc_reinit_counter <= not force_reinit; reset_mbo_i <= '1'; current_state <= DO_REINIT; else - inc_reinit_counter <= '1'; + inc_reinit_counter <= not force_reinit; current_state <= WAIT_FOR_FINISHED_STORING; end if; + elsif TOKEN_BACK_IN = '1' then + current_state <= WAIT_FOR_FINISHED_STORING; + finished_readout_i <= '1'; end if; when WAIT_FOR_FINISHED_STORING => @@ -246,6 +257,18 @@ begin end if; end process; + proc_force_reinit : process(CLK) + begin + if rising_edge(CLK) then + if FORCE_REINIT_IN = '1' then + force_reinit <= '1'; + elsif current_state = DO_REINIT then + force_reinit <= '0'; + end if; + end if; + end process; + + ------------------------------------------------------------------------------- -- I/O ------------------------------------------------------------------------------- @@ -276,6 +299,38 @@ begin end if; end process; +------------------------------------------------------------------------------- +-- Debugging +------------------------------------------------------------------------------- + proc_state_statistics : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + time_begrun <= (others => '0'); + time_calib <= (others => '0'); + time_idle <= (others => '0'); + time_readout <= (others => '0'); + time_waiting <= (others => '0'); + elsif TIMER_TICKS_IN(0) = '1' then + case current_state is + when IDLE => + time_idle <= time_idle + to_unsigned(1,1); + when BEGRUN | DO_REINIT | DO_REINIT2 => + time_begrun <= time_begrun + to_unsigned(1,1); + when CALIB_TRIGGER => + time_calib <= time_calib + to_unsigned(1,1); + when DO_READOUT | TIMING_TRIGGER => + time_readout <= time_readout + to_unsigned(1,1); + when WAIT_FOR_FINISHED_STORING | RELEASE_LVL1 => + time_waiting <= time_waiting + to_unsigned(1,1); + when others => null; + end case; + end if; + end if; + end process; + + STAT_TIMES_OUT <= std_logic_vector(time_waiting & time_readout & time_calib & time_begrun & time_idle); + ------------------------------------------------------------------------------- -- Debugging ------------------------------------------------------------------------------- diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index e543930..1778b37 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -247,7 +247,7 @@ architecture mdc_oepb_arch of mdc_oepb is signal statisticreg_read : std_logic; signal statisticreg_write : std_logic; signal statisticreg_ready : std_logic; - signal statisticreg_addr : std_logic_vector(3 downto 0); + signal statisticreg_addr : std_logic_vector(4 downto 0); signal statisticreg_data : std_logic_vector(31 downto 0); signal debug_mdc_control_i : std_logic_vector(31 downto 0); @@ -289,6 +289,8 @@ architecture mdc_oepb_arch of mdc_oepb is signal medreg_read : std_logic; signal medreg_ready: std_logic; signal medreg_write: std_logic; + + signal trigger_status_i : std_logic_vector(63 downto 0); begin @@ -407,7 +409,7 @@ begin DATA_INTERFACE_NUMBER => 1, DATA_BUFFER_DEPTH => 13, --13 DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**11-600, --2**13-1024 + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024 TRG_RELEASE_AFTER_DATA => c_YES, HEADER_BUFFER_DEPTH => 9, HEADER_BUFFER_FULL_THRESH => 2**9-16 @@ -482,6 +484,7 @@ begin STAT_DEBUG_2 => open, STAT_DEBUG_DATA_HANDLER_OUT=> debug_data_handler_i, STAT_DEBUG_IPU_HANDLER_OUT => debug_ipu_handler_i, + STAT_TRIGGER_OUT => trigger_status_i, CTRL_MPLEX => (others => '0'), IOBUF_CTRL_GEN => (others => '0'), STAT_ONEWIRE => open, @@ -499,7 +502,7 @@ begin PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200", 5 => x"e000", 6 => x"9000", 7 => x"e100", 8 => x"9100", 9 => x"9200", others => x"0000"), PORT_ADDR_MASK => (0 => 9, 1 => 6, 2 => 1, 3 => 6, 4 => 0, - 5 => 0, 6 => 4, 7 => 0, 8 => 4, 9 => 2, others => 0) + 5 => 0, 6 => 4, 7 => 0, 8 => 5, 9 => 2, others => 0) ) port map( CLK => clk_100, @@ -616,8 +619,8 @@ begin BUS_READ_ENABLE_OUT(8) => statisticreg_read, BUS_WRITE_ENABLE_OUT(8) => statisticreg_write, BUS_DATA_OUT(8*32+31 downto 8*32) => open, - BUS_ADDR_OUT(8*16+3 downto 8*16) => statisticreg_addr, - BUS_ADDR_OUT(8*16+15 downto 8*16+4) => open, + BUS_ADDR_OUT(8*16+4 downto 8*16) => statisticreg_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+5) => open, BUS_TIMEOUT_OUT(8) => open, BUS_DATA_IN(8*32+31 downto 8*32) => statisticreg_data, BUS_DATAREADY_IN(8) => statisticreg_ready, @@ -906,7 +909,10 @@ begin COMMON_CTRL_REG_IN => reg_common_ctrl_reg_out, STAT_REG_OUT => reg_registers_in, CTRL_REG_IN => reg_registers_out, + + STAT_TRIGGER_IN => trigger_status_i, + TIMER_TICKS_IN => timer_ticks, DEBUG_OUT => debug_mdc_control_i );