From: Ludwig Maier Date: Tue, 10 Feb 2015 21:24:30 +0000 (+0100) Subject: added ADCM design project X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8162de1eba4c0f48718882d5f91af94d1cda1ee7;p=adcm.git added ADCM design project --- diff --git a/.gitignore b/.gitignore index edb675f..8507be3 100644 --- a/.gitignore +++ b/.gitignore @@ -1,24 +1 @@ -*~ -*.log -*.rpt -netlists version.vhd -*.jhd -*.naf -*.sort -*.srp -*.sym -*tmpl.vhd -*.log -workdir -workdir_* -*.bit -*.kate-swp* -*.kate-swap* -.run_manager.ini -reportview.xml -.kateproject.d -cts/project* -cbmnet/project* -cbmnet/sim* - diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..fd51954 --- /dev/null +++ b/Makefile @@ -0,0 +1,194 @@ +# Call . /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env + +TARGET=adcmv3 +FAMILYNAME=LatticeECP3 +DEVICENAME=LFE3-150EA +PACKAGE=FPBGA672 +SPEEDGRADE=8 + +TIMESTAMP=$(shell date '+%s') +VERSION=$(shell cat version-major-minor.txt) + +# ------------------------------------------------------------------------------------ + +.PHONY: all +all: workdir/$(TARGET).bit + +.PHONY: clean +clean: + rm -rf workdir/* + +.PHONY: distclean +distclean: + rm -rf workdir/* + +.PHONY: checkenv +checkenv: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "--------------- Check Lattice Environment ---------------" + @echo "----------------------------------------------------------------------" + @if [ -n "${LM_LICENSE_FILE}" ] ; then \ + echo "Lattice Environment is: ${LM_LICENSE_FILE}"; \ + else \ + echo "------> Lattice Environment is not set"; \ + exit 1; \ + fi + +# ------------------------------------------------------------------------------------ + +# Bitgen +workdir/$(TARGET).bit: workdir/$(TARGET).ncd + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Bitgen ------------------------------------------------" + @echo "----------------------------------------------------------------------" + cd workdir && \ + bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $(TARGET).ncd \ + $(TARGET).bit $(TARGET).prf + @$(MAKE) report + @$(MAKE) error + +# Place and Route (multipar) +workdir/$(TARGET).ncd: workdir/$(TARGET)_map.ncd + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Place and Route (multipar)-----------------------------" + @echo "----------------------------------------------------------------------" + rm -rf workdir/$(TARGET).ncd workdir/$(TARGET).dir + cd workdir && \ + par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf + cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd + +# Mapper +workdir/$(TARGET)_map.ncd: workdir/$(TARGET).ngd $(TARGET).lpf + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Mapper ------------------------------------------------" + @echo "----------------------------------------------------------------------" + cd workdir && \ + map -retime -split_node -a $(FAMILYNAME) -p $(DEVICENAME) \ + -t $(PACKAGE) -s $(SPEEDGRADE) $(TARGET).ngd -pr $(TARGET).prf \ + -o $(TARGET)_map.ncd -mp $(TARGET).mrp $(TARGET).lpf + +# EDIF 2 NGD +workdir/$(TARGET).ngd: workdir/$(TARGET).edf + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- EDIF 2 NGD---------------------------------------------" + @echo "----------------------------------------------------------------------" + cd workdir && \ + edif2ngd -l $(FAMILYNAME) -d $(DEVICENAME) \$(TARGET).edf $(TARGET).ngo + cd workdir && \ + edfupdate -t $(TARGET).tcy -w $(TARGET).ngo -m $(TARGET).ngo \ + $(TARGET).ngx + cd workdir && \ + ngdbuild -a $(FAMILYNAME) -d $(DEVICENAME) -dt $(TARGET).ngo \ + $(TARGET).ngd + +# VHDL / Verilog Compiler +workdir/$(TARGET).edf: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "--------------- Build All --------------------------------------------" + @echo "----------------------------------------------------------------------" + @$(MAKE) checkenv + @$(MAKE) workdir + @$(MAKE) version + + @echo "" + @echo "----------------------------------------------------------------------" + @echo "--------------- VHDL Compiler ----------------------------------------" + @echo "----------------------------------------------------------------------" + synpwrap -prj $(TARGET).prj || \ + (grep "@E" workdir/$(TARGET).srr && exit 2) + +# ------------------------------------------------------------------------------------ + +# Version File +.PHONY: version +version: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "--------------- Version File -----------------------------------------" + @echo "----------------------------------------------------------------------" + @echo "-- attention, automatically generated. Don't change by hand." > version.vhd + @echo "library ieee;" >> version.vhd + @echo "USE IEEE.std_logic_1164.ALL;" >> version.vhd + @echo "USE IEEE.std_logic_ARITH.ALL;" >> version.vhd + @echo "USE IEEE.std_logic_UNSIGNED.ALL;" >> version.vhd + @echo "use ieee.numeric_std.all;" >> version.vhd + @echo "" >> version.vhd + @echo "package version is" >> version.vhd + @echo "" >> version.vhd + @echo " constant VERSION_NUMBER_TIME : integer := $(TIMESTAMP);" >> version.vhd + @echo -n " constant VERSION_NUMBER : integer := " >> version.vhd + @echo "to_integer(x\"$(VERSION)\");" >> version.vhd + @echo "" >> version.vhd + @echo "end package version;" >> version.vhd + @cat version.vhd + +# Setup Workdir +.PHONY: workdir +workdir: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Setup Workdir -----------------------------------------" + @echo "----------------------------------------------------------------------" + mkdir -p workdir + cd workdir && ../../base/linkdesignfiles.sh + cp $(TARGET).lpf workdir/$(TARGET).lpf +# cat $(TARGET)_constraints.lpf >> workdir/$(TARGET).lpf + cp nodelist.txt workdir/ + +# Timing Report +.PHONY: report +report: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Timing Report -----------------------------------------" + @echo "----------------------------------------------------------------------" + cd workdir && \ + iotiming -s $(TARGET).ncd $(TARGET).prf + cd workdir && \ + trce -c -v 15 -o $(TARGET).twr.setup $(TARGET).ncd $(TARGET).prf + cd workdir && \ + trce -hld -c -v 5 -o $(TARGET).twr.hold $(TARGET).ncd $(TARGET).prf + cd workdir && \ + ltxt2ptxt $(TARGET).ncd + +# Error Check +.PHONY: error +error: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Error Check -----------------------------------------" + @echo "----------------------------------------------------------------------" + @echo -e "\n$(TARGET).mrp:" + @grep "Semantic error" ./workdir/$(TARGET).mrp || exit 0 + + @echo -e "\n$(TARGET).twr.setup:" + @grep 'Error: The following path exceeds requirements by' ./workdir/$(TARGET).twr.setup \ + || exit 0 + + @echo -e "\n$(TARGET).twr.hold:" + @grep "Error:" ./workdir/$(TARGET).twr.hold || exit 0 + + @echo -e "\nCircuit Loops:" + @grep "potential circuit loops" ./workdir/* || exit 0 + +# ------------------------------------------------------------------------------------ +# Extract dependencies from project file +#.PHONY: $(TARGET).dep +#$(TARGET).dep: +# @echo "" +# @echo "----------------------------------------------------------------------" +# @echo "--------------- Extract Dependencies from Project File ---------------" +# @echo "----------------------------------------------------------------------" +# grep 'add_file' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \ +# | xargs echo "workdir/$(TARGET).edf:" > $(TARGET).dep +# grep 'map_dep' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \ +# | xargs echo "workdir/$(TARGET)_map.ncd:" >> $(TARGET).dep +# +#-include $(TARGET).dep + diff --git a/adcmv3.prj b/adcmv3.prj index 23224e7..ee7a2ef 100644 --- a/adcmv3.prj +++ b/adcmv3.prj @@ -5,8 +5,8 @@ # add_file options add_file -vhdl -lib work "version.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "source/adcmv3_components.vhd" add_file -vhdl -lib work "source/adcmv3_components2.vhd" @@ -83,45 +83,45 @@ add_file -vhdl -lib work "cores/pll_40m.vhd" add_file -vhdl -lib work "cores/slv_onewire_dpram.vhd" # TrbNet design files -add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" -add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" -add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" -add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_sbuf5.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_sbuf6.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" -add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" -add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" -add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd" -add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd" -add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" -add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" -add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd" -add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" -add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" -add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" -add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" -# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_2.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd" +# add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd" # add_file -vhdl -lib work "source/sfp_rx_handler.vhd" # implementation: "workdir" diff --git a/cores/adc_apv_map_mem.srp b/cores/adc_apv_map_mem.srp new file mode 100644 index 0000000..c4a1fc4 --- /dev/null +++ b/cores/adc_apv_map_mem.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Nov 04 16:11:12 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e + Circuit name : adc_apv_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem + EDIF output : suppressed + VHDL output : adc_apv_map_mem.vhd + VHDL template : adc_apv_map_mem_tmpl.vhd + VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_apv_map_mem.srp + Element Usage : + ROM128X1 : 4 + Estimated Resource Usage: + LUT : 16 diff --git a/cores/adc_apv_map_mem_generate.log b/cores/adc_apv_map_mem_generate.log new file mode 100644 index 0000000..e7ce86b --- /dev/null +++ b/cores/adc_apv_map_mem_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Nov 04 16:11:12 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem -memformat orca -e + Circuit name : adc_apv_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Data width : 4 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv3/src/adc_apv_mapping.mem + EDIF output : suppressed + VHDL output : adc_apv_map_mem.vhd + VHDL template : adc_apv_map_mem_tmpl.vhd + VHDL testbench : tb_adc_apv_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_apv_map_mem.srp + Estimated Resource Usage: + LUT : 16 + +END SCUBA Module Synthesis + +File: ..\src\adc_apv_map_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/adc_apv_map_mem_tmpl.vhd b/cores/adc_apv_map_mem_tmpl.vhd new file mode 100644 index 0000000..0386612 --- /dev/null +++ b/cores/adc_apv_map_mem_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Wed Nov 04 16:11:12 2009 + +-- parameterized module component declaration +component adc_apv_map_mem + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : adc_apv_map_mem + port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/cores/adc_ch_in.srp b/cores/adc_ch_in.srp new file mode 100644 index 0000000..e3fea71 --- /dev/null +++ b/cores/adc_ch_in.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Apr 24 11:41:10 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_ch_in -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type iol -mode in -width 1 -gear 1 -del 16 -e + Circuit name : adc_ch_in + Module type : iol + Module Version : 3.6 + Ports : + Inputs : Del[3:0], ECLK, SCLK, Rst, Data[0:0] + Outputs : Q[1:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : adc_ch_in.vhd + VHDL template : adc_ch_in_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_ch_in.srp + Element Usage : + IB : 1 + IDDRFXA : 1 + DELAYB : 1 + Estimated Resource Usage: diff --git a/cores/adc_ch_in_tmpl.vhd b/cores/adc_ch_in_tmpl.vhd new file mode 100644 index 0000000..fc15c1b --- /dev/null +++ b/cores/adc_ch_in_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 3.6 +-- Fri Apr 24 11:41:10 2009 + +-- parameterized module component declaration +component adc_ch_in + port (Del: in std_logic_vector(3 downto 0); ECLK: in std_logic; + SCLK: in std_logic; Rst: in std_logic; + Data: in std_logic_vector(0 downto 0); + Q: out std_logic_vector(1 downto 0)); +end component; + +-- parameterized module component instance +__ : adc_ch_in + port map (Del(3 downto 0)=>__, ECLK=>__, SCLK=>__, Rst=>__, Data(0 downto 0)=>__, + Q(1 downto 0)=>__); diff --git a/cores/adc_onewire_map_mem.srp b/cores/adc_onewire_map_mem.srp new file mode 100644 index 0000000..a45415a --- /dev/null +++ b/cores/adc_onewire_map_mem.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Nov 05 10:27:05 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e + Circuit name : adc_onewire_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem + EDIF output : suppressed + VHDL output : adc_onewire_map_mem.vhd + VHDL template : adc_onewire_map_mem_tmpl.vhd + VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_onewire_map_mem.srp + Element Usage : + ROM128X1 : 4 + Estimated Resource Usage: + LUT : 16 diff --git a/cores/adc_onewire_map_mem_generate.log b/cores/adc_onewire_map_mem_generate.log new file mode 100644 index 0000000..ed0c0f5 --- /dev/null +++ b/cores/adc_onewire_map_mem_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Nov 05 10:27:05 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_onewire_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem -memformat orca -e + Circuit name : adc_onewire_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Data width : 4 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\adc_onewire_mapping.mem + EDIF output : suppressed + VHDL output : adc_onewire_map_mem.vhd + VHDL template : adc_onewire_map_mem_tmpl.vhd + VHDL testbench : tb_adc_onewire_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_onewire_map_mem.srp + Estimated Resource Usage: + LUT : 16 + +END SCUBA Module Synthesis + +File: adc_onewire_map_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/adc_onewire_map_mem_tmpl.vhd b/cores/adc_onewire_map_mem_tmpl.vhd new file mode 100644 index 0000000..8659f3d --- /dev/null +++ b/cores/adc_onewire_map_mem_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Thu Nov 05 10:27:05 2009 + +-- parameterized module component declaration +component adc_onewire_map_mem + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : adc_onewire_map_mem + port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/cores/adc_pll_tmpl.vhd b/cores/adc_pll_tmpl.vhd new file mode 100644 index 0000000..221ccc4 --- /dev/null +++ b/cores/adc_pll_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 4.2 +-- Thu Apr 16 11:20:59 2009 + +-- parameterized module component declaration +component adc_pll + port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic; + LOCK: out std_logic); +end component; + +-- parameterized module component instance +__ : adc_pll + port map (CLK=>__, RESET=>__, CLKOP=>__, LOCK=>__); diff --git a/cores/adc_snoop_mem.srp b/cores/adc_snoop_mem.srp new file mode 100644 index 0000000..8f43024 --- /dev/null +++ b/cores/adc_snoop_mem.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Oct 13 16:03:30 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + Circuit name : adc_snoop_mem + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[15:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : adc_snoop_mem.vhd + VHDL template : adc_snoop_mem_tmpl.vhd + VHDL testbench : tb_adc_snoop_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_snoop_mem.srp + Element Usage : + DP16KB : 1 + Estimated Resource Usage: + EBR : 1 diff --git a/cores/adc_snoop_mem_generate.log b/cores/adc_snoop_mem_generate.log new file mode 100644 index 0000000..6e9dac6 --- /dev/null +++ b/cores/adc_snoop_mem_generate.log @@ -0,0 +1,44 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Oct 13 16:03:30 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n adc_snoop_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 10 -rwidth 16 -waddr_width 10 -wwidth 16 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + Circuit name : adc_snoop_mem + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[9:0], RdAddress[9:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[15:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : adc_snoop_mem.vhd + VHDL template : adc_snoop_mem_tmpl.vhd + VHDL testbench : tb_adc_snoop_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : adc_snoop_mem.srp + Estimated Resource Usage: + EBR : 1 + +END SCUBA Module Synthesis + +File: adc_snoop_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/adc_snoop_mem_tmpl.vhd b/cores/adc_snoop_mem_tmpl.vhd new file mode 100644 index 0000000..899a664 --- /dev/null +++ b/cores/adc_snoop_mem_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +-- Tue Oct 13 16:03:30 2009 + +-- parameterized module component declaration +component adc_snoop_mem + port (WrAddress: in std_logic_vector(9 downto 0); + RdAddress: in std_logic_vector(9 downto 0); + Data: in std_logic_vector(15 downto 0); WE: in std_logic; + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; WrClock: in std_logic; + WrClockEn: in std_logic; Q: out std_logic_vector(15 downto 0)); +end component; + +-- parameterized module component instance +__ : adc_snoop_mem + port map (WrAddress(9 downto 0)=>__, RdAddress(9 downto 0)=>__, Data(15 downto 0)=>__, + WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__, + WrClockEn=>__, Q(15 downto 0)=>__); diff --git a/cores/apv_adc_map_mem.srp b/cores/apv_adc_map_mem.srp new file mode 100644 index 0000000..5e3fe40 --- /dev/null +++ b/cores/apv_adc_map_mem.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Nov 04 16:10:56 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e + Circuit name : apv_adc_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem + EDIF output : suppressed + VHDL output : apv_adc_map_mem.vhd + VHDL template : apv_adc_map_mem_tmpl.vhd + VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : apv_adc_map_mem.srp + Element Usage : + ROM128X1 : 4 + Estimated Resource Usage: + LUT : 16 diff --git a/cores/apv_adc_map_mem_generate.log b/cores/apv_adc_map_mem_generate.log new file mode 100644 index 0000000..ea70ce7 --- /dev/null +++ b/cores/apv_adc_map_mem_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Nov 04 16:10:56 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_adc_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem -memformat orca -e + Circuit name : apv_adc_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Data width : 4 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv3/src/apv_adc_mapping.mem + EDIF output : suppressed + VHDL output : apv_adc_map_mem.vhd + VHDL template : apv_adc_map_mem_tmpl.vhd + VHDL testbench : tb_apv_adc_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : apv_adc_map_mem.srp + Estimated Resource Usage: + LUT : 16 + +END SCUBA Module Synthesis + +File: ..\src\apv_adc_map_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/apv_adc_map_mem_tmpl.vhd b/cores/apv_adc_map_mem_tmpl.vhd new file mode 100644 index 0000000..b14294d --- /dev/null +++ b/cores/apv_adc_map_mem_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Wed Nov 04 16:10:56 2009 + +-- parameterized module component declaration +component apv_adc_map_mem + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : apv_adc_map_mem + port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/cores/apv_map_mem.srp b/cores/apv_map_mem.srp new file mode 100644 index 0000000..d3b5189 --- /dev/null +++ b/cores/apv_map_mem.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Oct 14 17:47:59 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e + Circuit name : apv_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem + EDIF output : suppressed + VHDL output : apv_map_mem.vhd + VHDL template : apv_map_mem_tmpl.vhd + VHDL testbench : tb_apv_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : apv_map_mem.srp + Element Usage : + ROM128X1 : 4 + Estimated Resource Usage: + LUT : 16 diff --git a/cores/apv_map_mem_generate.log b/cores/apv_map_mem_generate.log new file mode 100644 index 0000000..49afe96 --- /dev/null +++ b/cores/apv_map_mem_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Wed Oct 14 17:47:59 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n apv_map_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 7 -num_words 128 -data_width 4 -outdata UNREGISTERED -memfile i:/vhdl_pro/adcmv2/src/apv_mapping.mem -memformat orca -e + Circuit name : apv_map_mem + Module type : rom + Module Version : 2.4 + Address width : 7 + Data width : 4 + Ports : + Inputs : Address[6:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : i:/vhdl_pro/adcmv2/src/apv_mapping.mem + EDIF output : suppressed + VHDL output : apv_map_mem.vhd + VHDL template : apv_map_mem_tmpl.vhd + VHDL testbench : tb_apv_map_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : apv_map_mem.srp + Estimated Resource Usage: + LUT : 16 + +END SCUBA Module Synthesis + +File: ..\src\apv_map_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/apv_map_mem_tmpl.vhd b/cores/apv_map_mem_tmpl.vhd new file mode 100644 index 0000000..daaa9a8 --- /dev/null +++ b/cores/apv_map_mem_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Wed Oct 14 17:47:59 2009 + +-- parameterized module component declaration +component apv_map_mem + port (Address: in std_logic_vector(6 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : apv_map_mem + port map (Address(6 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/cores/crossover.srp b/cores/crossover.srp new file mode 100644 index 0000000..dd496d7 --- /dev/null +++ b/cores/crossover.srp @@ -0,0 +1,43 @@ +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 11:16:48 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e + Circuit name : crossover + Module type : ebfifo + Module Version : 5.0 + Ports : + Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : crossover.vhd + VHDL template : crossover_tmpl.vhd + VHDL testbench : tb_crossover_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : crossover.srp + Element Usage : + AGEB2 : 6 + AND2 : 2 + CU2 : 6 + FADD2B : 8 + FSUB2B : 6 + FD1P3BX : 2 + FD1P3DX : 124 + FD1S3BX : 1 + FD1S3DX : 31 + INV : 2 + OR2 : 1 + ROM16X1 : 13 + DPR16X4A : 24 + XOR2 : 10 + Estimated Resource Usage: + LUT : 78 + DRAM : 24 + Reg : 158 diff --git a/cores/crossover_generate.log b/cores/crossover_generate.log new file mode 100644 index 0000000..4a2c3aa --- /dev/null +++ b/cores/crossover_generate.log @@ -0,0 +1,46 @@ +Starting process: + +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 11:16:48 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n crossover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -pfu_fifo -addr_width 4 -data_width 96 -num_words 16 -rdata_width 96 -no_enable -pe -1 -pf -1 -rfill -fill -e + Circuit name : crossover + Module type : ebfifo + Module Version : 5.0 + Ports : + Inputs : Data[95:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset + Outputs : Q[95:0], WCNT[4:0], RCNT[4:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : crossover.vhd + VHDL template : crossover_tmpl.vhd + VHDL testbench : tb_crossover_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : crossover.srp + Estimated Resource Usage: + LUT : 78 + DRAM : 24 + Reg : 158 + +END SCUBA Module Synthesis + +File: ..\src\crossover.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/crossover_tmpl.vhd b/cores/crossover_tmpl.vhd new file mode 100644 index 0000000..bbdc80d --- /dev/null +++ b/cores/crossover_tmpl.vhd @@ -0,0 +1,20 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 5.0 +-- Fri Nov 20 11:16:48 2009 + +-- parameterized module component declaration +component crossover + port (Data: in std_logic_vector(95 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(95 downto 0); + WCNT: out std_logic_vector(4 downto 0); + RCNT: out std_logic_vector(4 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : crossover + port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, WCNT(4 downto 0)=>__, + RCNT(4 downto 0)=>__, Empty=>__, Full=>__); diff --git a/cores/decoder_8bit_tmpl.vhd b/cores/decoder_8bit_tmpl.vhd new file mode 100644 index 0000000..fb3c041 --- /dev/null +++ b/cores/decoder_8bit_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 2.4 +-- Tue Mar 03 09:38:59 2009 + +-- parameterized module component declaration +component decoder_8bit + port (Address: in std_logic_vector(7 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : decoder_8bit + port map (Address(7 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/cores/dll_100m_tmpl.vhd b/cores/dll_100m_tmpl.vhd new file mode 100644 index 0000000..dfc2502 --- /dev/null +++ b/cores/dll_100m_tmpl.vhd @@ -0,0 +1,15 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 3.2 +-- Thu Jan 29 18:49:16 2009 + +-- parameterized module component declaration +component dll_100m + port (clk: in std_logic; resetn: in std_logic; + aluhold: in std_logic; clkop: out std_logic; + clkos: out std_logic; lock: out std_logic); +end component; + +-- parameterized module component instance +__ : dll_100m + port map (clk=>__, resetn=>__, aluhold=>__, clkop=>__, clkos=>__, + lock=>__); diff --git a/cores/dpram_8x19.srp b/cores/dpram_8x19.srp new file mode 100644 index 0000000..ded8bac --- /dev/null +++ b/cores/dpram_8x19.srp @@ -0,0 +1,32 @@ +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 19:14:28 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e + Circuit name : dpram_8x19 + Module type : sdpram + Module Version : 3.4 + Address width : 4 + Ports : + Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0] + Outputs : Q[18:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : dpram_8x19.vhd + VHDL template : dpram_8x19_tmpl.vhd + VHDL testbench : tb_dpram_8x19_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : dpram_8x19.srp + Element Usage : + ROM16X1 : 1 + DPR16X4A : 5 + Estimated Resource Usage: + LUT : 1 + DRAM : 5 diff --git a/cores/dpram_8x19_generate.log b/cores/dpram_8x19_generate.log new file mode 100644 index 0000000..f50d5d2 --- /dev/null +++ b/cores/dpram_8x19_generate.log @@ -0,0 +1,48 @@ +Starting process: + +SCUBA, Version ispLever_v72_PROD_Build (44) +Fri Nov 20 19:14:28 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e + Circuit name : dpram_8x19 + Module type : sdpram + Module Version : 3.4 + Address width : 4 + Data width : 19 + Ports : + Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0] + Outputs : Q[18:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : dpram_8x19.vhd + VHDL template : dpram_8x19_tmpl.vhd + VHDL testbench : tb_dpram_8x19_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : dpram_8x19.srp + Estimated Resource Usage: + LUT : 1 + DRAM : 5 + +END SCUBA Module Synthesis + +File: ..\src\dpram_8x19.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/dpram_8x19_tmpl.vhd b/cores/dpram_8x19_tmpl.vhd new file mode 100644 index 0000000..9985f90 --- /dev/null +++ b/cores/dpram_8x19_tmpl.vhd @@ -0,0 +1,17 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 3.4 +-- Fri Nov 20 19:14:28 2009 + +-- parameterized module component declaration +component dpram_8x19 + port (WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(18 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + Q: out std_logic_vector(18 downto 0)); +end component; + +-- parameterized module component instance +__ : dpram_8x19 + port map (WrAddress(3 downto 0)=>__, Data(18 downto 0)=>__, WrClock=>__, + WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, Q(18 downto 0)=>__); diff --git a/cores/eds_buffer_dpram_tmpl.vhd b/cores/eds_buffer_dpram_tmpl.vhd new file mode 100644 index 0000000..95c9ae0 --- /dev/null +++ b/cores/eds_buffer_dpram_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v71_PROD_Build (58) +-- Module Version: 3.3 +-- Fri Aug 29 14:24:36 2008 + +-- parameterized module component declaration +component eds_buffer_dpram + port (WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(39 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; Q: out std_logic_vector(39 downto 0)); +end component; + +-- parameterized module component instance +__ : eds_buffer_dpram + port map (WrAddress(3 downto 0)=>__, Data(39 downto 0)=>__, WrClock=>__, + WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__, + RdClockEn=>__, Reset=>__, Q(39 downto 0)=>__); diff --git a/cores/fifo_16x11.srp b/cores/fifo_16x11.srp new file mode 100644 index 0000000..5b4cd3b --- /dev/null +++ b/cores/fifo_16x11.srp @@ -0,0 +1,42 @@ +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Thu Mar 11 10:33:40 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_16x11 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -pfu_fifo -addr_width 4 -data_width 11 -num_words 16 -no_enable -pe -1 -pf -1 -fill -e + Circuit name : fifo_16x11 + Module type : fifoblk + Module Version : 4.7 + Ports : + Inputs : Data[10:0], Clock, WrEn, RdEn, Reset + Outputs : Q[10:0], WCNT[4:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : fifo_16x11.vhd + VHDL template : fifo_16x11_tmpl.vhd + VHDL testbench : tb_fifo_16x11_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : fifo_16x11.srp + Element Usage : + AGEB2 : 3 + ALEB2 : 3 + AND2 : 3 + CU2 : 6 + CB2 : 3 + FADD2B : 7 + FD1P3DX : 26 + FD1S3BX : 1 + FD1S3DX : 1 + INV : 4 + ROM16X1 : 3 + DPR16X4A : 3 + XOR2 : 1 + Estimated Resource Usage: + LUT : 51 + DRAM : 3 + Reg : 28 diff --git a/cores/fifo_16x11_generate.log b/cores/fifo_16x11_generate.log new file mode 100644 index 0000000..ddb9b66 --- /dev/null +++ b/cores/fifo_16x11_generate.log @@ -0,0 +1,46 @@ +Starting process: + +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Thu Mar 11 10:33:40 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_16x11 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -pfu_fifo -addr_width 4 -data_width 11 -num_words 16 -no_enable -pe -1 -pf -1 -fill -e + Circuit name : fifo_16x11 + Module type : fifoblk + Module Version : 4.7 + Ports : + Inputs : Data[10:0], Clock, WrEn, RdEn, Reset + Outputs : Q[10:0], WCNT[4:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : fifo_16x11.vhd + VHDL template : fifo_16x11_tmpl.vhd + VHDL testbench : tb_fifo_16x11_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : fifo_16x11.srp + Estimated Resource Usage: + LUT : 51 + DRAM : 3 + Reg : 28 + +END SCUBA Module Synthesis + +File: ..\src\fifo_16x11.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/fifo_16x11_tmpl.vhd b/cores/fifo_16x11_tmpl.vhd new file mode 100644 index 0000000..ca37eec --- /dev/null +++ b/cores/fifo_16x11_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 4.7 +-- Thu Mar 11 10:33:40 2010 + +-- parameterized module component declaration +component fifo_16x11 + port (Data: in std_logic_vector(10 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(10 downto 0); + WCNT: out std_logic_vector(4 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_16x11 + port map (Data(10 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(10 downto 0)=>__, WCNT(4 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/cores/fifo_1kx18.srp b/cores/fifo_1kx18.srp new file mode 100644 index 0000000..0b4cdc7 --- /dev/null +++ b/cores/fifo_1kx18.srp @@ -0,0 +1,42 @@ +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Thu Apr 29 14:49:48 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_1kx18 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf 1020 -fill -e + Circuit name : fifo_1kx18 + Module type : fifoblk + Module Version : 4.8 + Ports : + Inputs : Data[17:0], Clock, WrEn, RdEn, Reset + Outputs : Q[17:0], WCNT[10:0], Empty, Full, AlmostFull + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : fifo_1kx18.vhd + VHDL template : fifo_1kx18_tmpl.vhd + VHDL testbench : tb_fifo_1kx18_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : fifo_1kx18.srp + Element Usage : + AGEB2 : 12 + ALEB2 : 6 + AND2 : 4 + CU2 : 12 + CB2 : 6 + FADD2B : 9 + FD1P3DX : 33 + FD1S3BX : 1 + FD1S3DX : 2 + INV : 9 + ROM16X1 : 2 + XOR2 : 1 + DP16KB : 1 + Estimated Resource Usage: + LUT : 97 + EBR : 1 + Reg : 36 diff --git a/cores/fifo_1kx18_generate.log b/cores/fifo_1kx18_generate.log new file mode 100644 index 0000000..7033f18 --- /dev/null +++ b/cores/fifo_1kx18_generate.log @@ -0,0 +1,46 @@ +Starting process: + +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Thu Apr 29 14:49:48 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_1kx18 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf 1020 -fill -e + Circuit name : fifo_1kx18 + Module type : fifoblk + Module Version : 4.8 + Ports : + Inputs : Data[17:0], Clock, WrEn, RdEn, Reset + Outputs : Q[17:0], WCNT[10:0], Empty, Full, AlmostFull + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : fifo_1kx18.vhd + VHDL template : fifo_1kx18_tmpl.vhd + VHDL testbench : tb_fifo_1kx18_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : fifo_1kx18.srp + Estimated Resource Usage: + LUT : 97 + EBR : 1 + Reg : 36 + +END SCUBA Module Synthesis + +File: ..\src\fifo_1kx18.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/fifo_1kx18_tmpl.vhd b/cores/fifo_1kx18_tmpl.vhd new file mode 100644 index 0000000..6d4b459 --- /dev/null +++ b/cores/fifo_1kx18_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v80_SP1_Build +-- Module Version: 4.8 +-- Thu Apr 29 14:49:48 2010 + +-- parameterized module component declaration +component fifo_1kx18 + port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); + WCNT: out std_logic_vector(10 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostFull: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_1kx18 + port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(17 downto 0)=>__, WCNT(10 downto 0)=>__, Empty=>__, + Full=>__, AlmostFull=>__); diff --git a/cores/fifo_2kx27_tmpl.vhd b/cores/fifo_2kx27_tmpl.vhd new file mode 100644 index 0000000..7e0698c --- /dev/null +++ b/cores/fifo_2kx27_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) +-- Module Version: 4.5 +-- Fri Feb 27 12:01:58 2009 + +-- parameterized module component declaration +component fifo_2kx27 + port (Data: in std_logic_vector(26 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(26 downto 0); + WCNT: out std_logic_vector(11 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : fifo_2kx27 + port map (Data(26 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(26 downto 0)=>__, WCNT(11 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/cores/frame_status_mem.srp b/cores/frame_status_mem.srp new file mode 100644 index 0000000..cf54009 --- /dev/null +++ b/cores/frame_status_mem.srp @@ -0,0 +1,34 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 13:08:21 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e + Circuit name : frame_status_mem + Module type : sdpram + Module Version : 3.5 + Address width : 4 + Ports : + Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset + Outputs : Q[11:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : frame_status_mem.vhd + VHDL template : frame_status_mem_tmpl.vhd + VHDL testbench : tb_frame_status_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : frame_status_mem.srp + Element Usage : + FD1P3DX : 12 + ROM16X1 : 1 + DPR16X4A : 3 + Estimated Resource Usage: + LUT : 1 + DRAM : 3 + Reg : 12 diff --git a/cores/frame_status_mem_generate.log b/cores/frame_status_mem_generate.log new file mode 100644 index 0000000..c0b628b --- /dev/null +++ b/cores/frame_status_mem_generate.log @@ -0,0 +1,49 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 13:08:21 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n frame_status_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 12 -waddr_width 4 -wwidth 12 -rnum_words 16 -wnum_words 16 -outData REGISTERED -e + Circuit name : frame_status_mem + Module type : sdpram + Module Version : 3.5 + Address width : 4 + Data width : 12 + Ports : + Inputs : WrAddress[3:0], Data[11:0], WrClock, WE, WrClockEn, RdAddress[3:0], RdClock, RdClockEn, Reset + Outputs : Q[11:0] + I/O buffer : not inserted + Clock edge : rising edge + EDIF output : suppressed + VHDL output : frame_status_mem.vhd + VHDL template : frame_status_mem_tmpl.vhd + VHDL testbench : tb_frame_status_mem_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : frame_status_mem.srp + Estimated Resource Usage: + LUT : 1 + DRAM : 3 + Reg : 12 + +END SCUBA Module Synthesis + +File: frame_status_mem.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/frame_status_mem_tmpl.vhd b/cores/frame_status_mem_tmpl.vhd new file mode 100644 index 0000000..9bb11c2 --- /dev/null +++ b/cores/frame_status_mem_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 3.5 +-- Mon Sep 14 13:08:21 2009 + +-- parameterized module component declaration +component frame_status_mem + port (WrAddress: in std_logic_vector(3 downto 0); + Data: in std_logic_vector(11 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress: in std_logic_vector(3 downto 0); + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; Q: out std_logic_vector(11 downto 0)); +end component; + +-- parameterized module component instance +__ : frame_status_mem + port map (WrAddress(3 downto 0)=>__, Data(11 downto 0)=>__, WrClock=>__, + WE=>__, WrClockEn=>__, RdAddress(3 downto 0)=>__, RdClock=>__, + RdClockEn=>__, Reset=>__, Q(11 downto 0)=>__); diff --git a/cores/input_bram.srp b/cores/input_bram.srp new file mode 100644 index 0000000..22a45ab --- /dev/null +++ b/cores/input_bram.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 12:58:01 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + Circuit name : input_bram + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[17:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : input_bram.vhd + VHDL template : input_bram_tmpl.vhd + VHDL testbench : tb_input_bram_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : input_bram.srp + Element Usage : + DP16KB : 2 + Estimated Resource Usage: + EBR : 2 diff --git a/cores/input_bram_generate.log b/cores/input_bram_generate.log new file mode 100644 index 0000000..c01e233 --- /dev/null +++ b/cores/input_bram_generate.log @@ -0,0 +1,44 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 12:58:01 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n input_bram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 11 -rwidth 18 -waddr_width 11 -wwidth 18 -rnum_words 2048 -wnum_words 2048 -outdata REGISTERED -resetmode SYNC -cascade -1 -e + Circuit name : input_bram + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[10:0], RdAddress[10:0], Data[17:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[17:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : input_bram.vhd + VHDL template : input_bram_tmpl.vhd + VHDL testbench : tb_input_bram_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : input_bram.srp + Estimated Resource Usage: + EBR : 2 + +END SCUBA Module Synthesis + +File: ..\src\input_bram.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/input_bram_tmpl.vhd b/cores/input_bram_tmpl.vhd new file mode 100644 index 0000000..7b37858 --- /dev/null +++ b/cores/input_bram_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +-- Mon Sep 14 12:58:01 2009 + +-- parameterized module component declaration +component input_bram + port (WrAddress: in std_logic_vector(10 downto 0); + RdAddress: in std_logic_vector(10 downto 0); + Data: in std_logic_vector(17 downto 0); WE: in std_logic; + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; WrClock: in std_logic; + WrClockEn: in std_logic; Q: out std_logic_vector(17 downto 0)); +end component; + +-- parameterized module component instance +__ : input_bram + port map (WrAddress(10 downto 0)=>__, RdAddress(10 downto 0)=>__, + Data(17 downto 0)=>__, WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, + WrClock=>__, WrClockEn=>__, Q(17 downto 0)=>__); diff --git a/cores/msg_file.log b/cores/msg_file.log new file mode 100644 index 0000000..512552b --- /dev/null +++ b/cores/msg_file.log @@ -0,0 +1,33 @@ +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Thu May 20 14:41:10 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n test_fifo2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -e + Circuit name : test_fifo2 + Module type : fifoblk + Module Version : 4.8 + Ports : + Inputs : Data[17:0], Clock, WrEn, RdEn, Reset + Outputs : Q[17:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : test_fifo2.vhd + VHDL template : test_fifo2_tmpl.vhd + VHDL testbench : tb_test_fifo2_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : test_fifo2.srp + Estimated Resource Usage: + LUT : 80 + EBR : 1 + Reg : 35 + +END SCUBA Module Synthesis + diff --git a/cores/mult_3x8.srp b/cores/mult_3x8.srp new file mode 100644 index 0000000..aa3ac4e --- /dev/null +++ b/cores/mult_3x8.srp @@ -0,0 +1,32 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Oct 29 11:23:03 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e + Circuit name : mult_3x8 + Module type : dspmult_a + Module Version : 4.3 + Ports : + Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0] + Outputs : Result[10:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : mult_3x8.vhd + VHDL template : mult_3x8_tmpl.vhd + VHDL testbench : tb_mult_3x8_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : mult_3x8.srp + Element Usage : + AND2 : 9 + FADD2B : 6 + FD1P3DX : 11 + MULT2 : 4 + Estimated Resource Usage: + LUT : 29 + Reg : 11 diff --git a/cores/mult_3x8_generate.log b/cores/mult_3x8_generate.log new file mode 100644 index 0000000..a8615eb --- /dev/null +++ b/cores/mult_3x8_generate.log @@ -0,0 +1,45 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Oct 29 11:23:03 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n mult_3x8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type dspmult -simple_portname -pfu_mult -widtha 3 -widthb 8 -widthp 11 -PL_stages 0 -output_reg -clk0 -ce0 -rst0 -e + Circuit name : mult_3x8 + Module type : dspmult_a + Module Version : 4.3 + Ports : + Inputs : Clock, ClkEn, Aclr, DataA[2:0], DataB[7:0] + Outputs : Result[10:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : mult_3x8.vhd + VHDL template : mult_3x8_tmpl.vhd + VHDL testbench : tb_mult_3x8_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : mult_3x8.srp + Estimated Resource Usage: + LUT : 29 + Reg : 11 + +END SCUBA Module Synthesis + +File: ..\src\mult_3x8.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/mult_3x8_tmpl.vhd b/cores/mult_3x8_tmpl.vhd new file mode 100644 index 0000000..9c5c888 --- /dev/null +++ b/cores/mult_3x8_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 4.3 +-- Thu Oct 29 11:23:03 2009 + +-- parameterized module component declaration +component mult_3x8 + port (Clock: in std_logic; ClkEn: in std_logic; + Aclr: in std_logic; DataA: in std_logic_vector(2 downto 0); + DataB: in std_logic_vector(7 downto 0); + Result: out std_logic_vector(10 downto 0)); +end component; + +-- parameterized module component instance +__ : mult_3x8 + port map (Clock=>__, ClkEn=>__, Aclr=>__, DataA(2 downto 0)=>__, + DataB(7 downto 0)=>__, Result(10 downto 0)=>__); diff --git a/cores/onewire_spare_one.srp b/cores/onewire_spare_one.srp new file mode 100644 index 0000000..b0b1cc6 --- /dev/null +++ b/cores/onewire_spare_one.srp @@ -0,0 +1,30 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Nov 05 15:51:35 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e + Circuit name : onewire_spare_one + Module type : rom + Module Version : 2.4 + Address width : 3 + Ports : + Inputs : Address[2:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem + EDIF output : suppressed + VHDL output : onewire_spare_one.vhd + VHDL template : onewire_spare_one_tmpl.vhd + VHDL testbench : tb_onewire_spare_one_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : onewire_spare_one.srp + Element Usage : + ROM16X1 : 4 + Estimated Resource Usage: + LUT : 4 diff --git a/cores/onewire_spare_one_generate.log b/cores/onewire_spare_one_generate.log new file mode 100644 index 0000000..ff8c064 --- /dev/null +++ b/cores/onewire_spare_one_generate.log @@ -0,0 +1,47 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Thu Nov 05 15:51:35 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n onewire_spare_one -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type romblk -addr_width 3 -num_words 8 -data_width 4 -outdata UNREGISTERED -memfile \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem -memformat orca -e + Circuit name : onewire_spare_one + Module type : rom + Module Version : 2.4 + Address width : 3 + Data width : 4 + Ports : + Inputs : Address[2:0] + Outputs : Q[3:0] + I/O buffer : not inserted + Memory file : \\home\mboehmer\vhdl_pro\adcmv3\src\spare_onewire_mapping.mem + EDIF output : suppressed + VHDL output : onewire_spare_one.vhd + VHDL template : onewire_spare_one_tmpl.vhd + VHDL testbench : tb_onewire_spare_one_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : onewire_spare_one.srp + Estimated Resource Usage: + LUT : 4 + +END SCUBA Module Synthesis + +File: onewire_spare_one.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/onewire_spare_one_tmpl.vhd b/cores/onewire_spare_one_tmpl.vhd new file mode 100644 index 0000000..94ce4aa --- /dev/null +++ b/cores/onewire_spare_one_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 2.4 +-- Thu Nov 05 15:51:35 2009 + +-- parameterized module component declaration +component onewire_spare_one + port (Address: in std_logic_vector(2 downto 0); + Q: out std_logic_vector(3 downto 0)); +end component; + +-- parameterized module component instance +__ : onewire_spare_one + port map (Address(2 downto 0)=>__, Q(3 downto 0)=>__); diff --git a/cores/ped_thr_true.srp b/cores/ped_thr_true.srp new file mode 100644 index 0000000..e67819a --- /dev/null +++ b/cores/ped_thr_true.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Mon Sep 14 12:54:09 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n ped_thr_true -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ramdp -device LFE2M100E -aaddr_width 7 -widtha 18 -baddr_width 7 -widthb 18 -anum_words 128 -bnum_words 128 -outdataA REGISTERED -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e + Circuit name : ped_thr_true + Module type : RAM_DP_TRUE + Module Version : 7.1 + Ports : + Inputs : DataInA[17:0], DataInB[17:0], AddressA[6:0], AddressB[6:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB + Outputs : QA[17:0], QB[17:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : ped_thr_true.vhd + VHDL template : ped_thr_true_tmpl.vhd + VHDL testbench : tb_ped_thr_true_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : ped_thr_true.srp + Element Usage : + DP16KB : 1 + Estimated Resource Usage: + EBR : 1 diff --git a/cores/ped_thr_true_tmpl.vhd b/cores/ped_thr_true_tmpl.vhd new file mode 100644 index 0000000..53666ec --- /dev/null +++ b/cores/ped_thr_true_tmpl.vhd @@ -0,0 +1,23 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 7.1 +-- Mon Sep 14 12:54:09 2009 + +-- parameterized module component declaration +component ped_thr_true + port (DataInA: in std_logic_vector(17 downto 0); + DataInB: in std_logic_vector(17 downto 0); + AddressA: in std_logic_vector(6 downto 0); + AddressB: in std_logic_vector(6 downto 0); + ClockA: in std_logic; ClockB: in std_logic; + ClockEnA: in std_logic; ClockEnB: in std_logic; + WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic; + ResetB: in std_logic; QA: out std_logic_vector(17 downto 0); + QB: out std_logic_vector(17 downto 0)); +end component; + +-- parameterized module component instance +__ : ped_thr_true + port map (DataInA(17 downto 0)=>__, DataInB(17 downto 0)=>__, + AddressA(6 downto 0)=>__, AddressB(6 downto 0)=>__, ClockA=>__, + ClockB=>__, ClockEnA=>__, ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, + ResetB=>__, QA(17 downto 0)=>__, QB(17 downto 0)=>__); diff --git a/cores/pll_40m_tmpl.vhd b/cores/pll_40m_tmpl.vhd new file mode 100644 index 0000000..786a886 --- /dev/null +++ b/cores/pll_40m_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_PROD_Build (44) +-- Module Version: 4.2 +-- Fri Jan 30 10:01:31 2009 + +-- parameterized module component declaration +component pll_40m + port (CLK: in std_logic; RESET: in std_logic; DPAMODE: in std_logic; + DPHASE0: in std_logic; DPHASE1: in std_logic; DPHASE2: in std_logic; + DPHASE3: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + LOCK: out std_logic); +end component; + +-- parameterized module component instance +__ : pll_40m + port map (CLK=>__, RESET=>__, DPAMODE=>__, DPHASE0=>__, DPHASE1=>__, + DPHASE2=>__, DPHASE3=>__, CLKOP=>__, CLKOS=>__, LOCK=>__); diff --git a/cores/slv_onewire_dpram.srp b/cores/slv_onewire_dpram.srp new file mode 100644 index 0000000..28e8aa5 --- /dev/null +++ b/cores/slv_onewire_dpram.srp @@ -0,0 +1,28 @@ +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Aug 11 14:48:40 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e + Circuit name : slv_onewire_dpram + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[31:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : slv_onewire_dpram.vhd + VHDL template : slv_onewire_dpram_tmpl.vhd + VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : slv_onewire_dpram.srp + Element Usage : + DP16KB : 1 + Estimated Resource Usage: + EBR : 1 diff --git a/cores/slv_onewire_dpram_generate.log b/cores/slv_onewire_dpram_generate.log new file mode 100644 index 0000000..8173499 --- /dev/null +++ b/cores/slv_onewire_dpram_generate.log @@ -0,0 +1,44 @@ +Starting process: + +SCUBA, Version ispLever_v72_SP2_Build (23) +Tue Aug 11 14:48:40 2009 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -n slv_onewire_dpram -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -device LFE2M100E -type ramdps -raddr_width 6 -rwidth 32 -waddr_width 7 -wwidth 16 -rnum_words 64 -wnum_words 128 -resetmode SYNC -cascade -1 -e + Circuit name : slv_onewire_dpram + Module type : RAM_DP + Module Version : 6.1 + Ports : + Inputs : WrAddress[6:0], RdAddress[5:0], Data[15:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn + Outputs : Q[31:0] + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : slv_onewire_dpram.vhd + VHDL template : slv_onewire_dpram_tmpl.vhd + VHDL testbench : tb_slv_onewire_dpram_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : slv_onewire_dpram.srp + Estimated Resource Usage: + EBR : 1 + +END SCUBA Module Synthesis + +File: slv_onewire_dpram.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/slv_onewire_dpram_tmpl.vhd b/cores/slv_onewire_dpram_tmpl.vhd new file mode 100644 index 0000000..7abb4e2 --- /dev/null +++ b/cores/slv_onewire_dpram_tmpl.vhd @@ -0,0 +1,19 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 6.1 +-- Tue Aug 11 14:48:40 2009 + +-- parameterized module component declaration +component slv_onewire_dpram + port (WrAddress: in std_logic_vector(6 downto 0); + RdAddress: in std_logic_vector(5 downto 0); + Data: in std_logic_vector(15 downto 0); WE: in std_logic; + RdClock: in std_logic; RdClockEn: in std_logic; + Reset: in std_logic; WrClock: in std_logic; + WrClockEn: in std_logic; Q: out std_logic_vector(31 downto 0)); +end component; + +-- parameterized module component instance +__ : slv_onewire_dpram + port map (WrAddress(6 downto 0)=>__, RdAddress(5 downto 0)=>__, Data(15 downto 0)=>__, + WE=>__, RdClock=>__, RdClockEn=>__, Reset=>__, WrClock=>__, + WrClockEn=>__, Q(31 downto 0)=>__); diff --git a/cores/sync_pll_40m.srp b/cores/sync_pll_40m.srp new file mode 100644 index 0000000..cbe0804 --- /dev/null +++ b/cores/sync_pll_40m.srp @@ -0,0 +1,26 @@ +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Wed Apr 28 15:46:17 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n sync_pll_40m -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 40 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode INTERNAL -extcap DISABLED -noclkos -noclkok -use_rst -e + Circuit name : sync_pll_40m + Module type : pll + Module Version : 5.1 + Ports : + Inputs : CLK, RESET + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : sync_pll_40m.vhd + VHDL template : sync_pll_40m_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : sync_pll_40m.srp + Element Usage : + EPLLD : 1 + Estimated Resource Usage: diff --git a/cores/sync_pll_40m_generate.log b/cores/sync_pll_40m_generate.log new file mode 100644 index 0000000..478f9dd --- /dev/null +++ b/cores/sync_pll_40m_generate.log @@ -0,0 +1,42 @@ +Starting process: + +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Wed Apr 28 15:46:17 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n sync_pll_40m -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 40 -phase_cntl STATIC -fclkop 40 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode INTERNAL -extcap DISABLED -noclkos -noclkok -use_rst -e + Circuit name : sync_pll_40m + Module type : pll + Module Version : 5.1 + Ports : + Inputs : CLK, RESET + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : sync_pll_40m.vhd + VHDL template : sync_pll_40m_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : sync_pll_40m.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + +File: sync_pll_40m.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/sync_pll_40m_tmpl.vhd b/cores/sync_pll_40m_tmpl.vhd new file mode 100644 index 0000000..6df2007 --- /dev/null +++ b/cores/sync_pll_40m_tmpl.vhd @@ -0,0 +1,13 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v80_SP1_Build +-- Module Version: 5.1 +-- Wed Apr 28 15:46:17 2010 + +-- parameterized module component declaration +component sync_pll_40m + port (CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic; + LOCK: out std_logic); +end component; + +-- parameterized module component instance +__ : sync_pll_40m + port map (CLK=>__, RESET=>__, CLKOP=>__, LOCK=>__); diff --git a/cores/tb_test_fifo2_tmpl.vhd b/cores/tb_test_fifo2_tmpl.vhd new file mode 100644 index 0000000..f6d3943 --- /dev/null +++ b/cores/tb_test_fifo2_tmpl.vhd @@ -0,0 +1,85 @@ +-- VHDL testbench template generated by SCUBA ispLever_v80_SP1_Build +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component test_fifo2 + port (Data : in std_logic_vector(17 downto 0); + Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; Q : out std_logic_vector(17 downto 0); + Empty: out std_logic; Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(17 downto 0) := (others => '0'); + signal Clock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal Q : std_logic_vector(17 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : test_fifo2 + port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn, + Reset => Reset, Q => Q, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + for i in 0 to 1028 loop + wait until Clock'event and Clock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + Clock <= not Clock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 1028 loop + wait until Clock'event and Clock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 1026 loop + wait until Clock'event and Clock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/cores/test_fifo2.jhd b/cores/test_fifo2.jhd new file mode 100644 index 0000000..838a995 --- /dev/null +++ b/cores/test_fifo2.jhd @@ -0,0 +1,171 @@ +MODULE test_fifo2 DEFIN test_fifo2.vhd + SUBMODULE CU2 + INSTANCE r_ctr_5 + SUBMODULE VLO + INSTANCE scuba_vlo_inst + SUBMODULE CU2 + INSTANCE r_ctr_4 + SUBMODULE CU2 + INSTANCE r_ctr_3 + SUBMODULE CU2 + INSTANCE r_ctr_2 + SUBMODULE CU2 + INSTANCE r_ctr_1 + SUBMODULE CU2 + INSTANCE r_ctr_0 + SUBMODULE FADD2B + INSTANCE r_ctr_cia + SUBMODULE VHI + INSTANCE scuba_vhi_inst + SUBMODULE CU2 + INSTANCE w_ctr_5 + SUBMODULE CU2 + INSTANCE w_ctr_4 + SUBMODULE CU2 + INSTANCE w_ctr_3 + SUBMODULE CU2 + INSTANCE w_ctr_2 + SUBMODULE CU2 + INSTANCE w_ctr_1 + SUBMODULE CU2 + INSTANCE w_ctr_0 + SUBMODULE FADD2B + INSTANCE w_ctr_cia + SUBMODULE FADD2B + INSTANCE a1 + SUBMODULE AGEB2 + INSTANCE g_cmp_5 + SUBMODULE AGEB2 + INSTANCE g_cmp_4 + SUBMODULE AGEB2 + INSTANCE g_cmp_3 + SUBMODULE AGEB2 + INSTANCE g_cmp_2 + SUBMODULE AGEB2 + INSTANCE g_cmp_1 + SUBMODULE AGEB2 + INSTANCE g_cmp_0 + SUBMODULE FADD2B + INSTANCE g_cmp_ci_a + SUBMODULE FADD2B + INSTANCE a0 + SUBMODULE ALEB2 + INSTANCE e_cmp_5 + SUBMODULE ALEB2 + INSTANCE e_cmp_4 + SUBMODULE ALEB2 + INSTANCE e_cmp_3 + SUBMODULE ALEB2 + INSTANCE e_cmp_2 + SUBMODULE ALEB2 + INSTANCE e_cmp_1 + SUBMODULE ALEB2 + INSTANCE e_cmp_0 + SUBMODULE FADD2B + INSTANCE e_cmp_ci_a + SUBMODULE CB2 + INSTANCE bdcnt_bctr_5 + SUBMODULE CB2 + INSTANCE bdcnt_bctr_4 + SUBMODULE CB2 + INSTANCE bdcnt_bctr_3 + SUBMODULE CB2 + INSTANCE bdcnt_bctr_2 + SUBMODULE CB2 + INSTANCE bdcnt_bctr_1 + SUBMODULE CB2 + INSTANCE bdcnt_bctr_0 + SUBMODULE FADD2B + INSTANCE bdcnt_bctr_cia + SUBMODULE FD1P3DX + INSTANCE FF_0 + SUBMODULE FD1P3DX + INSTANCE FF_1 + SUBMODULE FD1P3DX + INSTANCE FF_2 + SUBMODULE FD1P3DX + INSTANCE FF_3 + SUBMODULE FD1P3DX + INSTANCE FF_4 + SUBMODULE FD1P3DX + INSTANCE FF_5 + SUBMODULE FD1P3DX + INSTANCE FF_6 + SUBMODULE FD1P3DX + INSTANCE FF_7 + SUBMODULE FD1P3DX + INSTANCE FF_8 + SUBMODULE FD1P3DX + INSTANCE FF_9 + SUBMODULE FD1P3DX + INSTANCE FF_10 + SUBMODULE FD1P3DX + INSTANCE FF_11 + SUBMODULE FD1P3DX + INSTANCE FF_12 + SUBMODULE FD1P3DX + INSTANCE FF_13 + SUBMODULE FD1P3DX + INSTANCE FF_14 + SUBMODULE FD1P3DX + INSTANCE FF_15 + SUBMODULE FD1P3DX + INSTANCE FF_16 + SUBMODULE FD1P3DX + INSTANCE FF_17 + SUBMODULE FD1P3DX + INSTANCE FF_18 + SUBMODULE FD1P3DX + INSTANCE FF_19 + SUBMODULE FD1P3DX + INSTANCE FF_20 + SUBMODULE FD1P3DX + INSTANCE FF_21 + SUBMODULE FD1S3DX + INSTANCE FF_22 + SUBMODULE FD1S3BX + INSTANCE FF_23 + SUBMODULE FD1P3DX + INSTANCE FF_24 + SUBMODULE FD1P3DX + INSTANCE FF_25 + SUBMODULE FD1P3DX + INSTANCE FF_26 + SUBMODULE FD1P3DX + INSTANCE FF_27 + SUBMODULE FD1P3DX + INSTANCE FF_28 + SUBMODULE FD1P3DX + INSTANCE FF_29 + SUBMODULE FD1P3DX + INSTANCE FF_30 + SUBMODULE FD1P3DX + INSTANCE FF_31 + SUBMODULE FD1P3DX + INSTANCE FF_32 + SUBMODULE FD1P3DX + INSTANCE FF_33 + SUBMODULE FD1P3DX + INSTANCE FF_34 + SUBMODULE DP16KB + INSTANCE pdp_ram_0_0_0 + SUBMODULE ROM16X1 + INSTANCE LUT4_0 + SUBMODULE ROM16X1 + INSTANCE LUT4_1 + SUBMODULE INV + INSTANCE INV_0 + SUBMODULE INV + INSTANCE INV_1 + SUBMODULE XOR2 + INSTANCE XOR2_t0 + SUBMODULE AND2 + INSTANCE AND2_t1 + SUBMODULE INV + INSTANCE INV_2 + SUBMODULE AND2 + INSTANCE AND2_t2 + SUBMODULE INV + INSTANCE INV_3 + SUBMODULE AND2 + INSTANCE AND2_t3 diff --git a/cores/test_fifo2.naf b/cores/test_fifo2.naf new file mode 100644 index 0000000..67d97ee --- /dev/null +++ b/cores/test_fifo2.naf @@ -0,0 +1,42 @@ +Data[17] i +Data[16] i +Data[15] i +Data[14] i +Data[13] i +Data[12] i +Data[11] i +Data[10] i +Data[9] i +Data[8] i +Data[7] i +Data[6] i +Data[5] i +Data[4] i +Data[3] i +Data[2] i +Data[1] i +Data[0] i +Clock i +WrEn i +RdEn i +Reset i +Q[17] o +Q[16] o +Q[15] o +Q[14] o +Q[13] o +Q[12] o +Q[11] o +Q[10] o +Q[9] o +Q[8] o +Q[7] o +Q[6] o +Q[5] o +Q[4] o +Q[3] o +Q[2] o +Q[1] o +Q[0] o +Empty o +Full o diff --git a/cores/test_fifo2.srp b/cores/test_fifo2.srp new file mode 100644 index 0000000..c24b7fd --- /dev/null +++ b/cores/test_fifo2.srp @@ -0,0 +1,42 @@ +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Thu May 20 14:41:10 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n test_fifo2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -e + Circuit name : test_fifo2 + Module type : fifoblk + Module Version : 4.8 + Ports : + Inputs : Data[17:0], Clock, WrEn, RdEn, Reset + Outputs : Q[17:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : test_fifo2.vhd + VHDL template : test_fifo2_tmpl.vhd + VHDL testbench : tb_test_fifo2_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : test_fifo2.srp + Element Usage : + AGEB2 : 6 + ALEB2 : 6 + AND2 : 3 + CU2 : 12 + CB2 : 6 + FADD2B : 7 + FD1P3DX : 33 + FD1S3BX : 1 + FD1S3DX : 1 + INV : 4 + ROM16X1 : 2 + XOR2 : 1 + DP16KB : 1 + Estimated Resource Usage: + LUT : 80 + EBR : 1 + Reg : 35 diff --git a/cores/test_fifo2.sym b/cores/test_fifo2.sym new file mode 100644 index 0000000..56e46fd Binary files /dev/null and b/cores/test_fifo2.sym differ diff --git a/cores/test_fifo2_generate.log b/cores/test_fifo2_generate.log new file mode 100644 index 0000000..c80e354 --- /dev/null +++ b/cores/test_fifo2_generate.log @@ -0,0 +1,46 @@ +Starting process: + +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Thu May 20 14:41:10 2010 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n test_fifo2 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -e + Circuit name : test_fifo2 + Module type : fifoblk + Module Version : 4.8 + Ports : + Inputs : Data[17:0], Clock, WrEn, RdEn, Reset + Outputs : Q[17:0], Empty, Full + I/O buffer : not inserted + EDIF output : suppressed + VHDL output : test_fifo2.vhd + VHDL template : test_fifo2_tmpl.vhd + VHDL testbench : tb_test_fifo2_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : big endian + Report output : test_fifo2.srp + Estimated Resource Usage: + LUT : 80 + EBR : 1 + Reg : 35 + +END SCUBA Module Synthesis + +File: test_fifo2.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/cores/test_fifo2_tmpl.vhd b/cores/test_fifo2_tmpl.vhd new file mode 100644 index 0000000..e4e9e51 --- /dev/null +++ b/cores/test_fifo2_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v80_SP1_Build +-- Module Version: 4.8 +-- Thu May 20 14:41:10 2010 + +-- parameterized module component declaration +component test_fifo2 + port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : test_fifo2 + port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(17 downto 0)=>__, Empty=>__, Full=>__); diff --git a/cores/test_fifo_tmpl.vhd b/cores/test_fifo_tmpl.vhd new file mode 100644 index 0000000..aada74f --- /dev/null +++ b/cores/test_fifo_tmpl.vhd @@ -0,0 +1,16 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 4.7 +-- Mon Dec 14 14:54:16 2009 + +-- parameterized module component declaration +component test_fifo + port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + +-- parameterized module component instance +__ : test_fifo + port map (Data(17 downto 0)=>__, Clock=>__, WrEn=>__, RdEn=>__, + Reset=>__, Q(17 downto 0)=>__, Empty=>__, Full=>__); diff --git a/cores/testfifo_tmpl.vhd b/cores/testfifo_tmpl.vhd new file mode 100644 index 0000000..c802148 --- /dev/null +++ b/cores/testfifo_tmpl.vhd @@ -0,0 +1,18 @@ +-- VHDL module instantiation generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +-- Wed Nov 18 17:17:38 2009 + +-- parameterized module component declaration +component testfifo + port (Data: in std_logic_vector(95 downto 0); + WrClock: in std_logic; RdClock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + RPReset: in std_logic; Q: out std_logic_vector(95 downto 0); + Empty: out std_logic; Full: out std_logic); +end component; + +-- parameterized module component instance +__ : testfifo + port map (Data(95 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, + RdEn=>__, Reset=>__, RPReset=>__, Q(95 downto 0)=>__, Empty=>__, + Full=>__); diff --git a/lever/adc_apv_map_mem.jhd b/lever/adc_apv_map_mem.jhd new file mode 100644 index 0000000..8b442ff --- /dev/null +++ b/lever/adc_apv_map_mem.jhd @@ -0,0 +1 @@ +MODULE adc_apv_map_mem diff --git a/lever/adc_ch_in.jhd b/lever/adc_ch_in.jhd new file mode 100644 index 0000000..3e8eb7e --- /dev/null +++ b/lever/adc_ch_in.jhd @@ -0,0 +1 @@ +MODULE adc_ch_in diff --git a/lever/adc_onewire_map_mem.jhd b/lever/adc_onewire_map_mem.jhd new file mode 100644 index 0000000..ffd384b --- /dev/null +++ b/lever/adc_onewire_map_mem.jhd @@ -0,0 +1 @@ +MODULE adc_onewire_map_mem diff --git a/lever/adc_snoop_mem.jhd b/lever/adc_snoop_mem.jhd new file mode 100644 index 0000000..36e1a63 --- /dev/null +++ b/lever/adc_snoop_mem.jhd @@ -0,0 +1 @@ +MODULE adc_snoop_mem diff --git a/lever/adder_16bit.jhd b/lever/adder_16bit.jhd new file mode 100644 index 0000000..9893f44 --- /dev/null +++ b/lever/adder_16bit.jhd @@ -0,0 +1 @@ +MODULE adder_16bit diff --git a/lever/adder_5bit.jhd b/lever/adder_5bit.jhd new file mode 100644 index 0000000..ceebbe6 --- /dev/null +++ b/lever/adder_5bit.jhd @@ -0,0 +1 @@ +MODULE adder_5bit diff --git a/lever/adder_6bit.jhd b/lever/adder_6bit.jhd new file mode 100644 index 0000000..a09957f --- /dev/null +++ b/lever/adder_6bit.jhd @@ -0,0 +1 @@ +MODULE adder_6bit diff --git a/lever/apv_adc_map_mem.jhd b/lever/apv_adc_map_mem.jhd new file mode 100644 index 0000000..1e2590c --- /dev/null +++ b/lever/apv_adc_map_mem.jhd @@ -0,0 +1 @@ +MODULE apv_adc_map_mem diff --git a/lever/automake.log b/lever/automake.log new file mode 100644 index 0000000..8c19b65 --- /dev/null +++ b/lever/automake.log @@ -0,0 +1,12 @@ +ispLEVER Auto-Make Log File +--------------------------- + +Starting: 'X:\Programme\ispTOOLS_80\ispcpld\BIN\checkini.exe -err=automake.err X:\Programme\ispTOOLS_80\ispcpld\config\ep5g00.ini' + +Done: completed successfully. + +Starting: 'X:\Programme\ispTOOLS_80\ispfpga\bin\nt\lci2prf.exe -oc adcmv3.lct adcmv3.lpf' + +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +Done: completed successfully. diff --git a/lever/comp14bit.jhd b/lever/comp14bit.jhd new file mode 100644 index 0000000..4a7c772 --- /dev/null +++ b/lever/comp14bit.jhd @@ -0,0 +1 @@ +MODULE comp14bit diff --git a/lever/comp4bit.jhd b/lever/comp4bit.jhd new file mode 100644 index 0000000..d4d64d6 --- /dev/null +++ b/lever/comp4bit.jhd @@ -0,0 +1 @@ +MODULE comp4bit diff --git a/lever/comp_12bit.jhd b/lever/comp_12bit.jhd new file mode 100644 index 0000000..b14d47e --- /dev/null +++ b/lever/comp_12bit.jhd @@ -0,0 +1 @@ +MODULE comp_12bit diff --git a/lever/crossover.jhd b/lever/crossover.jhd new file mode 100644 index 0000000..c7fa66f --- /dev/null +++ b/lever/crossover.jhd @@ -0,0 +1 @@ +MODULE crossover diff --git a/lever/decoder_8bit.jhd b/lever/decoder_8bit.jhd new file mode 100644 index 0000000..49fb617 --- /dev/null +++ b/lever/decoder_8bit.jhd @@ -0,0 +1 @@ +MODULE decoder_8bit diff --git a/lever/dll_100m.jhd b/lever/dll_100m.jhd new file mode 100644 index 0000000..d11ac41 --- /dev/null +++ b/lever/dll_100m.jhd @@ -0,0 +1 @@ +MODULE dll_100m diff --git a/lever/eds_buffer_dpram.jhd b/lever/eds_buffer_dpram.jhd new file mode 100644 index 0000000..faf58eb --- /dev/null +++ b/lever/eds_buffer_dpram.jhd @@ -0,0 +1 @@ +MODULE eds_buffer_dpram diff --git a/lever/fifo_18x16_media_interface_mb.sym b/lever/fifo_18x16_media_interface_mb.sym new file mode 100644 index 0000000..f8c3e49 Binary files /dev/null and b/lever/fifo_18x16_media_interface_mb.sym differ diff --git a/lever/fifo_1kx18.jhd b/lever/fifo_1kx18.jhd new file mode 100644 index 0000000..79dcb07 --- /dev/null +++ b/lever/fifo_1kx18.jhd @@ -0,0 +1 @@ +MODULE fifo_1kx18 diff --git a/lever/fifo_2kx27.jhd b/lever/fifo_2kx27.jhd new file mode 100644 index 0000000..c2e43eb --- /dev/null +++ b/lever/fifo_2kx27.jhd @@ -0,0 +1 @@ +MODULE fifo_2kx27 diff --git a/lever/frame_status_mem.jhd b/lever/frame_status_mem.jhd new file mode 100644 index 0000000..ef7418b --- /dev/null +++ b/lever/frame_status_mem.jhd @@ -0,0 +1 @@ +MODULE frame_status_mem diff --git a/lever/input_bram.jhd b/lever/input_bram.jhd new file mode 100644 index 0000000..826467b --- /dev/null +++ b/lever/input_bram.jhd @@ -0,0 +1 @@ +MODULE input_bram diff --git a/lever/lattice_ecp2m_fifo_16bit_dualport.jhd b/lever/lattice_ecp2m_fifo_16bit_dualport.jhd new file mode 100644 index 0000000..aee7a44 --- /dev/null +++ b/lever/lattice_ecp2m_fifo_16bit_dualport.jhd @@ -0,0 +1 @@ +MODULE lattice_ecp2m_fifo_16bit_dualport diff --git a/lever/lattice_ecp2m_fifo_18x1k.jhd b/lever/lattice_ecp2m_fifo_18x1k.jhd new file mode 100644 index 0000000..15628a1 --- /dev/null +++ b/lever/lattice_ecp2m_fifo_18x1k.jhd @@ -0,0 +1 @@ +MODULE lattice_ecp2m_fifo_18x1k diff --git a/lever/onewire_spare_one.jhd b/lever/onewire_spare_one.jhd new file mode 100644 index 0000000..f1de495 --- /dev/null +++ b/lever/onewire_spare_one.jhd @@ -0,0 +1 @@ +MODULE onewire_spare_one diff --git a/lever/ped_thr_true.jhd b/lever/ped_thr_true.jhd new file mode 100644 index 0000000..218e158 --- /dev/null +++ b/lever/ped_thr_true.jhd @@ -0,0 +1 @@ +MODULE ped_thr_true diff --git a/lever/pll_40m.jhd b/lever/pll_40m.jhd new file mode 100644 index 0000000..bd6eec8 --- /dev/null +++ b/lever/pll_40m.jhd @@ -0,0 +1 @@ +MODULE pll_40m diff --git a/lever/serdes_gbe_2.jhd b/lever/serdes_gbe_2.jhd new file mode 100644 index 0000000..4e8e2d6 --- /dev/null +++ b/lever/serdes_gbe_2.jhd @@ -0,0 +1 @@ +MODULE serdes_gbe_2 diff --git a/lever/slv_onewire_dpram.jhd b/lever/slv_onewire_dpram.jhd new file mode 100644 index 0000000..ae6b819 --- /dev/null +++ b/lever/slv_onewire_dpram.jhd @@ -0,0 +1 @@ +MODULE slv_onewire_dpram diff --git a/lever/spi_dpram_32_to_8.jhd b/lever/spi_dpram_32_to_8.jhd new file mode 100644 index 0000000..a5c1c35 --- /dev/null +++ b/lever/spi_dpram_32_to_8.jhd @@ -0,0 +1 @@ +MODULE spi_dpram_32_to_8 diff --git a/lever/suber_12bit.jhd b/lever/suber_12bit.jhd new file mode 100644 index 0000000..a22359c --- /dev/null +++ b/lever/suber_12bit.jhd @@ -0,0 +1 @@ +MODULE suber_12bit diff --git a/lever/sync_pll_40m.jhd b/lever/sync_pll_40m.jhd new file mode 100644 index 0000000..db6d2ad --- /dev/null +++ b/lever/sync_pll_40m.jhd @@ -0,0 +1 @@ +MODULE sync_pll_40m diff --git a/lever/syntmp/hdlinfo.log b/lever/syntmp/hdlinfo.log new file mode 100644 index 0000000..caa114c --- /dev/null +++ b/lever/syntmp/hdlinfo.log @@ -0,0 +1,12 @@ +$ Start of Compile +#Fri Jun 18 10:31:03 2010 + +Synopsys VHDL Compiler, version comp350rcp1, Build 105R, built Jul 22 2009 +Copyright (C) 1994-2009, Synopsys Inc. All Rights Reserved + +@N: CD720 :"X:\Programme\ispTOOLS_80\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns +@N:"I:\vhdl_pro\comp_adcmv3\design\sbuf.vhd":21:7:21:10|Top entity is set to sbuf. +Process took 0h:00m:07s realtime, 0h:00m:02s cputime +# Fri Jun 18 10:31:11 2010 + +###########################################################] diff --git a/lever/work/elaboration.log b/lever/work/elaboration.log new file mode 100644 index 0000000..398e2ec --- /dev/null +++ b/lever/work/elaboration.log @@ -0,0 +1,23 @@ +elbread.dll ver. 1.0.5.375 Wed Oct 12 10:43:07 2011 + + +-------------------------------------- +Entity | Architecture | Library +-------------------------------------- +testbench | behavior | work +spi_master | behavioral | work +spi_slim | behavioral | work +------------------------------------ + +------------------------------- +Package | Library +------------------------------- +standard | std +TEXTIO | std +std_logic_1164 | ieee +std_logic_arith | ieee +STD_LOGIC_UNSIGNED | ieee +trb_net_std | work +NUMERIC_STD | ieee +trb_net_components | work +----------------------------- diff --git a/lever/work/log/console.log b/lever/work/log/console.log new file mode 100644 index 0000000..f800f84 --- /dev/null +++ b/lever/work/log/console.log @@ -0,0 +1,219 @@ +adel -all +# Library contents cleared. +vcom ../../trbnet/trb_net_components.vhd +# Compile... +# File: I:\VHDL_Pro\trbnet\trb_net_components.vhd +# Compile Package "trb_net_components" +# Too many errors - compilation terminated +# Error: COMP96_0055: trb_net_components.vhd : (6, 9): Cannot find referenced context element. +# Error: COMP96_0078: trb_net_components.vhd : (19, 39): Unknown identifier "c_NO". +# Error: COMP96_0133: trb_net_components.vhd : (19, 39): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (19, 39): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (19, 39): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (20, 39): Unknown identifier "c_YES". +# Error: COMP96_0133: trb_net_components.vhd : (20, 39): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (20, 39): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (20, 39): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (29, 47): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (29, 47): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (29, 47): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (30, 47): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (30, 47): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (30, 47): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (33, 47): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (33, 47): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (33, 47): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (34, 47): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (34, 47): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (34, 47): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (105, 50): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (105, 50): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (105, 50): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (106, 49): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (106, 49): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (106, 49): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (113, 50): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (113, 50): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (113, 50): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (114, 50): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (114, 50): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (114, 50): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (132, 51): Unknown identifier "c_API_PASSIVE". +# Error: COMP96_0133: trb_net_components.vhd : (132, 51): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (132, 51): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (132, 51): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (135, 51): Unknown identifier "std_FORCE_REPLY". +# Error: COMP96_0133: trb_net_components.vhd : (135, 51): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (135, 51): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (135, 51): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (136, 51): Unknown identifier "std_SBUF_VERSION". +# Error: COMP96_0133: trb_net_components.vhd : (136, 51): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (136, 51): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (136, 51): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (137, 51): Unknown identifier "c_YES". +# Error: COMP96_0133: trb_net_components.vhd : (137, 51): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (137, 51): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (137, 51): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (138, 51): Unknown identifier "c_YES". +# Error: COMP96_0133: trb_net_components.vhd : (138, 51): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (138, 51): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (138, 51): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (139, 51): Unknown identifier "c_YES". +# Error: COMP96_0133: trb_net_components.vhd : (139, 51): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (139, 51): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (139, 51): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (140, 51): Unknown identifier "c_NO". +# Error: COMP96_0133: trb_net_components.vhd : (140, 51): Cannot find object declaration. +# Error: COMP96_0104: trb_net_components.vhd : (140, 51): Undefined type of expression. +# Error: COMP96_0077: trb_net_components.vhd : (140, 51): Assignment target incompatible with right side. Expected type 'INTEGER'. +# Error: COMP96_0078: trb_net_components.vhd : (153, 53): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (153, 53): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (153, 53): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (154, 53): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (154, 53): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (154, 53): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (163, 53): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (163, 53): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (163, 53): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (164, 53): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (164, 53): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (164, 53): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (180, 57): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (180, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (180, 57): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (181, 57): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (181, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (181, 57): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (184, 57): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (184, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (184, 57): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (185, 57): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (185, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (185, 57): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (188, 57): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (188, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (188, 57): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (189, 57): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (189, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (189, 57): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (192, 57): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (192, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (192, 57): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (193, 57): Unknown identifier "c_NUM_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (193, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (193, 57): Locally static expression is required in the range definition. +# Error: COMP96_0078: trb_net_components.vhd : (213, 57): Unknown identifier "c_DATA_WIDTH". +# Error: COMP96_0133: trb_net_components.vhd : (213, 57): Cannot find object declaration. +# Error: COMP96_0094: trb_net_components.vhd : (213, 57): Locally static expression is required in the range definition. +# Compile failure 100 Errors 0 Warnings Analysis time : 0.5 [s] +vcom ../version.vhd +# Compile... +# File: I:\VHDL_Pro\comp_adcmv3\version.vhd +# Compile Package "version" +# Compile success 0 Errors 0 Warnings Analysis time : 63.0 [ms] +vcom ../design/adcmv3_components.vhd +# Compile... +# File: I:\VHDL_Pro\comp_adcmv3\design\adcmv3_components.vhd +# Compile Package "adcmv3_components" +# Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s] +vcom ../../trbnet/trb_net_std.vhd +# Compile... +# File: I:\VHDL_Pro\trbnet\trb_net_std.vhd +# Compile Package "trb_net_std" +# Compile Package Body "trb_net_std" +# Compile success 0 Errors 0 Warnings Analysis time : 0.3 [s] +vcom ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd +# Compile... +# File: I:\VHDL_Pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo.vhd +# Compile Package "lattice_ecp2m_fifo" +# Compile success 0 Errors 0 Warnings Analysis time : 93.0 [ms] +vcom ../../trbnet/trb_net_components.vhd +# Compile... +# File: I:\VHDL_Pro\trbnet\trb_net_components.vhd +# Compile Package "trb_net_components" +# Compile success 0 Errors 0 Warnings Analysis time : 0.4 [s] +vcom ../version.vhd +# Compile... +# File: I:\VHDL_Pro\comp_adcmv3\version.vhd +# Compile Package "version" +# Compile success 0 Errors 0 Warnings Analysis time : 78.0 [ms] +vcom ../design/adcmv3_components.vhd +# Compile... +# File: I:\VHDL_Pro\comp_adcmv3\design\adcmv3_components.vhd +# Compile Package "adcmv3_components" +# Compile success 0 Errors 0 Warnings Analysis time : 0.3 [s] +vcom ../../trbnet/trb_net_std.vhd +# Compile... +# File: I:\VHDL_Pro\trbnet\trb_net_std.vhd +# Compile Package "trb_net_std" +# Compile Package Body "trb_net_std" +# Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s] +vcom ../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd +# Compile... +# File: I:\VHDL_Pro\trbnet\lattice\ecp2m\lattice_ecp2m_fifo.vhd +# Compile Package "lattice_ecp2m_fifo" +# Compile success 0 Errors 0 Warnings Analysis time : 78.0 [ms] +vcom ../../trbnet/special/spi_slim.vhd +# Compile... +# File: I:\VHDL_Pro\trbnet\special\spi_slim.vhd +# Compile Entity "spi_slim" +# Warning: COMP96_0119: spi_slim.vhd : (14, 30): The range is 'null range'. +# Compile Architecture "Behavioral" of Entity "spi_slim" +# Compile success 0 Errors 1 Warnings Analysis time : 0.5 [s] +vcom ../../trbnet/special/spi_master.vhd +# Compile... +# File: I:\VHDL_Pro\trbnet\special\spi_master.vhd +# Compile Entity "spi_master" +# Compile Architecture "Behavioral" of Entity "spi_master" +# Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s] +vcom ../sim/tb_spi_master.vhd +# Compile... +# File: I:\VHDL_Pro\comp_adcmv3\sim\tb_spi_master.vhd +# Compile Entity "testbench" +# Compile Architecture "behavior" of Entity "testbench" +# Compile success 0 Errors 0 Warnings Analysis time : 0.2 [s] +vsim testbench -PL pmi_work -L ovi_ecp2m -L pcsc_work +# ELBREAD: Elaboration process. +# ELBREAD: Elaboration time 0.1 [s]. +# vsim: Stack memory: 32MB +# vsim: Retval memory: 32MB +# KERNEL: Main thread initiated. +# KERNEL: Kernel process initialization phase. +# KERNEL: Time resolution set to 1ps. +# ELAB2: Elaboration final pass... +# ELAB2: Create instances ... +# ELAB2: Create instances complete. +# ELAB2: You do not have a license to run VHDL performance optimized simulation. Contact Aldec for ordering information - sales@aldec.com. +# ELAB2: Elaboration final pass complete - time: 0.1 [s]. +# KERNEL: Warning: You are using the Active-HDL Lattice Edition. The performance of simulation is running at a reduced rate. +# KERNEL: Warning: Contact Aldec for available upgrade options - sales@aldec.com. +# KERNEL: Kernel process initialization done. +# Allocation: Simulator allocated 2547 kB (elbread=1023 elab2=1167 kernel=356 sdf=0) +# 10:43, Mittwoch, 12. Oktober 2011 +# Simulation has been initialized +# Selected Top-Level: testbench (behavior) +do tb_spi_master_vhdf.udo testbench +add wave * +run 1000 ns +# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# KERNEL: Time: 0 ps, Iteration: 0, Instance: /uut/THE_SPI_SLIM, Process: line__192. +# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# KERNEL: Time: 0 ps, Iteration: 0, Instance: /uut/THE_SPI_SLIM, Process: line__192. +# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# KERNEL: Time: 0 ps, Iteration: 0, Instance: /uut/THE_SPI_SLIM, Process: line__549. +# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# KERNEL: Time: 0 ps, Iteration: 0, Instance: /uut/THE_SPI_SLIM, Process: line__614. +# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# KERNEL: Time: 10 ns, Iteration: 1, Instance: /uut/THE_SPI_SLIM, Process: THE_CLOCK_DIVIDER. +# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# KERNEL: Time: 10 ns, Iteration: 2, Instance: /uut/THE_SPI_SLIM, Process: line__192. +# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# KERNEL: Time: 10 ns, Iteration: 2, Instance: /uut/THE_SPI_SLIM, Process: line__192. +# KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +# KERNEL: Time: 20 ns, Iteration: 1, Instance: /uut/THE_SPI_SLIM, Process: THE_CLOCK_DIVIDER. +# KERNEL: stopped at time: 1 us +run 10us +# KERNEL: stopped at time: 11 us +run 10us +# KERNEL: stopped at time: 21 us +# Simulation has been stopped diff --git a/nodelist.txt b/nodelist.txt new file mode 100755 index 0000000..0c760d8 --- /dev/null +++ b/nodelist.txt @@ -0,0 +1,50 @@ +[pbs1] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs2] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs3] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs4] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs5] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs6] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs7] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs8] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs9] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[pbs10] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ diff --git a/sim/tb_adc_apv_map_mem_tmpl.vhd b/sim/tb_adc_apv_map_mem_tmpl.vhd new file mode 100644 index 0000000..73cba33 --- /dev/null +++ b/sim/tb_adc_apv_map_mem_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component adc_apv_map_mem + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : adc_apv_map_mem + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/sim/tb_adc_onewire_map_mem_tmpl.vhd b/sim/tb_adc_onewire_map_mem_tmpl.vhd new file mode 100644 index 0000000..c38f34b --- /dev/null +++ b/sim/tb_adc_onewire_map_mem_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component adc_onewire_map_mem + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : adc_onewire_map_mem + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/sim/tb_apv_adc_map_mem_tmpl.vhd b/sim/tb_apv_adc_map_mem_tmpl.vhd new file mode 100644 index 0000000..d66043c --- /dev/null +++ b/sim/tb_apv_adc_map_mem_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component apv_adc_map_mem + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : apv_adc_map_mem + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/sim/tb_apv_map_mem_tmpl.vhd b/sim/tb_apv_map_mem_tmpl.vhd new file mode 100644 index 0000000..9e06c81 --- /dev/null +++ b/sim/tb_apv_map_mem_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component apv_map_mem + port (Address : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(6 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : apv_map_mem + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 131 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/sim/tb_comp4bit_tmpl.vhd b/sim/tb_comp4bit_tmpl.vhd new file mode 100644 index 0000000..69fe6ee --- /dev/null +++ b/sim/tb_comp4bit_tmpl.vhd @@ -0,0 +1,48 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component comp4bit + port (DataA : in std_logic_vector(3 downto 0); + DataB : in std_logic_vector(3 downto 0); AGTB: out std_logic + ); + end component; + + signal DataA : std_logic_vector(3 downto 0) := (others => '0'); + signal DataB : std_logic_vector(3 downto 0) := (others => '0'); + signal AGTB: std_logic; +begin + u1 : comp4bit + port map (DataA => DataA, DataB => DataB, AGTB => AGTB + ); + + process + + begin + DataA <= (others => '0') ; + for i in 0 to 200 loop + wait for 10 ns; + DataA <= DataA + '1' ; + end loop; + wait; + end process; + + process + + begin + DataB <= (others => '0') ; + for i in 0 to 100 loop + wait for 10 ns; + DataB <= DataB + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/sim/tb_crossfifo_tmpl.vhd b/sim/tb_crossfifo_tmpl.vhd new file mode 100644 index 0000000..405d101 --- /dev/null +++ b/sim/tb_crossfifo_tmpl.vhd @@ -0,0 +1,103 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component crossfifo + port (Data : in std_logic_vector(95 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(95 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostEmpty: out std_logic + ); + end component; + + signal Data : std_logic_vector(95 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(95 downto 0); + signal Empty: std_logic; + signal Full: std_logic; + signal AlmostEmpty: std_logic; +begin + u1 : crossfifo + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 259 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 259 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 259 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/sim/tb_crossover_tmpl.vhd b/sim/tb_crossover_tmpl.vhd new file mode 100644 index 0000000..ca6cbbf --- /dev/null +++ b/sim/tb_crossover_tmpl.vhd @@ -0,0 +1,106 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component crossover + port (Data : in std_logic_vector(95 downto 0); + WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; + RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; + Q : out std_logic_vector(95 downto 0); + WCNT : out std_logic_vector(4 downto 0); + RCNT : out std_logic_vector(4 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(95 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal RdClock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal RPReset: std_logic := '0'; + signal Q : std_logic_vector(95 downto 0); + signal WCNT : std_logic_vector(4 downto 0); + signal RCNT : std_logic_vector(4 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : crossover + port map (Data => Data, WrClock => WrClock, RdClock => RdClock, + WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, + Q => Q, WCNT => WCNT, RCNT => RCNT, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 19 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + RdClock <= not RdClock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 19 loop + wait until WrClock'event and WrClock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 19 loop + wait until RdClock'event and RdClock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + RPReset <= '1' ; + wait for 100 ns; + RPReset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/sim/tb_dpram_8x19_tmpl.vhd b/sim/tb_dpram_8x19_tmpl.vhd new file mode 100644 index 0000000..08ccad6 --- /dev/null +++ b/sim/tb_dpram_8x19_tmpl.vhd @@ -0,0 +1,98 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_PROD_Build (44) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component dpram_8x19 + port (WrAddress : in std_logic_vector(3 downto 0); + Data : in std_logic_vector(18 downto 0); WrClock: in std_logic; + WE: in std_logic; WrClockEn: in std_logic; + RdAddress : in std_logic_vector(3 downto 0); + Q : out std_logic_vector(18 downto 0) + ); + end component; + + signal WrAddress : std_logic_vector(3 downto 0) := (others => '0'); + signal Data : std_logic_vector(18 downto 0) := (others => '0'); + signal WrClock: std_logic := '0'; + signal WE: std_logic := '0'; + signal WrClockEn: std_logic := '0'; + signal RdAddress : std_logic_vector(3 downto 0) := (others => '0'); + signal Q : std_logic_vector(18 downto 0); +begin + u1 : dpram_8x19 + port map (WrAddress => WrAddress, Data => Data, WrClock => WrClock, + WE => WE, WrClockEn => WrClockEn, RdAddress => RdAddress, Q => Q + ); + + process + + begin + WrAddress <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 38 loop + wait until WrClock'event and WrClock = '1'; + WrAddress <= WrAddress + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + Data <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 19 loop + wait until WrClock'event and WrClock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + WrClock <= not WrClock after 5.00 ns; + + process + + begin + WE <= '0' ; + wait for 10 ns; + for i in 0 to 19 loop + wait until WrClock'event and WrClock = '1'; + WE <= '1' after 1 ns; + end loop; + WE <= '0' ; + wait; + end process; + + process + + begin + WrClockEn <= '0' ; + wait for 100 ns; + wait for 10 ns; + WrClockEn <= '1' ; + wait; + end process; + + process + + begin + RdAddress <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 38 loop + wait for 10 ns; + RdAddress <= RdAddress + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/sim/tb_fifo_16x11_tmpl.vhd b/sim/tb_fifo_16x11_tmpl.vhd new file mode 100644 index 0000000..b62c08a --- /dev/null +++ b/sim/tb_fifo_16x11_tmpl.vhd @@ -0,0 +1,87 @@ +-- VHDL testbench template generated by SCUBA ispLever_v8.0_PROD_Build (41) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_16x11 + port (Data : in std_logic_vector(10 downto 0); + Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; Q : out std_logic_vector(10 downto 0); + WCNT : out std_logic_vector(4 downto 0); Empty: out std_logic; + Full: out std_logic + ); + end component; + + signal Data : std_logic_vector(10 downto 0) := (others => '0'); + signal Clock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal Q : std_logic_vector(10 downto 0); + signal WCNT : std_logic_vector(4 downto 0); + signal Empty: std_logic; + signal Full: std_logic; +begin + u1 : fifo_16x11 + port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn, + Reset => Reset, Q => Q, WCNT => WCNT, Empty => Empty, Full => Full + ); + + process + + begin + Data <= (others => '0') ; + for i in 0 to 20 loop + wait until Clock'event and Clock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + Clock <= not Clock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 20 loop + wait until Clock'event and Clock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 18 loop + wait until Clock'event and Clock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/sim/tb_fifo_1kx18_tmpl.vhd b/sim/tb_fifo_1kx18_tmpl.vhd new file mode 100644 index 0000000..e204e95 --- /dev/null +++ b/sim/tb_fifo_1kx18_tmpl.vhd @@ -0,0 +1,89 @@ +-- VHDL testbench template generated by SCUBA ispLever_v80_SP1_Build +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component fifo_1kx18 + port (Data : in std_logic_vector(17 downto 0); + Clock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; + Reset: in std_logic; Q : out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(10 downto 0); Empty: out std_logic; + Full: out std_logic; AlmostFull: out std_logic + ); + end component; + + signal Data : std_logic_vector(17 downto 0) := (others => '0'); + signal Clock: std_logic := '0'; + signal WrEn: std_logic := '0'; + signal RdEn: std_logic := '0'; + signal Reset: std_logic := '0'; + signal Q : std_logic_vector(17 downto 0); + signal WCNT : std_logic_vector(10 downto 0); + signal Empty: std_logic; + signal Full: std_logic; + signal AlmostFull: std_logic; +begin + u1 : fifo_1kx18 + port map (Data => Data, Clock => Clock, WrEn => WrEn, RdEn => RdEn, + Reset => Reset, Q => Q, WCNT => WCNT, Empty => Empty, Full => Full, + AlmostFull => AlmostFull + ); + + process + + begin + Data <= (others => '0') ; + for i in 0 to 1028 loop + wait until Clock'event and Clock = '1'; + Data <= Data + '1' after 1 ns; + end loop; + wait; + end process; + + Clock <= not Clock after 5.00 ns; + + process + + begin + WrEn <= '0' ; + wait for 100 ns; + wait until Reset = '0'; + for i in 0 to 1028 loop + wait until Clock'event and Clock = '1'; + WrEn <= '1' after 1 ns; + end loop; + WrEn <= '0' ; + wait; + end process; + + process + + begin + RdEn <= '0' ; + wait until Reset = '0'; + wait until WrEn = '1'; + wait until WrEn = '0'; + for i in 0 to 1026 loop + wait until Clock'event and Clock = '1'; + RdEn <= '1' after 1 ns; + end loop; + RdEn <= '0' ; + wait; + end process; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + +end architecture test; diff --git a/sim/tb_mult_3x8_tmpl.vhd b/sim/tb_mult_3x8_tmpl.vhd new file mode 100644 index 0000000..4e92e9b --- /dev/null +++ b/sim/tb_mult_3x8_tmpl.vhd @@ -0,0 +1,72 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component mult_3x8 + port (Clock: in std_logic; ClkEn: in std_logic; + Aclr: in std_logic; DataA : in std_logic_vector(2 downto 0); + DataB : in std_logic_vector(7 downto 0); + Result : out std_logic_vector(10 downto 0) + ); + end component; + + signal Clock: std_logic := '0'; + signal ClkEn: std_logic := '0'; + signal Aclr: std_logic := '0'; + signal DataA : std_logic_vector(2 downto 0) := (others => '0'); + signal DataB : std_logic_vector(7 downto 0) := (others => '0'); + signal Result : std_logic_vector(10 downto 0); +begin + u1 : mult_3x8 + port map (Clock => Clock, ClkEn => ClkEn, Aclr => Aclr, DataA => DataA, + DataB => DataB, Result => Result + ); + + Clock <= not Clock after 5.00 ns; + + process + + begin + ClkEn <= '1' ; + wait; + end process; + + process + + begin + Aclr <= '1' ; + wait for 100 ns; + Aclr <= '0' ; + wait; + end process; + + process + + begin + DataA <= (others => '0') ; + for i in 0 to 200 loop + wait until Clock'event and Clock = '1'; + DataA <= DataA + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + DataB <= (others => '0') ; + for i in 0 to 200 loop + wait until Clock'event and Clock = '1'; + DataB <= DataB + '1' after 1 ns; + end loop; + wait; + end process; + +end architecture test; diff --git a/sim/tb_onewire_spare_one_tmpl.vhd b/sim/tb_onewire_spare_one_tmpl.vhd new file mode 100644 index 0000000..8a91575 --- /dev/null +++ b/sim/tb_onewire_spare_one_tmpl.vhd @@ -0,0 +1,38 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component onewire_spare_one + port (Address : in std_logic_vector(2 downto 0); + Q : out std_logic_vector(3 downto 0) + ); + end component; + + signal Address : std_logic_vector(2 downto 0) := (others => '0'); + signal Q : std_logic_vector(3 downto 0); +begin + u1 : onewire_spare_one + port map (Address => Address, Q => Q + ); + + process + + begin + Address <= (others => '0') ; + wait for 100 ns; + wait for 10 ns; + for i in 0 to 11 loop + wait for 10 ns; + Address <= Address + '1' ; + end loop; + wait; + end process; + +end architecture test; diff --git a/sim/tb_suber_12bit_tmpl.vhd b/sim/tb_suber_12bit_tmpl.vhd new file mode 100644 index 0000000..f4afdf6 --- /dev/null +++ b/sim/tb_suber_12bit_tmpl.vhd @@ -0,0 +1,72 @@ +-- VHDL testbench template generated by SCUBA ispLever_v72_SP2_Build (23) +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity tb is +end entity tb; + + +architecture test of tb is + + component suber_12bit + port (DataA : in std_logic_vector(11 downto 0); + DataB : in std_logic_vector(11 downto 0); Clock: in std_logic; + Reset: in std_logic; ClockEn: in std_logic; + Result : out std_logic_vector(11 downto 0) + ); + end component; + + signal DataA : std_logic_vector(11 downto 0) := (others => '0'); + signal DataB : std_logic_vector(11 downto 0) := (others => '0'); + signal Clock: std_logic := '0'; + signal Reset: std_logic := '0'; + signal ClockEn: std_logic := '0'; + signal Result : std_logic_vector(11 downto 0); +begin + u1 : suber_12bit + port map (DataA => DataA, DataB => DataB, Clock => Clock, Reset => Reset, + ClockEn => ClockEn, Result => Result + ); + + process + + begin + DataA <= (others => '0') ; + for i in 0 to 200 loop + wait until Clock'event and Clock = '1'; + DataA <= DataA + '1' after 1 ns; + end loop; + wait; + end process; + + process + + begin + DataB <= (others => '0') ; + for i in 0 to 200 loop + wait until Clock'event and Clock = '1'; + DataB <= DataB + '1' after 1 ns; + end loop; + wait; + end process; + + Clock <= not Clock after 5.00 ns; + + process + + begin + Reset <= '1' ; + wait for 100 ns; + Reset <= '0' ; + wait; + end process; + + process + + begin + ClockEn <= '1' ; + wait; + end process; + +end architecture test; diff --git a/source/adcmv3_components2.vhd b/source/adcmv3_components2.vhd new file mode 100644 index 0000000..6496d1e --- /dev/null +++ b/source/adcmv3_components2.vhd @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package adcmv3_componets is + + type debug_array_t is array(integer range <>) of + std_logic_vector(15 downto 0); + + component debug_multiplexer + generic ( + NUM_PORTS : integer range 1 to 32); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1); + DEBUG_LINE_OUT : out std_logic_vector(15 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component; + +end package; diff --git a/source/debug_multiplexer.vhd b/source/debug_multiplexer.vhd new file mode 100644 index 0000000..7b70f58 --- /dev/null +++ b/source/debug_multiplexer.vhd @@ -0,0 +1,118 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.adcmv3_componets.all; + +entity debug_multiplexer is + generic ( + NUM_PORTS : integer range 1 to 32 := 1 + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1); + DEBUG_LINE_OUT : out std_logic_vector(15 downto 0); + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + + ); +end entity; + +architecture Behavioral of debug_multiplexer is + + signal port_select : std_logic_vector(7 downto 0); + signal debug_line_o : std_logic_vector(15 downto 0); + + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + +begin + + PROC_MULTIPLEXER: process(port_select, + DEBUG_LINE_IN) + begin + if (unsigned(port_select) < NUM_PORTS) then + debug_line_o <= + DEBUG_LINE_IN(to_integer(unsigned(port_select))); + elsif (unsigned(port_select) = NUM_PORTS) then + -- Checkerboard + for I in 0 to 7 loop + debug_line_o(I * 2) <= CLK_IN; + debug_line_o(I * 2 + 1) <= not CLK_IN; + end loop; + else + debug_line_o <= (others => '1'); + end if; + end process PROC_MULTIPLEXER; + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + port_select <= (others => '0'); + else + slv_ack_o <= '1'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + + if (SLV_WRITE_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + if (unsigned(SLV_DATA_IN(7 downto 0)) < NUM_PORTS + 1) then + port_select <= SLV_DATA_IN(7 downto 0); + end if; + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + elsif (SLV_READ_IN = '1') then + case SLV_ADDR_IN is + when x"0000" => + slv_data_out_o(7 downto 0) <= port_select; + slv_data_out_o(31 downto 8) <= (others => '0'); + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_SLAVE_BUS; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + + DEBUG_LINE_OUT <= debug_line_o; + +end Behavioral; diff --git a/source/rich_trb.vhd b/source/rich_trb.vhd index 8ebd24a..8dc794e 100644 --- a/source/rich_trb.vhd +++ b/source/rich_trb.vhd @@ -208,7 +208,7 @@ generic map( REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", REGIO_INIT_ENDPOINT_ID => x"0001", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), - REGIO_COMPILE_VERSION => x"0003", + -- REGIO_COMPILE_VERSION => x"0003", REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature REGIO_USE_1WIRE_INTERFACE => c_YES, TIMING_TRIGGER_RAW => c_YES, diff --git a/stdout.log b/stdout.log new file mode 100644 index 0000000..c1dbcdf --- /dev/null +++ b/stdout.log @@ -0,0 +1,77 @@ +line 5789, col 42: Option set not found: vcs_ECP4_lib. +line 5803, col 44: Option set not found: vcs_ECP45M_lib. + + +Running in Lattice mode + + +Starting: /usr/local/opt/lattice_diamond/diamond/3.2/synpbase/linux_a_64/mbin/synbatch +Install: /usr/local/opt/lattice_diamond/diamond/3.2/synpbase +Date: Tue Feb 10 22:13:23 2015 +Version: I-2013.09L-SP1-1 + +Arguments: -product synplify_pro -batch adcmv3.prj +ProductType: synplify_pro + + + + + + +log file: "/home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srr" + + + + + +Running adcmv3|workdir + + +Running: Compile on adcmv3|workdir + + +Running: Compile Process on adcmv3|workdir + + +Running: Compile Input on adcmv3|workdir + +Copied /home/rich/TRB/nXyter/trb3/adcm/workdir/synwork/adcmv3_comp.srs to /home/rich/TRB/nXyter/trb3/adcm/workdir/adcmv3.srs + +compiler Completed +Return Code: 0 +Run Time:00h:00m:28s + + +Complete: Compile Process on adcmv3|workdir + + +Running: Pre-mapping on adcmv3|workdir + +premap Completed with warnings +Return Code: 1 +Run Time:00h:00m:06s + + +Complete: Compile on adcmv3|workdir + + +Running: Map on adcmv3|workdir + + +Running: Map & Optimize on adcmv3|workdir + +fpga_mapper Completed with warnings +Return Code: 1 +Run Time:00h:03m:16s + + +Complete: Map on adcmv3|workdir + +Complete: Logic Synthesis on adcmv3|workdir + +exit status=0 + + +exit status=0 + + diff --git a/version-major-minor.txt b/version-major-minor.txt new file mode 100644 index 0000000..cde5dce --- /dev/null +++ b/version-major-minor.txt @@ -0,0 +1 @@ +0400 diff --git a/version.vhd- b/version.vhd- new file mode 100644 index 0000000..8ae9c99 --- /dev/null +++ b/version.vhd- @@ -0,0 +1,13 @@ +-- attention, automatically generated. Don't change by hand. +library ieee; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +use ieee.numeric_std.all; + +package version is + + constant VERSION_NUMBER_TIME : integer := 1423599792; + constant VERSION_NUMBER : integer := to_integer(x""); + +end package version; diff --git a/workdir/.recordref b/workdir/.recordref new file mode 100644 index 0000000..e69de29 diff --git a/workdir/.recordref_modgen b/workdir/.recordref_modgen new file mode 100644 index 0000000..e69de29