From: Peter Lemmens <p.j.j.lemmens@rug.nl>
Date: Thu, 16 Jan 2014 14:20:53 +0000 (+0100)
Subject: Stable (or at least it really looks that way) but not quite synchronous
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8179083e5c9527171ba5f73a1db25b9d14f9355b;p=soda.git

Stable (or at least it really looks that way) but not quite synchronous
All crashes (3 sofar) of trbnet have been solved with 'trbcmd reset'.

Changes to soda:
- The source now has a tx-fifo (fixed delay) but NO rx-fifo.
- Both sides have a watchdog implemented. It checks 'got_link_ready'. If this is absent the watchdog fires and resets the rx-control fsm.
- Calibration works with: 'trbcmd w 0xf355 0xbe00 0x40000000;trbcmd w 0xf355 0xbe00 0x00000000; trbcmd r 0xf355 0xbe02'
- The client still has an rx-fifo ; this will be next to go.
---

diff --git a/soda_client.ldf b/soda_client.ldf
index 4e37427..c711e8d 100644
--- a/soda_client.ldf
+++ b/soda_client.ldf
@@ -4,7 +4,7 @@
         <Option name="HDL type" value="VHDL"/>
     </Options>
     <Implementation title="soda_client" dir="soda_client" description="soda_client" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
+        <Options top="trb3_periph_sodaclient"/>
         <Source name="source/version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -320,7 +320,7 @@
         <Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
             <Options/>
         </Source>
-        <Source name="source/soda_source_syn_translated.fdc" type="Synplify Design Constraints File" type_short="SDC">
+        <Source name="source/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
             <Options/>
         </Source>
         <Source name="trb3_soda_client.xcf" type="Programming Project File" type_short="Programming">
diff --git a/soda_client.lpf b/soda_client.lpf
index 6be6dfb..3f53e01 100644
--- a/soda_client.lpf
+++ b/soda_client.lpf
@@ -1,4 +1,4 @@
-rvl_alias "clk_raw_internal" "clk_raw_internal";
+rvl_alias "reveal_ist_380" "the_sync_link/clk_rx_full";
 RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0"; 
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
diff --git a/soda_source.lpf b/soda_source.lpf
index bb301ca..3667e7a 100644
--- a/soda_source.lpf
+++ b/soda_source.lpf
@@ -1,4 +1,4 @@
-rvl_alias "clk_raw_internal" "clk_raw_internal";
+rvl_alias "rx_clock_full" "rx_clock_full";
 RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
diff --git a/source/med_ecp3_sfp_sync_down.vhd b/source/med_ecp3_sfp_sync_down.vhd
index 7c60bff..e9266fb 100644
--- a/source/med_ecp3_sfp_sync_down.vhd
+++ b/source/med_ecp3_sfp_sync_down.vhd
@@ -171,6 +171,8 @@ type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GE
 signal sci_state         : sci_ctrl;
 signal sci_timer         : unsigned(12 downto 0) := (others => '0');
 signal start_timer       : unsigned(18 downto 0) := (others => '0');
+signal watchdog_timer	: unsigned(20 downto 0) := (others => '0');
+signal watchdog_trigger	: std_logic :='0';
 
 begin
 
@@ -186,9 +188,9 @@ CLK_TX_FULL_OUT	<= clk_tx_full;
 SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
 
 
---rst_n <= not CLEAR;	PL!
-rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
-rst   <=     (CLEAR or sd_los_i or internal_make_link_reset_out);
+--rst_n <= not CLEAR;	PL!
+rst_n					<= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+rst					<=		(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
 
 
 gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
@@ -211,7 +213,7 @@ THE_SERDES : entity work.serdes_sync_downstream
     hdinn_ch0            => SD_RXD_N_IN,
     hdoutp_ch0           => SD_TXD_P_OUT,
     hdoutn_ch0           => SD_TXD_N_OUT,
-    rxiclk_ch0           => clk_200_i,
+--    rxiclk_ch0           => clk_200_i,		-- read fifo is no longer present! PL!
     txiclk_ch0           => clk_200_i,
     rx_full_clk_ch0      => clk_rx_full,
     rx_half_clk_ch0      => clk_rx_half,
@@ -305,18 +307,40 @@ rx_allow_q <= rx_allow when rising_edge(SYSCLK);
 tx_allow_q <= tx_allow when rising_edge(SYSCLK);
 
 
-PROC_START_TIMER : process begin
-  wait until rising_edge(clk_200_i);
-  if got_link_ready_i = '1' then
-    if start_timer(start_timer'left) = '0' then
-      start_timer <= start_timer + 1;
-    end if;  
-  else
-    start_timer <= (others => '0');
-  end if;
-end process;
-    
+--PROC_START_TIMER : process begin
+  --wait until rising_edge(clk_200_i);
+  --if got_link_ready_i = '1' then
+    --if start_timer(start_timer'left) = '0' then
+      --start_timer <= start_timer + 1;
+    --end if;  
+  --else
+    --start_timer <= (others => '0');
+  --end if;
+--end process;
     
+PROC_START_TIMER : process(clk_200_i)
+begin
+	if rising_edge(clk_200_i) then
+		if got_link_ready_i = '1' then
+			watchdog_timer	<= (others => '0');
+			if start_timer(start_timer'left) = '0' then
+				start_timer <= start_timer + 1;
+			end if;  
+		else
+			start_timer <= (others => '0');
+			if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 1) = '1')) then
+				watchdog_trigger	<= '1';
+			else 
+				watchdog_trigger	<= '0';
+			end if;
+			if watchdog_trigger = '0' then
+				watchdog_timer	<= watchdog_timer + 1;
+			else 
+				watchdog_timer	<= (others => '0');
+			end if;
+		end if;
+	end if;
+end process;
 -------------------------------------------------      
 -- TX Data
 -------------------------------------------------         
diff --git a/source/med_ecp3_sfp_sync_up.vhd b/source/med_ecp3_sfp_sync_up.vhd
index 80c333e..7cebc5f 100644
--- a/source/med_ecp3_sfp_sync_up.vhd
+++ b/source/med_ecp3_sfp_sync_up.vhd
@@ -185,6 +185,8 @@ type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GE
 signal sci_state         : sci_ctrl;
 signal sci_timer         : unsigned(12 downto 0) := (others => '0');
 signal start_timer       : unsigned(18 downto 0) := (others => '0');
+signal watchdog_timer	: unsigned(20 downto 0) := (others => '0');
+signal watchdog_trigger	: std_logic :='0';
 
 begin
 
@@ -198,8 +200,8 @@ SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches
 
 
 --rst_n <= not CLEAR;	PL!
-rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
-rst   <=     (CLEAR or sd_los_i or internal_make_link_reset_out);
+rst_n					<= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
+rst					<=		(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
 
 
 gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
@@ -313,15 +315,28 @@ rx_allow_q <= rx_allow when rising_edge(SYSCLK);
 tx_allow_q <= tx_allow when rising_edge(SYSCLK);
 
 
-PROC_START_TIMER : process begin
-  wait until rising_edge(clk_200_i);
-  if got_link_ready_i = '1' then
-    if start_timer(start_timer'left) = '0' then
-      start_timer <= start_timer + 1;
-    end if;  
-  else
-    start_timer <= (others => '0');
-  end if;
+PROC_START_TIMER : process(clk_200_i)
+begin
+	if rising_edge(clk_200_i) then
+		if got_link_ready_i = '1' then
+			watchdog_timer	<= (others => '0');
+			if start_timer(start_timer'left) = '0' then
+				start_timer <= start_timer + 1;
+			end if;  
+		else
+			start_timer <= (others => '0');
+			if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then
+				watchdog_trigger	<= '1';
+			else 
+				watchdog_trigger	<= '0';
+			end if;
+			if watchdog_trigger = '0' then
+				watchdog_timer	<= watchdog_timer + 1;
+			else 
+				watchdog_timer	<= (others => '0');
+			end if;
+		end if;
+	end if;
 end process;
     
     
diff --git a/source/serdes_sync_downstream.ipx b/source/serdes_sync_downstream.ipx
index 220861b..b1e4559 100644
--- a/source/serdes_sync_downstream.ipx
+++ b/source/serdes_sync_downstream.ipx
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 23 10:40:50.024" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 16 15:03:46.952" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-		<File name="serdes_sync_downstream.lpc" type="lpc" modified="2013 12 23 10:40:48.000"/>
-		<File name="serdes_sync_downstream.pp" type="pp" modified="2013 12 23 10:40:48.000"/>
-		<File name="serdes_sync_downstream.sym" type="sym" modified="2013 12 23 10:40:48.000"/>
-		<File name="serdes_sync_downstream.tft" type="tft" modified="2013 12 23 10:40:48.000"/>
-		<File name="serdes_sync_downstream.txt" type="pcs_module" modified="2013 12 23 10:40:48.000"/>
-		<File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2013 12 23 10:40:48.000"/>
+		<File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 01 16 15:03:44.000"/>
+		<File name="serdes_sync_downstream.pp" type="pp" modified="2014 01 16 15:03:44.000"/>
+		<File name="serdes_sync_downstream.sym" type="sym" modified="2014 01 16 15:03:44.000"/>
+		<File name="serdes_sync_downstream.tft" type="tft" modified="2014 01 16 15:02:59.000"/>
+		<File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 01 16 15:03:44.000"/>
+		<File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 01 16 15:02:59.000"/>
   </Package>
 </DiamondModule>
diff --git a/source/serdes_sync_downstream.lpc b/source/serdes_sync_downstream.lpc
index 1b33f89..34c8b34 100644
--- a/source/serdes_sync_downstream.lpc
+++ b/source/serdes_sync_downstream.lpc
@@ -16,8 +16,8 @@ CoreRevision=8.1
 ModuleName=serdes_sync_downstream
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=12/23/2013
-Time=10:40:48
+Date=01/16/2014
+Time=15:03:44
 
 [Parameters]
 Verilog=0
@@ -91,7 +91,7 @@ _rx_data_width0=8
 _rx_data_width1=8
 _rx_data_width2=8
 _rx_data_width3=8
-_rx_fifo0=ENABLED
+_rx_fifo0=DISABLED
 _rx_fifo1=ENABLED
 _rx_fifo2=ENABLED
 _rx_fifo3=ENABLED
diff --git a/source/serdes_sync_downstream.txt b/source/serdes_sync_downstream.txt
index 42ee441..4432978 100644
--- a/source/serdes_sync_downstream.txt
+++ b/source/serdes_sync_downstream.txt
@@ -20,7 +20,7 @@ CH0_TX_DATA_RATE        "FULL"
 CH0_TX_DATA_WIDTH       "8"
 CH0_RX_DATA_WIDTH        "8"
 CH0_TX_FIFO       "ENABLED"
-CH0_RX_FIFO        "ENABLED"
+CH0_RX_FIFO        "DISABLED"
 CH0_TDRV      "0"
 #CH0_TX_FICLK_RATE      200
 #CH0_RXREFCLK_RATE        "200"
diff --git a/source/serdes_sync_downstream.vhd b/source/serdes_sync_downstream.vhd
index 301b2c5..17cfd20 100644
--- a/source/serdes_sync_downstream.vhd
+++ b/source/serdes_sync_downstream.vhd
@@ -1538,7 +1538,6 @@ entity serdes_sync_downstream is
     hdinp_ch0, hdinn_ch0    :   in std_logic;
     hdoutp_ch0, hdoutn_ch0   :   out std_logic;
     sci_sel_ch0    :   in std_logic;
-    rxiclk_ch0    :   in std_logic;
     txiclk_ch0    :   in std_logic;
     rx_full_clk_ch0   :   out std_logic;
     rx_half_clk_ch0   :   out std_logic;
@@ -2202,7 +2201,7 @@ port map  (
   PCIE_PHYSTATUS_0 => open,
   SCISELCH0 => sci_sel_ch0,
   SCIENCH0 => fpsc_vhi,
-  FF_RXI_CLK_0 => rxiclk_ch0,
+  FF_RXI_CLK_0 => fpsc_vlo,
   FF_TXI_CLK_0 => txiclk_ch0,
   FF_EBRD_CLK_0 => fpsc_vlo,
   FF_RX_F_CLK_0 => rx_full_clk_ch0,
diff --git a/source/soda_client.vhd b/source/soda_client.vhd
index 782a6ba..498ccc8 100644
--- a/source/soda_client.vhd
+++ b/source/soda_client.vhd
@@ -21,6 +21,8 @@ entity soda_client is
 		RX_DLM_IN				: in std_logic;
 		TX_DLM_OUT				: out	std_logic;
 		TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0)	:= (others => '0');
+		TX_DLM_PREVIEW_OUT	: out	std_logic	:= '0';	--PL!
+		LINK_PHASE_IN			: in	std_logic	:= '0';	--PL!
 
 		SODA_DATA_IN			: in	std_logic_vector(31 downto 0)	:= (others => '0');
 		SODA_DATA_OUT			: out	std_logic_vector(31 downto 0)	:= (others => '0');
@@ -91,10 +93,12 @@ begin
 			CLEAR						=>	'0',
 			CLK_EN					=> CLK_EN,
 			--Internal Connection
+			LINK_PHASE_IN			=> LINK_PHASE_IN,
 			START_OF_SUPERBURST	=> start_of_superburst_S,
 			SUPER_BURST_NR_IN		=> super_burst_nr_S,
 			SODA_CMD_STROBE_IN	=> soda_cmd_valid_S,
 			SODA_CMD_WORD_IN		=> soda_cmd_word_S,
+			TX_DLM_PREVIEW_OUT	=>	TX_DLM_PREVIEW_OUT,
 			TX_DLM_OUT				=> tx_dlm_out_S,	--TX_DLM_OUT,
 			TX_DLM_WORD_OUT		=> TX_DLM_WORD_OUT
 		);
diff --git a/source/soda_components.vhd b/source/soda_components.vhd
index 67f81df..9229669 100644
--- a/source/soda_components.vhd
+++ b/source/soda_components.vhd
@@ -161,6 +161,8 @@ package soda_components is
 			RX_DLM_IN				: in std_logic;
 			TX_DLM_OUT				: out	std_logic;
 			TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0) := (others => '0');
+			TX_DLM_PREVIEW_OUT	: out	std_logic	:= '0';	--PL!
+			LINK_PHASE_IN			: in	std_logic	:= '0';	--PL!
 
 			SODA_DATA_IN			: in	std_logic_vector(31 downto 0) := (others => '0');
 			SODA_DATA_OUT			: out	std_logic_vector(31 downto 0) := (others => '0');
@@ -178,12 +180,14 @@ package soda_components is
 			SODACLK					: in	std_logic; -- fabric clock
 			RESET						: in	std_logic; -- synchronous reset
 			CLEAR						: in	std_logic; -- asynchronous reset
-			CLK_EN					: in	std_logic; 
+			CLK_EN					: in	std_logic;
 			--Internal Connection
+			LINK_PHASE_IN			: in	std_logic := '0';	--_vector(1 downto 0) := (others => '0');
 			START_OF_SUPERBURST	: in	std_logic := '0';
 			SUPER_BURST_NR_IN		: in	std_logic_vector(30 downto 0) := (others => '0');
 			SODA_CMD_STROBE_IN	: in	std_logic := '0';	-- 
 			SODA_CMD_WORD_IN		: in	std_logic_vector(30 downto 0) := (others => '0');		--REGIO_CTRL_REG in trbnet handler is 32 bit
+			TX_DLM_PREVIEW_OUT	: out	std_logic := '0';
 			TX_DLM_OUT				: out	std_logic := '0';	-- 
 			TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0) := (others => '0')
 		);
diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd
index 7d31f23..2a165be 100644
--- a/source/soda_packet_builder.vhd
+++ b/source/soda_packet_builder.vhd
@@ -51,8 +51,8 @@ architecture Behavioral of soda_packet_builder is
 	signal	packet_state_S				:	packet_state_type := c_IDLE;
 	
 	signal	soda_dlm_preview_S		: std_logic;
-	signal	soda_cmd_reg_full_S		: std_logic;
-	signal	soda_cmd_reg_S				: std_logic_vector(31 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
+--	signal	soda_cmd_reg_full_S		: std_logic;
+--	signal	soda_cmd_reg_S				: std_logic_vector(31 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
 
 begin
 
@@ -167,10 +167,12 @@ begin
 						packet_state_S	<= c_CMD2;
 						soda_dlm_preview_S	<= '1';
 						soda_pkt_valid_S		<= '0';
+						TIME_CAL_OUT			<= soda_cmd_word_S(30);
 					when c_CMD2	=>
 						packet_state_S	<= c_CMD3;
 						soda_pkt_valid_S		<= '1';
 						soda_pkt_word_S		<= soda_cmd_word_S(23 downto 16);
+						TIME_CAL_OUT			<= '0';
 					when c_CMD3	=>
 						packet_state_S	<= c_CMD4;
 						soda_pkt_valid_S		<= '0';
diff --git a/source/soda_reply_pkt_builder.vhd b/source/soda_reply_pkt_builder.vhd
index 259b20a..47ad048 100644
--- a/source/soda_reply_pkt_builder.vhd
+++ b/source/soda_reply_pkt_builder.vhd
@@ -10,68 +10,142 @@ use work.soda_components.all;
 
 entity soda_reply_pkt_builder is
 	port(
-		SODACLK					: in	std_logic; -- fabric clock
-		RESET						: in	std_logic; -- synchronous reset
-		CLEAR						: in	std_logic; -- asynchronous reset
-		CLK_EN					: in	std_logic; 
+		SODACLK						: in	std_logic; -- fabric clock
+		RESET							: in	std_logic; -- synchronous reset
+		CLEAR							: in	std_logic; -- asynchronous reset
+		CLK_EN						: in	std_logic; 
 		--Internal Connection
-		START_OF_SUPERBURST	: in	std_logic := '0';
-		SUPER_BURST_NR_IN		: in	std_logic_vector(30 downto 0) := (others => '0');
-		SODA_CMD_STROBE_IN	: in	std_logic := '0';	-- 
-		SODA_CMD_WORD_IN		: in	std_logic_vector(30 downto 0) := (others => '0');		--REGIO_CTRL_REG in trbnet handler is 32 bit
-		TX_DLM_OUT				: out	std_logic := '0';	-- 
-		TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0) := (others => '0')
+		LINK_PHASE_IN				: in	std_logic := '0';	--_vector(1 downto 0) := (others => '0');
+		START_OF_SUPERBURST		: in	std_logic := '0';
+		SUPER_BURST_NR_IN			: in	std_logic_vector(30 downto 0) := (others => '0');
+		SODA_CMD_STROBE_IN		: in	std_logic := '0';	-- 
+		SODA_CMD_WORD_IN			: in	std_logic_vector(30 downto 0) := (others => '0');		--REGIO_CTRL_REG in trbnet handler is 32 bit
+		TX_DLM_PREVIEW_OUT		: out	std_logic := '0';	-- 
+		TX_DLM_OUT					: out	std_logic := '0';	-- 
+		TX_DLM_WORD_OUT			: out	std_logic_vector(7 downto 0) := (others => '0')
 	);
 end soda_reply_pkt_builder;
 
 architecture Behavioral of soda_reply_pkt_builder is
 
-	type		packet_state_type is 	(	c_IDLE, c_PKT1, c_PKT2 );
+	type		packet_state_type is 	(	c_IDLE, c_ERROR,
+													c_WAIT4BST1, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8,
+													c_WAIT4CMD1, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8
+												);
 	signal	packet_state_S				:	packet_state_type := c_IDLE;
 
+signal	soda_dlm_preview_S		: std_logic;
+
 begin
 	
-	reply_fsm_proc : process(SODACLK)
+	TX_DLM_PREVIEW_OUT		<= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or
+													((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) 
+													else '0';
+
+reply_fsm_proc : process(SODACLK)
 	begin
-		if rising_edge(SODACLK) then
+		if rising_edge(SODACLK) then
 			if (RESET='1') then
-				packet_state_S		<= c_IDLE;
+				packet_state_S			<= c_IDLE;
+				soda_dlm_preview_S	<= '0';
+				TX_DLM_OUT				<= '0';
+				TX_DLM_WORD_OUT		<= (others=>'0');
 			else
-				case packet_state_S is
-					when c_IDLE	=>
-						if (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1') then
-							packet_state_S	<= c_PKT1;
+				case packet_state_S is
+					when c_IDLE	=>
+						if (START_OF_SUPERBURST='1') then
+							soda_dlm_preview_S	<= '1';
+							if (LINK_PHASE_IN = c_PHASE_H) then
+								packet_state_S	<= c_BST1;
+								TX_DLM_OUT			<= '1';
+								TX_DLM_WORD_OUT	<= SUPER_BURST_NR_IN(7 downto 0);
+							else
+								packet_state_S		<= c_WAIT4BST1;
+								TX_DLM_OUT			<= '0';
+							end if;
+						elsif (SODA_CMD_STROBE_IN='1') then
+							soda_dlm_preview_S	<= '1';
+							if (LINK_PHASE_IN = c_PHASE_H) then
+								packet_state_S	<= c_CMD1;
+								TX_DLM_OUT			<= '1';
+								TX_DLM_WORD_OUT	<= SODA_CMD_WORD_IN(7 downto 0);
+							else
+								packet_state_S		<= c_WAIT4CMD1;
+								TX_DLM_OUT			<= '0';
+							end if;
 						end if;
-					when c_PKT1 =>
-						packet_state_S	<= c_PKT2;
-					when c_PKT2 =>
-						packet_state_S	<= c_IDLE;
+					when c_WAIT4BST1	=>
+						packet_state_S			<= c_BST1;
+						soda_dlm_preview_S	<= '1';
+						TX_DLM_OUT				<= '1';
+						TX_DLM_WORD_OUT		<= '1' & SUPER_BURST_NR_IN(30 downto 24);
+					when c_BST1 =>
+						packet_state_S			<= c_BST2;
+						TX_DLM_OUT				<= '0';
+						soda_dlm_preview_S	<= '0';
+					when c_BST2 =>
+						packet_state_S			<= c_IDLE;
+					when c_WAIT4CMD1	=>
+						packet_state_S	<= c_CMD1;
+						soda_dlm_preview_S	<= '1';
+						TX_DLM_OUT				<= '1';
+						TX_DLM_WORD_OUT		<= '1' & SODA_CMD_WORD_IN(30 downto 24);
+					when c_CMD1 =>
+						packet_state_S	<= c_CMD2;
+						TX_DLM_OUT				<= '0';
+						soda_dlm_preview_S	<= '0';
+					when c_CMD2 =>
+						packet_state_S			<= c_IDLE;
 					when others =>
-						packet_state_S	<= c_IDLE;
+						packet_state_S			<= c_IDLE;
+						TX_DLM_OUT				<= '0';
+						soda_dlm_preview_S	<= '0';
 				end case;
-			end if;
+			end if;
 		end if;
 	end process;
+
+--reply_fsm_proc : process(SODACLK)
+--	begin
+--		if rising_edge(SODACLK) then
+--			if (RESET='1') then
+--				packet_state_S		<= c_IDLE;
+--			else
+--				case packet_state_S is
+--					when c_IDLE	=>
+--						if (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1') then
+--							packet_state_S	<= c_PKT1;
+--						end if;
+--					when c_PKT1 =>
+--						packet_state_S	<= c_PKT2;
+--					when c_PKT2 =>
+--						packet_state_S	<= c_IDLE;
+--					when others =>
+--						packet_state_S	<= c_IDLE;
+--				end case;
+--			end if;
+--		end if;
+--	end process;
 
-	collect_reply_proc : process(SODACLK)
-	begin
-		if rising_edge(SODACLK) then
-			if (RESET='1') then
-				TX_DLM_OUT			<= '0';
-				TX_DLM_WORD_OUT	<= (others=>'0');
-			elsif (START_OF_SUPERBURST='1') then
-				TX_DLM_OUT			<= '1';
-				TX_DLM_WORD_OUT	<= SUPER_BURST_NR_IN(7 downto 0);
-			elsif (SODA_CMD_STROBE_IN='1') then
-				TX_DLM_OUT			<= '1';
-				TX_DLM_WORD_OUT	<= SODA_CMD_WORD_IN(7 downto 0);
-			elsif (packet_state_S=c_PKT1) then
-				TX_DLM_OUT			<= '0';
-			elsif (packet_state_S=c_PKT2) then
-				TX_DLM_WORD_OUT	<= (others=>'0');
-			end if;
-		end if;
-	end process;
+--	collect_reply_proc : process(SODACLK)
+--	begin
+--		if rising_edge(SODACLK) then
+--			if (RESET='1') then
+--				TX_DLM_OUT			<= '0';
+--				TX_DLM_WORD_OUT	<= (others=>'0');
+--			elsif (START_OF_SUPERBURST='1') then
+--				TX_DLM_OUT			<= '1';
+--				TX_DLM_WORD_OUT	<= SUPER_BURST_NR_IN(7 downto 0);
+--			elsif (SODA_CMD_STROBE_IN='1') then
+--				TX_DLM_OUT			<= '1';
+--				TX_DLM_WORD_OUT	<= SODA_CMD_WORD_IN(7 downto 0);
+--			elsif (packet_state_S=c_PKT1) then
+--				TX_DLM_OUT			<= '0';
+--			elsif (packet_state_S=c_PKT2) then
+--				TX_DLM_WORD_OUT	<= (others=>'0');
+--			end if;
+--		end if;
+--	end process;
 	
 
 end architecture;
\ No newline at end of file
diff --git a/source/trb3_periph_sodaclient.vhd b/source/trb3_periph_sodaclient.vhd
index 3625782..2971a3f 100644
--- a/source/trb3_periph_sodaclient.vhd
+++ b/source/trb3_periph_sodaclient.vhd
@@ -198,6 +198,8 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is
   signal tx_dlm_word       : std_logic_vector(7 downto 0);
   signal rx_dlm_word       : std_logic_vector(7 downto 0);
   signal make_reset        : std_logic;
+	signal tx_dlm_preview_S		: std_logic;	--PL!
+	signal link_phase_S			: std_logic;	--PL!
 
   -- SODA slow controll
 	signal soda_ack      : std_logic;
@@ -520,55 +522,57 @@ THE_SPI_RELOAD :  spi_flash_and_fpga_reload	--.flash_reboot_arch
 ---------------------------------------------------------------------------      
 
 THE_SYNC_LINK : med_ecp3_sfp_sync_up
-  generic map(
-    SERDES_NUM  => 0,    --number of serdes in quad
-    IS_SYNC_SLAVE => c_YES
-    )
-  port map(
-    CLK                => clk_raw_internal, --clk_200_i,
-    SYSCLK             => clk_sys_internal,	--clk_sys_i,
-    RESET              => reset_i,
-    CLEAR              => clear_i,
-    --Internal Connection for TrbNet data -> not used a.t.m.
-    MED_DATA_IN        => med_data_out(15 downto 0),
-    MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
-    MED_DATAREADY_IN   => med_dataready_out(0),
-    MED_READ_OUT       => med_read_in(0),
-    MED_DATA_OUT       => med_data_in(15 downto 0),
-    MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
-    MED_DATAREADY_OUT  => med_dataready_in(0),
-    MED_READ_IN        => med_read_out(0),
-    CLK_RX_HALF_OUT    => soda_rx_clock_half,
-    CLK_RX_FULL_OUT    => soda_rx_clock_full,
-    
-    RX_DLM             => rx_dlm_i,
-    RX_DLM_WORD        => rx_dlm_word,
-    TX_DLM             => tx_dlm_i,
-    TX_DLM_WORD        => tx_dlm_word,
-    --SFP Connection
-    SD_RXD_P_IN        => SERDES_ADDON_RX(0),
-    SD_RXD_N_IN        => SERDES_ADDON_RX(1),
-    SD_TXD_P_OUT       => SERDES_ADDON_TX(0),
-    SD_TXD_N_OUT       => SERDES_ADDON_TX(1),
-    SD_REFCLK_P_IN     => '0',
-    SD_REFCLK_N_IN     => '0',
-    SD_PRSNT_N_IN      => SFP_MOD0(1),
-    SD_LOS_IN          => SFP_LOS(1),
-    SD_TXDIS_OUT       => SFP_TXDIS(1),
-    
-    SCI_DATA_IN        => sci1_data_in,
-    SCI_DATA_OUT       => sci1_data_out,
-    SCI_ADDR           => sci1_addr,
-    SCI_READ           => sci1_read,
-    SCI_WRITE          => sci1_write,
-    SCI_ACK            => sci1_ack,  
-    SCI_NACK           => sci1_nack,
-    -- Status and control port
-    STAT_OP            => med_stat_op(15 downto 0),
-    CTRL_OP            => med_ctrl_op(15 downto 0),
-    STAT_DEBUG         => open,
-    CTRL_DEBUG         => (others => '0')
-   );      
+	generic map(
+		SERDES_NUM  => 0,    --number of serdes in quad
+		IS_SYNC_SLAVE => c_YES
+		)
+	port map(
+		CLK                => clk_raw_internal, --clk_200_i,
+		SYSCLK             => clk_sys_internal,	--clk_sys_i,
+		RESET              => reset_i,
+		CLEAR              => clear_i,
+		--Internal Connection for TrbNet data -> not used a.t.m.
+		MED_DATA_IN        => med_data_out(15 downto 0),
+		MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
+		MED_DATAREADY_IN   => med_dataready_out(0),
+		MED_READ_OUT       => med_read_in(0),
+		MED_DATA_OUT       => med_data_in(15 downto 0),
+		MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
+		MED_DATAREADY_OUT  => med_dataready_in(0),
+		MED_READ_IN        => med_read_out(0),
+		CLK_RX_HALF_OUT    => soda_rx_clock_half,
+		CLK_RX_FULL_OUT    => soda_rx_clock_full,
+
+		RX_DLM             => rx_dlm_i,
+		RX_DLM_WORD        => rx_dlm_word,
+		TX_DLM             => tx_dlm_i,
+		TX_DLM_WORD        => tx_dlm_word,
+		TX_DLM_PREVIEW_IN	=> tx_dlm_preview_S,			--PL!
+		LINK_PHASE_OUT		=>	link_phase_S,		--PL!
+		--SFP Connection
+		SD_RXD_P_IN        => SERDES_ADDON_RX(0),
+		SD_RXD_N_IN        => SERDES_ADDON_RX(1),
+		SD_TXD_P_OUT       => SERDES_ADDON_TX(0),
+		SD_TXD_N_OUT       => SERDES_ADDON_TX(1),
+		SD_REFCLK_P_IN     => '0',
+		SD_REFCLK_N_IN     => '0',
+		SD_PRSNT_N_IN      => SFP_MOD0(1),
+		SD_LOS_IN          => SFP_LOS(1),
+		SD_TXDIS_OUT       => SFP_TXDIS(1),
+
+		SCI_DATA_IN        => sci1_data_in,
+		SCI_DATA_OUT       => sci1_data_out,
+		SCI_ADDR           => sci1_addr,
+		SCI_READ           => sci1_read,
+		SCI_WRITE          => sci1_write,
+		SCI_ACK            => sci1_ack,  
+		SCI_NACK           => sci1_nack,
+		-- Status and control port
+		STAT_OP            => med_stat_op(15 downto 0),
+		CTRL_OP            => med_ctrl_op(15 downto 0),
+		STAT_DEBUG         => open,
+		CTRL_DEBUG         => (others => '0')
+	);      
 
    
 ---------------------------------------------------------------------------
@@ -587,7 +591,8 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up
 			RX_DLM_IN				=> rx_dlm_i,
 			TX_DLM_OUT				=> tx_dlm_i, 
 			TX_DLM_WORD_OUT		=> tx_dlm_word,
-
+			TX_DLM_PREVIEW_OUT	=> tx_dlm_preview_S,
+			LINK_PHASE_IN			=> link_phase_S,
 			SODA_DATA_IN			=> soda_data_in,
 			SODA_DATA_OUT			=> soda_data_out,
 			SODA_ADDR_IN			=> soda_addr,