From: Jan Michel Date: Wed, 28 Jun 2023 09:09:29 +0000 (+0200) Subject: add external slow control bus (flashsettings, debuguart) to streaming hub X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=819875fffbe01f165777c7927fbc63785f5fff15;p=trbnet.git add external slow control bus (flashsettings, debuguart) to streaming hub --- diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 67b0438..e93ea4a 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -1153,6 +1153,7 @@ end generate; BUS_MASTER_IN.ack <= DAT_DATAREADY_IN or DAT_WRITE_ACK_IN; BUS_MASTER_IN.nack <= DAT_NO_MORE_DATA_IN; BUS_MASTER_IN.unknown <= DAT_UNKNOWN_ADDR_IN; + BUS_MASTER_IN.data <= DAT_DATA_IN; --Fucking Modelsim wants it like this... diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index fe8ffd5..4c533b4 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -626,6 +626,10 @@ component trb_net16_hub_streaming_port_sctrl_cts is ONEWIRE_MONITOR_OUT : out std_logic; MY_ADDRESS_OUT : out std_logic_vector (15 downto 0); UNIQUE_ID_OUT : out std_logic_vector (63 downto 0); + --Data port - external master (e.g. Flash or Debug) + BUS_MASTER_IN : out CTRLBUS_TX; + BUS_MASTER_OUT : in CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0'); + BUS_MASTER_ACTIVE : in std_logic := '0'; --REGIO INTERFACE (0x8000 - 0xFFFF) REGIO_ADDR_OUT : out std_logic_vector (16-1 downto 0); REGIO_READ_ENABLE_OUT : out std_logic; diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd index cee3c83..4a6a641 100644 --- a/trb_net16_hub_streaming_port_sctrl_cts.vhd +++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd @@ -173,6 +173,10 @@ entity trb_net16_hub_streaming_port_sctrl_cts is ONEWIRE_MONITOR_OUT : out std_logic; MY_ADDRESS_OUT : out std_logic_vector (15 downto 0); UNIQUE_ID_OUT : out std_logic_vector (63 downto 0); + --Data port - external master (e.g. Flash or Debug) + BUS_MASTER_IN : out CTRLBUS_TX; + BUS_MASTER_OUT : in CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0'); + BUS_MASTER_ACTIVE : in std_logic := '0'; --REGIO INTERFACE (0x8000 - 0xFFFF) REGIO_ADDR_OUT : out std_logic_vector (16-1 downto 0); REGIO_READ_ENABLE_OUT : out std_logic; @@ -517,6 +521,9 @@ info_tx_ack_or_info_tx_wack <= info_tx.ack or info_tx.wack; ONEWIRE_MONITOR_OUT=> ONEWIRE_MONITOR_OUT, MY_ADDRESS_OUT => my_address, UNIQUE_ID_OUT => UNIQUE_ID_OUT, + BUS_MASTER_IN => BUS_MASTER_IN, + BUS_MASTER_OUT => BUS_MASTER_OUT, + BUS_MASTER_ACTIVE => BUS_MASTER_ACTIVE, COMMON_CTRL_REGS => common_ctrl, COMMON_STAT_REGS => common_stat, COMMON_CTRL_REG_STROBE => common_ctrl_strobe,