From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Sun, 27 Mar 2022 20:49:05 +0000 (+0200)
Subject: cleanup
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=82194507a9d46a3d0ebcd46a94fa713d76cfbda3;p=trb3sc.git

cleanup
---

diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd
index 84f1eac..a2504dd 100644
--- a/backplanemaster/config.vhd
+++ b/backplanemaster/config.vhd
@@ -14,7 +14,7 @@ package config is
     constant FPGA_TYPE              : integer  := 3;  --3: ECP3, 5: ECP5
 
 -- Link speed
-    constant LINK_SPEED             : integer  := 200; -- 125: 1.25Gbps, 200: 2.00Gbps
+    constant LINK_SPEED             : integer  := 125; -- 125: 1.25Gbps, 200: 2.00Gbps
   
 --Gbe included?
     constant INCLUDE_GBE            : integer  := c_NO;
diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 1e165e1..967ebe3 100644
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -209,14 +209,14 @@ architecture trb3sc_arch of trb3sc_cts is
   signal hit_in_i                    : std_logic_vector(64 downto 1);
   signal mbs_async_out               : std_logic;
   
-  attribute syn_keep of GSR_N        : signal is true;
-  attribute syn_preserve of GSR_N    : signal is true;  
-  attribute syn_keep of bussci1_rx     : signal is true;
-  attribute syn_preserve of bussci1_rx : signal is true;  
+  attribute syn_keep of GSR_N           : signal is true;
+  attribute syn_preserve of GSR_N       : signal is true;  
+  attribute syn_keep of bussci1_rx      : signal is true;
+  attribute syn_preserve of bussci1_rx  : signal is true;  
   attribute syn_keep of bustools_rx     : signal is true;
   attribute syn_preserve of bustools_rx : signal is true;    
-  attribute syn_keep of bustc_rx     : signal is true;
-  attribute syn_preserve of bustc_rx : signal is true;   
+  attribute syn_keep of bustc_rx        : signal is true;
+  attribute syn_preserve of bustc_rx    : signal is true;   
   
   signal tx_dlm_i                    : std_logic;
   signal rx_dlm_i                    : std_logic;
diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index a2f7232..f823109 100644
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -99,7 +99,6 @@ architecture trb3sc_arch of trb3sc_tdctemplate is
   signal reset_i           : std_logic;
 
   signal time_counter      : unsigned(31 downto 0) := (others => '0');
-  signal led               : std_logic_vector(1 downto 0);
   signal debug_clock_reset : std_logic_vector(31 downto 0);
   signal inputs            : std_logic_vector(67 downto 0);
   signal monitor_inputs_i  : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);