From: hadaq Date: Thu, 29 Mar 2007 09:41:09 +0000 (+0000) Subject: add trb_net_dummy_fifo.vhd, Ingo X-Git-Tag: oldGBE~737 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=837c45ee6c8dbafd6da105cf1a60554c97f20039;p=trbnet.git add trb_net_dummy_fifo.vhd, Ingo --- diff --git a/trb_net_active_api.vhd b/trb_net_active_api.vhd index 4f9296f..329d26f 100644 --- a/trb_net_active_api.vhd +++ b/trb_net_active_api.vhd @@ -259,111 +259,7 @@ begin ); end generate CHECK_BUFFER6; - -CHECK_BUFFER1: if FIFO_TERM_BUFFER_DEPTH >0 generate - FIFO_TERM_BUFFER: trb_net_fifo - generic map ( - WIDTH => 51, - DEPTH => FIFO_TERM_BUFFER_DEPTH) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_term_buffer_data_in, - WRITE_ENABLE_IN => fifo_term_buffer_write, - DATA_OUT => fifo_term_buffer_data_out, - READ_ENABLE_IN => fifo_term_buffer_read, - FULL_OUT => fifo_term_buffer_full, - EMPTY_OUT => fifo_term_buffer_empty - ); -end generate CHECK_BUFFER1; -CHECK_BUFFER2: if FIFO_TERM_BUFFER_DEPTH =0 generate - fifo_term_buffer_empty <= '1'; - fifo_term_buffer_full <= '0'; - fifo_term_buffer_data_out <= (others => '0'); - -end generate CHECK_BUFFER2; - - --BUGBUG here we should use the trb_net_term entity - - FIFO_TERM_BUFFER_CTRL: process (tb_current_state, INT_INIT_DATA_IN, - INT_INIT_DATAREADY_IN, tb_next_registered_trailer, - tb_registered_trailer, - fifo_term_buffer_empty, fifo_term_buffer_data_out, - INT_REPLY_READ_IN, tb_registered_target, APL_MY_ADDRESS_IN) - begin -- process - INT_INIT_READ_OUT <= '0'; - fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_ILLEGAL; - fifo_term_buffer_data_in(DWORD_POSITION) <= (others => '0'); - fifo_term_buffer_write <= '0'; - tb_next_state <= MY_ERROR; - tb_next_registered_trailer <= tb_registered_trailer; - tb_next_registered_target <= tb_registered_target; - fifo_term_buffer_read<= '0'; - INT_REPLY_DATAREADY_OUT <= '0'; - INT_REPLY_DATA_OUT(DWORD_POSITION) <= (others => '0'); - INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL; ------------------------------------------------------------------------ --- IDLE ------------------------------------------------------------------------ - if tb_current_state = IDLE then - INT_INIT_READ_OUT <= '1'; -- I always can read - tb_next_state <= IDLE; - if INT_INIT_DATA_IN(TYPE_POSITION) = TYPE_HDR and INT_INIT_DATAREADY_IN = '1' then - -- switch source and target adress - fifo_term_buffer_data_in(SOURCE_POSITION) <= INT_INIT_DATA_IN(TARGET_POSITION); - fifo_term_buffer_data_in(TARGET_POSITION) <= INT_INIT_DATA_IN(SOURCE_POSITION); - fifo_term_buffer_data_in(F3_POSITION) <= INT_INIT_DATA_IN(F3_POSITION); - fifo_term_buffer_data_in(TYPE_POSITION) <= TYPE_HDR; - tb_next_registered_target <= INT_INIT_DATA_IN(TARGET_POSITION); - if fifo_term_buffer_full = '0' and (INT_INIT_DATA_IN(TARGET_POSITION) = APL_MY_ADDRESS_IN - or INT_INIT_DATA_IN(TARGET_POSITION) = BROADCAST_ADRESS) then - fifo_term_buffer_write <= '1'; - else - fifo_term_buffer_write <= '0'; - end if; - elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_DAT and INT_INIT_DATAREADY_IN = '1' then - fifo_term_buffer_data_in <= INT_INIT_DATA_IN; - if fifo_term_buffer_full = '0' and (tb_registered_target = APL_MY_ADDRESS_IN - or tb_registered_target = BROADCAST_ADRESS) then - fifo_term_buffer_write <= '1'; - else - fifo_term_buffer_write <= '0'; - end if; - elsif INT_INIT_DATA_IN(TYPE_POSITION) <= TYPE_TRM and INT_INIT_DATAREADY_IN = '1' then - tb_next_registered_trailer <= INT_INIT_DATA_IN(DWORD_POSITION); - --keep trailer for later use - tb_next_state <= RUNNING; - end if; ------------------------------------------------------------------------ --- RUNNING ------------------------------------------------------------------------ - elsif tb_current_state = RUNNING then - tb_next_state <= RUNNING; - if fifo_term_buffer_empty = '0' then -- Have buffered stuff - INT_REPLY_DATAREADY_OUT <= '1'; - INT_REPLY_DATA_OUT <= fifo_term_buffer_data_out; - if (INT_REPLY_READ_IN = '1') then - fifo_term_buffer_read <= '1'; - end if; - else - tb_next_state <= SEND_TRAILER; - end if; -- Have buffered stuff ------------------------------------------------------------------------ --- TRAILER ------------------------------------------------------------------------ - elsif tb_current_state = SEND_TRAILER then - tb_next_state <= SEND_TRAILER ; - INT_REPLY_DATAREADY_OUT <= '1'; - INT_REPLY_DATA_OUT(DWORD_POSITION) <= tb_registered_trailer; - INT_REPLY_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - if (INT_REPLY_READ_IN = '1') then - tb_next_state <= IDLE; - tb_next_registered_target <= ILLEGAL_ADRESS; - end if; - end if; -- tb_current_state switch - end process; - + INIT_SBUF: trb_net_sbuf generic map (DATA_WIDTH => 51, @@ -388,24 +284,25 @@ next_registered_trailer <= combined_trailer; next_APL_DATA_OUT <= fifo_to_apl_data_out(DWORD_POSITION); next_APL_TYP_OUT <= fifo_to_apl_data_out(TYPE_POSITION); - process (out_select, combined_header, registered_trailer, - fifo_to_int_data_out) - begin - if out_select = HDR then - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_HDR; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_header; - elsif out_select = TRM then - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer; - elsif out_select = TRM_COMB then - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_trailer; - else - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; - end if; - end process; - + process (out_select, combined_header, registered_trailer, + fifo_to_int_data_out) + begin + if out_select = HDR then + next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_HDR; + next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_header; + elsif out_select = TRM then + next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; + next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer; + elsif out_select = TRM_COMB then + next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; + next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_trailer; + else + next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; + next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + end if; + end process; +-- kostet 2% + -- combinatorial part of state machine STATE_COMB : process(current_state, APL_SEND_IN, combined_header, INT_INIT_READ_IN, APL_WRITE_IN, fifo_to_int_empty, diff --git a/trb_net_dummy_fifo.vhd b/trb_net_dummy_fifo.vhd new file mode 100644 index 0000000..57c778c --- /dev/null +++ b/trb_net_dummy_fifo.vhd @@ -0,0 +1,91 @@ +-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo + +library ieee; + +use ieee.std_logic_1164.all; + +USE ieee.std_logic_signed.ALL; + +USE ieee.std_logic_arith.ALL; + + + +entity trb_net_dummy_fifo is + + generic (WIDTH : integer := 51); + + port (CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); + +end trb_net_dummy_fifo; + +architecture arch_trb_net_dummy_fifo of trb_net_dummy_fifo is + + signal current_DOUT, next_DOUT : std_logic_vector(WIDTH -1 downto 0); + signal current_FULL, next_FULL : std_logic; + signal current_EMPTY, next_EMPTY : std_logic; + + begin + + FULL_OUT <= current_FULL; + EMPTY_OUT <= current_EMPTY; + DATA_OUT <= current_DOUT; + + process(READ_ENABLE_IN, WRITE_ENABLE_IN, current_EMPTY) + begin + if WRITE_ENABLE_IN = '1' and READ_ENABLE_IN = '1' then + next_FULL <= current_FULL; + next_EMPTY <= current_EMPTY; + elsif WRITE_ENABLE_IN = '1' then + next_FULL <= '1'; + next_EMPTY <= '0'; + elsif READ_ENABLE_IN = '1' then + next_FULL <= '0'; + next_EMPTY <= '1'; + else + next_FULL <= current_FULL; + next_EMPTY <= current_EMPTY; + end if; + end process; + + reg_empty: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_EMPTY <= '1'; + current_FULL <= '0'; + elsif CLK_EN = '1' then + current_EMPTY <= next_EMPTY; + current_FULL <= next_FULL; + else + current_EMPTY <= current_EMPTY; + current_FULL <= current_FULL; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_DOUT <= (others => '0'); + elsif WRITE_ENABLE_IN = '1' then + current_DOUT <= DATA_IN; + else + current_DOUT <= current_DOUT; + end if; + end if; + end process; + +end arch_trb_net_dummy_fifo; +