From: hadeshyp Date: Fri, 14 Dec 2012 13:15:23 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=84268f02c60e7c97420b460e581671c230a066e3;p=trb3.git *** empty log message *** --- diff --git a/base/code/mbs_vulom_recv.vhd b/base/code/mbs_vulom_recv.vhd index 11f4719..a5b1863 100644 --- a/base/code/mbs_vulom_recv.vhd +++ b/base/code/mbs_vulom_recv.vhd @@ -61,6 +61,7 @@ signal first_bits_fast : std_logic; signal first_bits_slow : std_logic; signal reg_MBS_IN : std_logic; signal done : std_logic; +signal done_slow : std_logic; signal number_reg : std_logic_vector(23 downto 0); signal status_reg : std_logic_vector(1 downto 0); @@ -72,7 +73,7 @@ signal trg_sync : std_logic; type state_t is (IDLE, WAIT1,WAIT2,WAIT3,WAIT4, FINISH); signal state : state_t; -type rdo_state_t is (RDO_IDLE, RDO_WRITE, RDO_FINISH); +type rdo_state_t is (RDO_IDLE, RDO_WAIT, RDO_WRITE, RDO_FINISH); signal rdostate : rdo_state_t; signal config_rdo_disable_i : std_logic; @@ -104,6 +105,7 @@ PROC_FSM: process begin case state is when IDLE => bitcnt <= 37; + done <= '1'; if reg_MBS_IN = '0' then done <= '0'; state <= WAIT1; @@ -139,9 +141,11 @@ PROC_FSM: process begin end if; end process; +done_slow <= done when rising_edge(CLK); + PROC_REG_INFO : process begin wait until rising_edge(CLK); - if done = '1' then + if done_slow = '1' then number_reg <= shift_reg(31 downto 8); status_reg <= shift_reg(7 downto 6); @@ -162,10 +166,21 @@ PROC_RDO : process begin case rdostate is when RDO_IDLE => if TRIGGER_IN = '1' and config_rdo_disable_i = '0' then - rdostate <= RDO_FINISH; - DATA_OUT <= error_reg & status_reg & "00000" & number_reg; - WRITE_OUT <= '1'; + if done_slow = '0' then + rdostate <= RDO_WAIT; + else + rdostate <= RDO_WRITE; + end if; end if; + when RDO_WAIT => + if done_slow = '1' then + rdostate <= RDO_WRITE; + end if; + when RDO_WRITE => + rdostate <= RDO_FINISH; + DATA_OUT <= error_reg & status_reg & "00000" & number_reg; + WRITE_OUT <= '1'; + when RDO_FINISH => FINISHED_OUT <= '1'; rdostate <= RDO_IDLE; @@ -174,7 +189,7 @@ end process; config_rdo_disable_i <= CONTROL_REG_IN(0); -STATUS_REG_OUT <= error_reg & reg_MBS_IN & std_logic_vector(to_unsigned(bitcnt,6)) & number_reg; -DEBUG <= x"0000" & done & reg_MBS_IN & shift_reg(13 downto 0); +STATUS_REG_OUT <= error_reg & '0' & std_logic_vector(to_unsigned(bitcnt,6)) & number_reg; +DEBUG <= x"00000000"; -- & done & '0' & shift_reg(13 downto 0); end architecture; \ No newline at end of file diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index ca3bce6..b1b8dac 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -450,4 +450,3 @@ package trb3_components is end package; - diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index 6b23a7b..795e62e 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -9,8 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_central"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; -# my $synplify_path = '/d/jspc29/lattice/synplify/fpga_e201103/'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.0'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; @@ -114,7 +113,7 @@ $c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +$c=qq|multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; execute($c); # IOR IO Timing Report diff --git a/cts/trb3_central.p2t b/cts/trb3_central.p2t index 9108758..63675c0 100644 --- a/cts/trb3_central.p2t +++ b/cts/trb3_central.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 5 +-t 8 -c 1 -e 2 #-g guidefile.ncd diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf index db3a475..d08948a 100644 --- a/cts/trb3_central_constraints.lpf +++ b/cts/trb3_central_constraints.lpf @@ -50,7 +50,7 @@ REGION "REGION_CTS" "R42C38D" 37 57 DEVSIZE; # BLKNAME THE_CTS; # LOCATE UGROUP "cts_group" REGION "REGION_CTS"; MULTICYCLE TO CELL "THE_CMB/trg_sync" 20 ns; - +MULTICYCLE TO CELL "THE_CMB/error_reg" 20 ns; #TrbNet Hub REGION "REGION_IOBUF" "R54C90D" 60 86 DEVSIZE; diff --git a/tdc_test/trb3_periph.prj b/tdc_test/trb3_periph.prj index a741ae0..56c52c2 100644 --- a/tdc_test/trb3_periph.prj +++ b/tdc_test/trb3_periph.prj @@ -164,27 +164,28 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" #add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/TDC.vhd" #add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/up_counter.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/trb3_periph.vhd" -##add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Adder_304.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/bit_sync.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Encoder_304_Bit.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/FIFO_32x32_OutReg.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Reference_channel.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_encoder_3.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_FIFO.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/TDC.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/up_counter.vhd" - -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/trb3_periph.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Adder_304.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/bit_sync.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel_200.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Encoder_304_Bit.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/FIFO_32x32_OutReg.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Reference_Channel.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_encoder_3.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_FIFO.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/TDC.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/up_counter.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/trb3_periph.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Adder_304.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/bit_sync.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel_200.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Encoder_304_Bit.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/FIFO_32x32_OutReg.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Reference_channel.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_encoder_3.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_FIFO.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/TDC.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/up_counter.vhd" + +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/trb3_periph.vhd" +# #add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Adder_304.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/bit_sync.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel_200.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Encoder_304_Bit.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/FIFO_32x32_OutReg.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Reference_Channel.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_encoder_3.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_FIFO.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/TDC.vhd" +# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/up_counter.vhd" diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd index 26a5b82..c03699d 100644 --- a/trb3_gbe/trb3_central.vhd +++ b/trb3_gbe/trb3_central.vhd @@ -15,7 +15,7 @@ use work.trb_net_gbe_components.all; entity trb3_central is generic ( - USE_ETHERNET : integer range c_NO to c_YES := c_YES + USE_ETHERNET : integer range c_NO to c_YES := c_NO ); port( --Clocks @@ -419,10 +419,10 @@ gen_normal_hub : if USE_ETHERNET = c_NO generate MII_IS_DOWNLINK => (4 => 0, others => 1), MII_IS_UPLINK_ONLY=> (4 => 1, others => 0), INT_NUMBER => 0, - INT_CHANNELS => (0,1,3,3,3,3,3,3), + INT_CHANNELS => (others => 0), USE_ONEWIRE => c_YES, COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), - HARDWARE_VERSION => x"90000000", + HARDWARE_VERSION => x"90000030", INIT_ENDPOINT_ID => x"0005", INIT_ADDRESS => x"F305", BROADCAST_SPECIAL_ADDR => x"40" @@ -468,6 +468,8 @@ gen_normal_hub : if USE_ETHERNET = c_NO generate CTRL_DEBUG => (others => '0'), STAT_DEBUG => open ); + + reset_via_gbe <= '0'; end generate; gen_ethernet_hub : if USE_ETHERNET = c_YES generate diff --git a/wasa/compile_panda_dirc_wasa_frankfurt.pl b/wasa/compile_panda_dirc_wasa_frankfurt.pl index cf6dead..4df50a4 100755 --- a/wasa/compile_panda_dirc_wasa_frankfurt.pl +++ b/wasa/compile_panda_dirc_wasa_frankfurt.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "panda_dirc_wasa"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.0'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; diff --git a/wasa/cores/UFM_WB.v b/wasa/cores/UFM_WB.v index c2f2c20..a85c386 100644 --- a/wasa/cores/UFM_WB.v +++ b/wasa/cores/UFM_WB.v @@ -44,6 +44,8 @@ `timescale 1ns / 100ps `include "efb_define_def.v" +`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/GSR.v" +`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/PUR.v" module UFM_WB( input clk_i @@ -127,6 +129,9 @@ reg n_wr_en_ufm; reg[4:0] n_count; reg n_ufm_addr_MSB; + PUR PUR_INST (.PUR(1'b1)); + GSR GSR_INST (.GSR(1'b1)); + flash inst1 ( .wb_clk_i(clk_i ), // EFB with UFM enabled .wb_rst_i(!rst_n ), .wb_cyc_i(wb_cyc_i ), @@ -159,6 +164,7 @@ always @ (*) begin sm_rd_data <= mem_rd_data; mem_we <= sm_we; + mem_ce <= sm_ce; mem_clk <= clk_i; mem_addr <= sm_addr; mem_wr_data <= sm_wr_data; diff --git a/wasa/cores/flash.ipx b/wasa/cores/flash.ipx index 56e95bc..e9d3469 100644 --- a/wasa/cores/flash.ipx +++ b/wasa/cores/flash.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/wasa/cores/flash.lpc b/wasa/cores/flash.lpc index db62717..50cf74d 100644 --- a/wasa/cores/flash.lpc +++ b/wasa/cores/flash.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=EFB -CoreRevision=1.0 +CoreRevision=1.1 ModuleName=flash SourceFormat=VHDL ParameterFileVersion=1.0 -Date=08/09/2012 -Time=14:22:11 +Date=12/10/2012 +Time=14:50:11 [Parameters] Verilog=0 diff --git a/wasa/cores/flash.vhd b/wasa/cores/flash.vhd index aad5a20..e8088ed 100644 --- a/wasa/cores/flash.vhd +++ b/wasa/cores/flash.vhd @@ -1,15 +1,15 @@ --- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) --- Module Version: 1.0 ---/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 33.33 -ufm -ufm_ebr 0 -mem_size 767 -ufm_0 -wb -dev 4000 -e +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 1.1 +--/d/jspc29/lattice/diamond/2.0/ispfpga/bin/lin/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 33.33 -ufm -ufm_ebr 0 -mem_size 767 -ufm_0 -wb -dev 4000 -e --- Thu Aug 9 14:22:11 2012 +-- Mon Dec 10 14:50:11 2012 library IEEE; use IEEE.std_logic_1164.all; --- -- synopsys translate_off +-- synopsys translate_off library MACHXO2; use MACHXO2.components.all; --- -- synopsys translate_on +-- synopsys translate_on entity flash is port ( @@ -148,10 +148,10 @@ begin SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED", SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER", EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED", - I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b0011001", + I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010", I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED", I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz", - I2C1_SLAVE_ADDR=> "0b0011001", I2C1_ADDRESSING=> "7BIT", + I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT", EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.3") port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i, WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7), diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd index e4697d0..bed5e96 100644 --- a/wasa/panda_dirc_wasa.vhd +++ b/wasa/panda_dirc_wasa.vhd @@ -213,19 +213,26 @@ signal inp_hold : std_logic_vector(15 downto 0); signal inp_gated : std_logic_vector(15 downto 0); signal inp_hold_reg: std_logic_vector(15 downto 0); signal last_inp_hold_reg: std_logic_vector(15 downto 0); +signal flash_go_tmp : std_logic_vector(5 downto 0); +signal flash_reset_n : std_logic; + +signal pwm_data_i : std_logic_vector(15 downto 0); +signal pwm_data_o : std_logic_vector(15 downto 0); +signal pwm_write_i : std_logic; +signal pwm_addr_i : std_logic_vector(3 downto 0); +type fsm_state is (IDLE, PWM_WRITE_GET_1, PWM_WRITE_GET_2, PWM_WRITE, PWM_WAIT); +signal fsm_copydat : fsm_state; + +signal pwm_fsm_data_i : std_logic_vector(15 downto 0); +signal pwm_fsm_addr : std_logic_vector(3 downto 0); +signal pwm_fsm_write : std_logic; +signal fsm_job : std_logic_vector(1 downto 0); +signal ram_fsm_data_i : std_logic_vector(7 downto 0); +signal ram_fsm_addr_i : std_logic_vector(3 downto 0); +signal ram_fsm_write_i: std_logic; begin --- PROC_RESET : process begin --- wait until rising_edge(clk_osc); --- reset_i <= not pll_lock; --- -- if reset_cnt /= x"F" then --- -- reset_cnt <= reset_cnt + 1; --- -- reset_i <= '1'; --- -- end if; --- end process; - - THE_PLL : pll port map( @@ -275,13 +282,27 @@ SPI_OUT <= buf_SPI_OUT; -- RAM Interface --------------------------------------------------------------------------- -ram_write_i <= spi_write_i(4); --or signal from Flash entity -ram_data_i <= spi_data_i(7 downto 0); --or signal from Flash entity -ram_addr_i <= spi_channel_i(3 downto 0); --or signal from Flash entity -spi_reg40_i <= x"00" & ram_data_o; +spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o; + +PROC_CTRL_FLASH : process begin + wait until rising_edge(clk_i); + if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"0") then + flash_command <= spi_data_i(14 downto 12); + flash_page <= spi_data_i(10 downto 0); + flash_go_tmp(0)<= '1'; + else + flash_go_tmp(5 downto 0) <= flash_go_tmp(4 downto 0) & '0'; + end if; + if flash_reset_n = '0' then + flash_go_tmp <= (others => '0'); + end if; +end process; + + flash_go <= or_all(flash_go_tmp); + THE_FLASH_RAM : flashram port map( DataInA => ram_data_i, @@ -304,26 +325,68 @@ THE_FLASH_RAM : flashram -- Flash Controller --------------------------------------------------------------------------- --- THE_FLASH : UFM_WB --- port map( --- clk_i => clk_26, --- rst_n => '1', --- cmd => flash_command, --- ufm_page => flash_page, --- GO => flash_go, --- BUSY => flash_busy, --- ERR => flash_err, --- mem_clk => open, --- mem_we => flashram_write_i, --- mem_ce => flashram_cen_i, --- mem_addr => flashram_addr_i, --- mem_wr_data => flashram_data_i, --- mem_rd_data => flashram_data_o --- ); +THE_FLASH : UFM_WB + port map( + clk_i => clk_26, + rst_n => flash_reset_n, + cmd => flash_command, + ufm_page => flash_page, + GO => flash_go, + BUSY => flash_busy, + ERR => flash_err, + mem_clk => open, + mem_we => flashram_write_i, + mem_ce => flashram_cen_i, + mem_addr => flashram_addr_i, + mem_wr_data => flashram_data_i, + mem_rd_data => flashram_data_o + ); + +PROC_DATA_COPY : process + variable count : integer range 0 to 31 := 0; + variable tmp : std_logic_vector(7 downto 0); +begin + wait until rising_edge(clk_i); + pwm_fsm_write <= '0'; + ram_fsm_write_i <= '0'; + case fsm_copydat is + when IDLE => + count := 0; + if spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"1" then + fsm_copydat <= PWM_WRITE_GET_1; + ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4)); + fsm_job <= spi_channel_i(1 downto 0); + count := count + 1; + end if; + when PWM_WRITE_GET_1 => + ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4)); + count := count + 1; + fsm_copydat <= PWM_WRITE_GET_2; + when PWM_WRITE_GET_2 => + fsm_copydat <= PWM_WRITE; + tmp := ram_data_o; + when PWM_WRITE => + pwm_fsm_data_i <= tmp & ram_data_o; + pwm_fsm_write <= '1'; + pwm_fsm_addr <= fsm_job(0) & std_logic_vector(to_unsigned(count/2-1,3)); + + if(count < 15) then + fsm_copydat <= PWM_WRITE_GET_1; + else + fsm_copydat <= PWM_WAIT; + end if; + + ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4)); + count := count + 1; + + when PWM_WAIT => + fsm_copydat <= IDLE; + end case; + if onewire_reset = '1' then + fsm_copydat <= IDLE; + end if; +end process; - --- PUR_INST : PUR port map(PUR=>'1'); --- GSR_INST : GSR port map(GSR=>'1'); --------------------------------------------------------------------------- -- PWM --------------------------------------------------------------------------- @@ -331,27 +394,40 @@ THE_FLASH_RAM : flashram THE_PWM_GEN : pwm_generator port map( CLK => clk_i, - DATA_IN => spi_data_i, - DATA_OUT => spi_reg00_i, - WRITE_IN => spi_write_i(0), - ADDR_IN => spi_channel_i(3 downto 0), + DATA_IN => pwm_data_i, + DATA_OUT => pwm_data_o, + WRITE_IN => pwm_write_i, + ADDR_IN => pwm_addr_i, PWM => pwm_i ); PWM <= pwm_i(15 downto 0); --- PWM_ODDR : oddr16 --- port map( --- clk => clk_i, --- clkout => open, --- reset => '0', --- sclk => open, --- dataout => pwm_i, --- dout => PWM --- ); +spi_reg00_i <= pwm_data_o; + +PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i, + pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write, + ram_fsm_addr_i, ram_fsm_data_i, ram_fsm_write_i) +begin + if(fsm_copydat = IDLE) then + pwm_data_i <= spi_data_i; + pwm_write_i <= spi_write_i(0); + pwm_addr_i <= spi_channel_i(3 downto 0); + ram_write_i <= spi_write_i(4); + ram_data_i <= spi_data_i(7 downto 0); + ram_addr_i <= spi_channel_i(3 downto 0); + else + pwm_data_i <= pwm_fsm_data_i; + pwm_write_i <= pwm_fsm_write; + pwm_addr_i <= pwm_fsm_addr; + ram_write_i <= ram_fsm_write_i; + ram_data_i <= ram_fsm_data_i; + ram_addr_i <= ram_fsm_addr_i; + end if; +end process; + - --------------------------------------------------------------------------- -- Temperature Sensor --------------------------------------------------------------------------- @@ -391,7 +467,7 @@ PROC_IDMEM : process begin end if; end process; - +flash_reset_n <= not onewire_reset; --------------------------------------------------------------------------- -- I/O Register 0x20 @@ -434,6 +510,8 @@ end process; inp_status <= INP when rising_edge(clk_i); last_inp <= inp_status(3 downto 0) when rising_edge(clk_i); + + --------------------------------------------------------------------------- -- LED blinking when activity on inputs --------------------------------------------------------------------------- @@ -461,17 +539,6 @@ SPARE_LINE(2) <= '0'; --timer(18); SPARE_LINE(3) <= '0'; - --- process(inp_gated,clk_i); --- begin --- if inp_gated(i) then --- inp_hold(i) <= inp_gated(i); --- elsif rising_edge(clk_i) then --- inp_hold(i) <= inp_hold(i) and not inp_hold_reg(i); --- end if; --- end process; --- - inp_hold <= (inp_gated or inp_hold) and not inp_hold_reg; inp_hold_reg <= inp_hold when rising_edge(clk_i); last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_i); @@ -504,11 +571,18 @@ last_inp_long_reg <= inp_long_reg when rising_edge(clk_i); -- TEST_LINE(0) <= '0'; -- TEST_LINE(15 downto 1) <= (others => '0'); -TEST_LINE(7 downto 0) <= spi_debug_i(7 downto 0); -TEST_LINE(10 downto 8) <= id_addr_i(2 downto 0); -TEST_LINE(11) <= onewire_monitor; -TEST_LINE(12) <= id_write_i; -TEST_LINE(15 downto 13) <= id_data_i(2 downto 0); +-- TEST_LINE(0) <= '0'; +-- TEST_LINE(1) <= spi_write_i(5); +-- TEST_LINE(2) <= pwm_write_i; +-- TEST_LINE(3) <= ram_write_i; +-- TEST_LINE(7 downto 4) <= pwm_addr_i; +-- TEST_LINE(11 downto 8) <= ram_addr_i; +-- TEST_LINE(12) <= spi_write_i(4); +-- TEST_LINE(13) <= ; +-- TEST_LINE(14) <= '1' when fsm_copydat = PWM_WRITE_GET_1 or fsm_copydat = PWM_WRITE_GET_2 else '0'; +-- TEST_LINE(15) <= '1' when fsm_copydat = PWM_WRITE_GET_2 or fsm_copydat = PWM_WRITE else '0'; +-- + LED_GREEN <= not leds(0) when led_status(4) = '0' else not led_status(0); LED_ORANGE <= not leds(1) when led_status(4) = '0' else not led_status(1); @@ -517,3 +591,35 @@ LED_YELLOW <= not leds(3) when led_status(4) = '0' else not led_status(3); end architecture; + + + +-- PWM_ODDR : oddr16 +-- port map( +-- clk => clk_i, +-- clkout => open, +-- reset => '0', +-- sclk => open, +-- dataout => pwm_i, +-- dout => PWM +-- ); + +-- PROC_RESET : process begin +-- wait until rising_edge(clk_osc); +-- reset_i <= not pll_lock; +-- -- if reset_cnt /= x"F" then +-- -- reset_cnt <= reset_cnt + 1; +-- -- reset_i <= '1'; +-- -- end if; +-- end process; + + +-- process(inp_gated,clk_i); +-- begin +-- if inp_gated(i) then +-- inp_hold(i) <= inp_gated(i); +-- elsif rising_edge(clk_i) then +-- inp_hold(i) <= inp_hold(i) and not inp_hold_reg(i); +-- end if; +-- end process; +-- diff --git a/wasa/sim/machxo.mpf b/wasa/sim/machxo.mpf index 7b8bc7d..0464cff 100644 --- a/wasa/sim/machxo.mpf +++ b/wasa/sim/machxo.mpf @@ -627,7 +627,7 @@ Resolution = ns UserTimeUnit = default ; Default run length -RunLength = 10 us +RunLength = 200 us ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 @@ -1645,41 +1645,43 @@ suppress = 8780 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 17 +Project_Files_Count = 18 Project_File_0 = /d/jspc22/trb/cvs/trb3/wasa/cores/efb_define_def.v -Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1344528395 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1344528395 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_1 = /d/jspc22/trb/cvs/trbnet/trb_net_components.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346851369 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - 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vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+/d/jspc22/trb/cvs/trb3/wasa/cores compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_11 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_12 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344353596 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_13 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344852431 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355218918 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_3 = /d/jspc22/trb/cvs/trb3/tdc_test/modelsim/sim_pulsestretch.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1348848169 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/full_tb.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355226184 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_5 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346854393 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_6 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355228266 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_7 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1348839333 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_8 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355228319 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_9 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849814 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_10 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_11 = /d/jspc22/trb/cvs/trb3/wasa/cores/UFM_WB.v +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1355162337 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+/d/jspc22/trb/cvs/trb3/wasa/cores compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_12 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_13 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350664433 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_14 = /d/jspc22/trb/cvs/trb3/wasa/cores/flashram.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516091 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_15 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516091 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_15 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355147411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_16 = /d/jspc22/trb/cvs/trb3/wasa/cores/pll.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849713 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849713 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_17 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/wasa/source/pwm.vhd b/wasa/source/pwm.vhd index 7f91d69..d167d44 100644 --- a/wasa/source/pwm.vhd +++ b/wasa/source/pwm.vhd @@ -13,6 +13,7 @@ entity pwm_generator is WRITE_IN : in std_logic := '0'; ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0'); + PWM : out std_logic_vector(31 downto 0) ); diff --git a/wasa/source/tb/full_tb.vhd b/wasa/source/tb/full_tb.vhd index ad3e880..6c22f24 100644 --- a/wasa/source/tb/full_tb.vhd +++ b/wasa/source/tb/full_tb.vhd @@ -70,7 +70,7 @@ reset <= '0' after 30 ns; process begin wait for 101 ns; bus_addr <= "00000"; - bus_data <= x"0010abcd"; + bus_data <= x"51800000"; bus_write <= '1'; wait for 10 ns; bus_write <= '0'; @@ -91,7 +91,7 @@ process begin wait for 10010 ns; bus_addr <= "00000"; - bus_data <= x"0013cd46"; + bus_data <= x"51810000"; bus_write <= '1'; wait for 10 ns; bus_write <= '0'; diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index e2d26b3..0111ae8 100644 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -311,7 +311,7 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91004060", + REGIO_HARDWARE_VERSION => x"91004950", REGIO_INIT_ADDRESS => x"f306", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 100, @@ -654,14 +654,14 @@ padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0)); CONTROL_REG_IN => ctrl_reg); - hit_in_i <= INP; +-- hit_in_i <= INP; -- to detect rising & falling edges --hit_in_i(1) <= not timing_trg_received_i; - --Gen_Hit_In_Signals : for i in 1 to 15 generate - -- hit_in_i(i*2) <= INPUT(i-1); - -- hit_in_i(i*2+1) <= not INPUT(i-1); - --end generate Gen_Hit_In_Signals; + Gen_Hit_In_Signals : for i in 0 to 31 generate + hit_in_i(i*2) <= INP(i); + hit_in_i(i*2+1) <= not INP(i); + end generate Gen_Hit_In_Signals; end architecture;