From: Cahit Date: Mon, 21 Mar 2016 13:44:14 +0000 (+0100) Subject: updated project file, config compile file, tdc version number for the project X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8436917675020c90e59fa61810b5565f88a2f72f;p=dirich.git updated project file, config compile file, tdc version number for the project --- diff --git a/dirich/config_compile_gsi.pl b/dirich/config_compile_gsi.pl new file mode 100644 index 0000000..e7f0dff --- /dev/null +++ b/dirich/config_compile_gsi.pl @@ -0,0 +1,21 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA381', +Speedgrade => '8', + +TOPNAME => "dirich", +lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.6_x64', +synplify_path => '/opt/synplicity/K-2015.09', +#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => '../nodes_lxhadeb07.txt', +pinout_file => 'dirich', + +include_TDC => 1, +include_GBE => 0, + +firefox_open => 0, +twr_number_of_errors => 20, diff --git a/dirich/dirich.prj b/dirich/dirich.prj index b0c6b6a..02e46e3 100644 --- a/dirich/dirich.prj +++ b/dirich/dirich.prj @@ -59,6 +59,7 @@ add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" #Basic Infrastructure add_file -vhdl -lib work "../cores/pll_240_100/pll_240_100.vhd" @@ -109,6 +110,7 @@ add_file -vhdl -lib work "../../trbnet/special/uart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" @@ -175,7 +177,37 @@ add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" - +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" +#add_file -vhdl -lib work "tdc_release/BusHandler.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" +#add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout_record.vhd" +#add_file -vhdl -lib work "tdc_release/Readout.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC_record.vhd" +#add_file -vhdl -lib work "tdc_release/TDC.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd" add_file -vhdl -lib work "./dirich.vhd" diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 5e600f7..ddad189 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -82,8 +82,8 @@ architecture dirich_arch of dirich is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; - signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -94,11 +94,14 @@ architecture dirich_arch of dirich is signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); - signal pwm_i : std_logic_vector(31 downto 0); - signal timer : TIMERS; - signal lcd_data : std_logic_vector(511 downto 0); - signal hdr_io : std_logic_vector(9 downto 0); - signal led_off : std_logic; + signal pwm_i : std_logic_vector(31 downto 0); + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + signal hdr_io : std_logic_vector(9 downto 0); + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(32 downto 1); + signal logic_analyser_i : std_logic_vector(16 downto 1); attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -224,9 +227,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, others => 0), + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -240,10 +243,12 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record BUS_RX(1) => bussci_rx, --SCI Serdes BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busthresh_rx, + BUS_RX(4) => bustdc_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busthresh_tx, + BUS_TX(4) => bustdc_tx, STAT_DEBUG => open ); @@ -270,7 +275,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record SPI_CLK_OUT => open, --Header HEADER_IO => hdr_io, - LED_DISABLE => led_off, +-- LED_DISABLE => led_off, --LCD LCD_DATA_IN => lcd_data, --ADC @@ -345,7 +350,46 @@ THE_PWM_GEN : entity work.pwm_generator end if; end process; - +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => CLOCK_IN, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => TRIG_IN, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => CLOCK_CAL, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => logic_analyser_i + ); + + -- For single edge measurements + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i <= INPUT; + end generate; + + -- For ToT Measurements + gen_double : if DOUBLE_EDGE_TYPE = 2 generate + Gen_Hit_In_Signals : for i in 1 to 16 generate + hit_in_i(i*2-1) <= INPUT(i-1); + hit_in_i(i*2) <= not INPUT(i-1); + end generate Gen_Hit_In_Signals; + end generate; + end architecture; diff --git a/dirich/tdc_release b/dirich/tdc_release new file mode 120000 index 0000000..6a654d0 --- /dev/null +++ b/dirich/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3 \ No newline at end of file diff --git a/dirich/dirich.lpf b/pinout/basic_constraints.lpf similarity index 85% rename from dirich/dirich.lpf rename to pinout/basic_constraints.lpf index 18434dc..fdbb754 100644 --- a/dirich/dirich.lpf +++ b/pinout/basic_constraints.lpf @@ -3,6 +3,9 @@ BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; +################################################################# +# Basic Settings +################################################################# SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON BANK 0 VCCIO 2.5 V; @@ -32,3 +35,4 @@ MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; GSR_NET NET "GSR_N"; +