From: Jan Michel <j.michel@gsi.de>
Date: Wed, 26 Jul 2017 16:14:04 +0000 (+0200)
Subject: Include code for synchronous read-out and busy in CTS
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=855e7cae21e73255bdf37a01fc0f49556ccae58f;p=trb3.git

Include code for synchronous read-out and busy in CTS
---

diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd
index 4b633dd..4cc8217 100755
--- a/cts/source/cts.vhd
+++ b/cts/source/cts.vhd
@@ -345,6 +345,9 @@ architecture RTL of CTS is
    
    signal trg_information_reg : std_logic_vector(23 downto 0);
    
+   signal busy_out_counter : unsigned(3 downto 0);
+   signal busy_out_i, busy_end_i : std_logic;
+   
 begin
    assert(EFFECTIVE_INPUT_COUNT > 0) report "The CTS requires atleast 1 input or input multiplexer";
    assert(TRIGGER_ADDON_COUNT = 0 or ADDON_LINE_COUNT > 0) report "If you use an input multiplexer you have to provide atleast 1 addon input line";
@@ -571,7 +574,9 @@ begin
    
    CTS_TRG_TYPE_OUT <= trigger_type_buf_i;
    
-   
+----------------------------------------------------
+-- Normal Busy out option
+----------------------------------------------------   
    proc_busyout : process begin
      wait until rising_edge(CLK);
      if td_fsm_i = TD_FSM_IDLE then
@@ -581,14 +586,31 @@ begin
      end if;
    end process;  
 
+----------------------------------------------------
+-- Busy out option for synchronous japanese setup
+----------------------------------------------------
 --    proc_busyout : process begin
 --      wait until rising_edge(CLK);
 --      if ro_fsm_i = RO_FSM_WAIT_BECOME_IDLE and CTS_IPU_BUSY_IN = '0' and fifo_empty_i = '1' then
---        TRIGGER_BUSY_OUT <= '0';
+--        busy_out_i <= '0';
+--        if busy_out_i = '1' then
+--          busy_out_counter <= x"9";
+--        end if;  
 --      elsif  td_fsm_i = TD_FSM_SEND_TRIGGER then 
---        TRIGGER_BUSY_OUT <= '1';
+--        busy_out_i <= '1';
 --      end if;
+--      
+--      if busy_out_counter = 0 then
+--        busy_end_i <= '0';
+--      else
+--        busy_out_counter <= busy_out_counter - 1;
+--        busy_end_i <= '1';
+--      end if;  
 --    end process;  
+--    -- TRIGGER_BUSY_OUT <= busy_out_i;
+--    TRIGGER_BUSY_OUT  <= busy_end_i;
+---------------------------------------------------
+   
    
    
    read_out_proc: process(CLK) is