From: Jan Michel <j.michel@gsi.de>
Date: Wed, 28 Mar 2018 14:22:01 +0000 (+0200)
Subject: update media interface ports in TRB3 periph hub
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=85f7dc66c950d23fe85ed3ccdb6e3bfb4ce1ee0b;p=trb3.git

update media interface ports in TRB3 periph hub
---

diff --git a/hub/trb3_periph_hub.vhd b/hub/trb3_periph_hub.vhd
index a7a8e0b..19e615c 100644
--- a/hub/trb3_periph_hub.vhd
+++ b/hub/trb3_periph_hub.vhd
@@ -281,7 +281,7 @@ end generate;
 -- The TrbNet media interface (to other FPGA)
 ---------------------------------------------------------------------------
 gen_full_media : if SYNC_MODE = c_NO generate
-  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp_4
+  THE_MEDIA_UPLINK : entity work.trb_net16_med_ecp3_sfp_4
     generic map(
       REVERSE_ORDER => c_NO,              --order of ports
       FREQUENCY     => 200                --run on 200 MHz clock
@@ -381,7 +381,7 @@ gen_sync_media : if SYNC_MODE = c_YES generate
   med_stat_op(3*16+15 downto 3*16) <= x"0007";
   med_stat_op(5*16+15 downto 5*16) <= x"0007";  
   
-  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+  THE_MEDIA_UPLINK : entity work.trb_net16_med_ecp3_sfp
   generic map(
       SERDES_NUM  => 1,     --number of serdes in quad
       EXT_CLOCK   => c_NO,  --use internal clock
@@ -408,12 +408,12 @@ gen_sync_media : if SYNC_MODE = c_YES generate
       CLK_RX_HALF_OUT    => rx_clock_100,
       CLK_RX_FULL_OUT    => rx_clock_200,
       --SFP Connection
-      SD_RXD_P_IN        => SERDES_ADDON_RX(8),
-      SD_RXD_N_IN        => SERDES_ADDON_RX(9),
-      SD_TXD_P_OUT       => SERDES_ADDON_TX(8),
-      SD_TXD_N_OUT       => SERDES_ADDON_TX(9),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
+--       SD_RXD_P_IN        => SERDES_ADDON_RX(8),
+--       SD_RXD_N_IN        => SERDES_ADDON_RX(9),
+--       SD_TXD_P_OUT       => SERDES_ADDON_TX(8),
+--       SD_TXD_N_OUT       => SERDES_ADDON_TX(9),
+--       SD_REFCLK_P_IN     => open,
+--       SD_REFCLK_N_IN     => open,
       SD_PRSNT_N_IN      => FPGA5_COMM(0),
       SD_LOS_IN          => FPGA5_COMM(0),
       SD_TXDIS_OUT       => FPGA5_COMM(2),
@@ -432,7 +432,7 @@ gen_sync_media : if SYNC_MODE = c_YES generate
       );
 end generate;
       
-THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
+THE_MEDIA_DOWNLINK : entity work.trb_net16_med_ecp3_sfp_4
     generic map(
       REVERSE_ORDER => c_NO,              --order of ports
       FREQUENCY     => 200                --run on 200 MHz clock