From: Ingo Froehlich <ingo@nomail.fake>
Date: Thu, 8 Mar 2018 12:00:23 +0000 (+0100)
Subject: 16 bit flash, IF
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=86cbd3c99e0d7127db0bef39a0d5d99775d0bb3a;p=dirich.git

16 bit flash, IF
---

diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
index d570bd6..c68aaaa 100644
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@ -5,6 +5,7 @@
 #project files
 
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "workdir/version.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/sedcheck.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd"
@@ -12,7 +13,7 @@ add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
 add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
-add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v"
 
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
 add_file -vhdl -lib work "thresholds.vhd"
diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index a00dd8b..d06996f 100644
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -7,6 +7,7 @@ use machxo3lf.all;
 
 library work;
 use work.trb_net_std.all;
+use work.version.all;
 
 entity thresholds is
   port(
@@ -141,33 +142,31 @@ PROC_REGS : process begin
   
     if bus_read = '1' then
       bus_ready <= '1';
-      if (spi_addr >= x"10") and (spi_addr < X"20") then
+      if (spi_addr >= x"00") and (spi_addr < x"10") then
 	spi_tx_data <= ram_data(to_integer(unsigned(spi_addr(3 downto 0)))); -- Read RAM
-        --spi_tx_data <= "00000000" & spi_addr; 
       else
         case spi_addr is
-             when x"ee" => spi_tx_data <= sed_debug(15 downto 0);
-             when x"ef" => spi_tx_data <= sed_debug(31 downto 16);
-             when others => null;
+          when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));
+          when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));
+          when x"ee" => spi_tx_data <= sed_debug(15 downto 0);
+          when x"ef" => spi_tx_data <= sed_debug(31 downto 16);
+          when x"ff" => spi_tx_data <= x"0100"; --version number
+          when others => spi_tx_data <= x"0000";
         end case; 
       end if;
       
     elsif bus_write = '1' then
-      if (spi_addr >= x"00") and (spi_addr < x"10") then  -- write directly to PWM
-	  pwm_data  <= spi_rx_data;
-	  pwm_addr  <= spi_addr(4 downto 0);
-	  pwm_write <= '1';
-      elsif (spi_addr >= x"10") and (spi_addr <  x"20") then  -- write to RAM
+--      if (spi_addr >= x"00") and (spi_addr < x"10") then  -- write directly to PWM
+--	  pwm_data  <= spi_rx_data;
+--	  pwm_addr  <= spi_addr(4 downto 0);
+--	  pwm_write <= '1';
+      if (spi_addr >= x"00") and (spi_addr <  x"10") then  -- write to RAM
 	  ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data;
 	  pwm_data  <= spi_rx_data;
 	  pwm_addr  <= spi_addr(4 downto 0);
 	  pwm_write <= '1';
       else
           case spi_addr is
---	      when x"20" => flash_command <= '1'; --write to flash;
---			    flash_go      <= '1';
---	      when x"21" => flash_command <= '0'; --read from flash;
---			    flash_go      <= '1';
               when x"22" => compensate_i  <= signed(spi_rx_data(15 downto 0));--signed(uart_rx_data(15 downto 0);
               when x"ee" => controlsed_i  <= spi_rx_data(3 downto 0);
 	      when others => null;