From: Peter Lemmens Date: Wed, 4 Mar 2015 15:35:30 +0000 (+0100) Subject: Colab update: in soda_hub.vhd: tx_ref_clk was changed from rx_full_clk to clk_200_osc; X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=881ccb1329e0c20f6c9dbd018d6ec6fc490f2853;p=soda.git Colab update: in soda_hub.vhd: tx_ref_clk was changed from rx_full_clk to clk_200_osc; to be verified!! Syntax of lpf-files has changed, causing havoc. This has been addressed. Design is working again(like before) --- diff --git a/code/ip/serdes_sync_source_downstream.ipx b/code/ip/serdes_sync_source_downstream.ipx index 02ac8ed..f75e480 100644 --- a/code/ip/serdes_sync_source_downstream.ipx +++ b/code/ip/serdes_sync_source_downstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_sync_source_downstream.lpc b/code/ip/serdes_sync_source_downstream.lpc index d013d9e..fa9375f 100644 --- a/code/ip/serdes_sync_source_downstream.lpc +++ b/code/ip/serdes_sync_source_downstream.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PCS -CoreRevision=8.1 +CoreRevision=8.2 ModuleName=serdes_sync_source_downstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=01/30/2015 -Time=17:46:06 +Date=03/02/2015 +Time=17:24:29 [Parameters] Verilog=0 diff --git a/code/ip/serdes_sync_upstream.ipx b/code/ip/serdes_sync_upstream.ipx index 9823920..bf676e5 100644 --- a/code/ip/serdes_sync_upstream.ipx +++ b/code/ip/serdes_sync_upstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_sync_upstream.lpc b/code/ip/serdes_sync_upstream.lpc index 8daad48..edc2b42 100644 --- a/code/ip/serdes_sync_upstream.lpc +++ b/code/ip/serdes_sync_upstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.2 ModuleName=serdes_sync_upstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=12/03/2014 -Time=15:52:28 +Date=03/04/2015 +Time=13:04:49 [Parameters] Verilog=0 @@ -55,7 +55,7 @@ _tx_data_width0=8 _tx_data_width1=8 _tx_data_width2=8 _tx_data_width3=8 -_tx_fifo0=DISABLED +_tx_fifo0=ENABLED _tx_fifo1=ENABLED _tx_fifo2=ENABLED _tx_fifo3=DISABLED @@ -63,7 +63,7 @@ _tx_ficlk_rate0=200 _tx_ficlk_rate1=200 _tx_ficlk_rate2=200 _tx_ficlk_rate3=200 -_pll_rxsrc0=INTERNAL +_pll_rxsrc0=EXTERNAL _pll_rxsrc1=EXTERNAL _pll_rxsrc2=EXTERNAL _pll_rxsrc3=INTERNAL @@ -71,7 +71,7 @@ Multiplier0= Multiplier1= Multiplier2= Multiplier3= -_rx_datarange0=2 +_rx_datarange0=2.5 _rx_datarange1=2.5 _rx_datarange2=2.5 _rx_datarange3=2 @@ -83,7 +83,7 @@ _rx_data_rate0=FULL _rx_data_rate1=FULL _rx_data_rate2=FULL _rx_data_rate3=FULL -_rxrefclk_rate0=200 +_rxrefclk_rate0=250.0 _rxrefclk_rate1=250.0 _rxrefclk_rate2=250.0 _rxrefclk_rate3=200 @@ -91,11 +91,11 @@ _rx_data_width0=8 _rx_data_width1=8 _rx_data_width2=8 _rx_data_width3=8 -_rx_fifo0=DISABLED +_rx_fifo0=ENABLED _rx_fifo1=ENABLED _rx_fifo2=ENABLED _rx_fifo3=DISABLED -_rx_ficlk_rate0=200 +_rx_ficlk_rate0=250.0 _rx_ficlk_rate1=250.0 _rx_ficlk_rate2=250.0 _rx_ficlk_rate3=200 @@ -119,7 +119,7 @@ _rterm_rx0=50 _rterm_rx1=50 _rterm_rx2=50 _rterm_rx3=50 -_rx_dcc0=DC +_rx_dcc0=AC _rx_dcc1=AC _rx_dcc2=AC _rx_dcc3=DC @@ -190,10 +190,10 @@ _cc_match_mode0=1 _cc_match_mode1=1 _cc_match_mode2=1 _cc_match_mode3=1 -_k00=01 +_k00=00 _k01=00 _k02=00 -_k03=01 +_k03=00 _k10=00 _k11=00 _k12=00 @@ -206,10 +206,10 @@ _k30=01 _k31=01 _k32=01 _k33=01 -_byten00=00011100 +_byten00=00000000 _byten01=00000000 _byten02=00000000 -_byten03=00011100 +_byten03=00000000 _byten10=00000000 _byten11=00000000 _byten12=00000000 diff --git a/code/ip/serdes_sync_upstream.txt b/code/ip/serdes_sync_upstream.txt index a057cb3..9f2bf0d 100644 --- a/code/ip/serdes_sync_upstream.txt +++ b/code/ip/serdes_sync_upstream.txt @@ -44,7 +44,7 @@ CH3_COMMA_M "1111111100" CH3_RXWA "ENABLED" CH3_ILSM "ENABLED" CH3_CTC "DISABLED" -CH3_CC_MATCH4 "0100011100" +CH3_CC_MATCH4 "0000000000" CH3_CC_MATCH_MODE "1" CH3_CC_MIN_IPG "3" CCHMARK "9" diff --git a/code/ip/serdes_sync_upstream.vhd b/code/ip/serdes_sync_upstream.vhd index 9d08f56..3ceaa4f 100644 --- a/code/ip/serdes_sync_upstream.vhd +++ b/code/ip/serdes_sync_upstream.vhd @@ -19,7 +19,7 @@ GENERIC( PLL_SRC : String -- CONFIG_FILE : String := "serdes_sync_upstream.txt"; -- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_CORE"; +-- CH0_CDR_SRC : String := "REFCLK_EXT"; -- CH1_CDR_SRC : String := "REFCLK_EXT"; -- CH2_CDR_SRC : String := "REFCLK_EXT"; -- CH3_CDR_SRC : String := "REFCLK_CORE"; @@ -2105,19 +2105,19 @@ end component; attribute CH3_CDR_SRC: string; attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000"; attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200.000"; + attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200"; attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000"; attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100.000"; + attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index 623bcf2..291910a 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -81,8 +81,8 @@ architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is component DCS -- synthesis translate_off generic - ( -DCSMODE : string :=“POS” +( + DCSMODE : string :="POS" ); -- synthesis translate_on port ( diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index 410d609..023f1dc 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -82,9 +82,8 @@ attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off"; component DCS -- synthesis translate_off -generic - ( -DCSMODE : string :=“POS” +generic( +DSCMODE : string :="POS" ); -- synthesis translate_on port ( @@ -270,7 +269,7 @@ THE_SERDES : entity work.serdes_sync_upstream SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => rx_full_clk, + fpga_txrefclk => clk_200_osc, --rx_full_clk, tx_serdes_rst_c => tx_serdes_rst, tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, diff --git a/code/soda_components.vhd b/code/soda_components.vhd index 1a61970..3b4a267 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -128,8 +128,9 @@ package soda_components is SYSCLK : in std_logic; -- fabric clock SODACLK : in std_logic; -- clock for data to serdes RESET : in std_logic; -- synchronous reset - --Internal Connection + SODA_BURST_PULSE_IN : in std_logic := '0'; -- + SODA_CYCLE_IN : in std_logic := '0'; -- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); RX_DLM_IN : in std_logic; @@ -146,7 +147,7 @@ package soda_components is SODA_WRITE_IN : in std_logic := '0'; SODA_ACK_OUT : out std_logic := '0'; LEDS_OUT : out std_logic_vector(3 downto 0) - ); + ); end component; component soda_4source is diff --git a/code/soda_only_ecp3_sfp_sync_up.vhd b/code/soda_only_ecp3_sfp_sync_up.vhd index 40656a6..03ef5be 100644 --- a/code/soda_only_ecp3_sfp_sync_up.vhd +++ b/code/soda_only_ecp3_sfp_sync_up.vhd @@ -69,8 +69,8 @@ attribute syn_sharing of soda_only_ecp3_sfp_sync_up_arch : architecture is "off" component DCS -- synthesis translate_off generic - ( -DCSMODE : string :=“POS” +( + DCSMODE : string :="POS" ); -- synthesis translate_on port ( @@ -540,4 +540,4 @@ sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL! --STAT_OP(5) <= request_retr_i; --STAT_OP(4) <= start_retr_i; --STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; -end soda_only_ecp3_sfp_sync_up_arch; \ No newline at end of file +end soda_only_ecp3_sfp_sync_up_arch; diff --git a/code/soda_source.vhd b/code/soda_source.vhd index 4f83cdc..6c5a7b6 100644 --- a/code/soda_source.vhd +++ b/code/soda_source.vhd @@ -14,8 +14,9 @@ entity soda_source is SYSCLK : in std_logic; -- fabric clock SODACLK : in std_logic; -- clock for data to serdes RESET : in std_logic; -- synchronous reset - --Internal Connection + SODA_BURST_PULSE_IN : in std_logic := '0'; -- + SODA_CYCLE_IN : in std_logic := '0'; -- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); RX_DLM_IN : in std_logic; @@ -31,7 +32,7 @@ entity soda_source is SODA_WRITE_IN : in std_logic := '0'; SODA_ACK_OUT : out std_logic := '0'; LEDS_OUT : out std_logic_vector(3 downto 0) - ); + ); end soda_source; architecture Behavioral of soda_source is @@ -96,20 +97,22 @@ begin packet_builder : soda_packet_builder port map( - SODACLK => SODACLK, - RESET => RESET, + SODACLK => SODACLK, + RESET => RESET, --Internal Connection - LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL! - SODA_CMD_STROBE_IN => soda_send_cmd_S, - START_OF_SUPERBURST => start_of_superburst_S, - SUPER_BURST_NR_IN => super_burst_nr_S, - SODA_CMD_WORD_IN => soda_cmd_word_S, - EXPECTED_REPLY_OUT => expected_reply_S, - TIME_CAL_OUT => start_calibration_S, - TX_DLM_PREVIEW_OUT => TX_DLM_PREVIEW_OUT, - TX_DLM_OUT => TX_DLM_OUT, - TX_DLM_WORD_OUT => TX_DLM_WORD_OUT - ); + LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL! + SODA_CYCLE_IN => SODA_CYCLE_IN, + + SODA_CMD_STROBE_IN => soda_send_cmd_S, + START_OF_SUPERBURST => start_of_superburst_S, + SUPER_BURST_NR_IN => super_burst_nr_S, + SODA_CMD_WORD_IN => soda_cmd_word_S, + EXPECTED_REPLY_OUT => expected_reply_S, + TIME_CAL_OUT => start_calibration_S, + TX_DLM_PREVIEW_OUT => TX_DLM_PREVIEW_OUT, + TX_DLM_OUT => TX_DLM_OUT, + TX_DLM_WORD_OUT => TX_DLM_WORD_OUT + ); src_reply_handler : soda_reply_handler port map( diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index 2f0bd3a..b718686 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -119,21 +119,20 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal txdn_half_clk : t_HUB_BIT; signal txdn_full_clk : t_HUB_BIT; --- signal clk_tdc : std_logic; - signal time_counter, time_counter2 : unsigned(31 downto 0); + signal time_counter : unsigned(31 downto 0); --Media Interface - signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); - signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); - signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0'); - signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0'); - signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); - signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0'); - signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); - signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); - signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); - signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0'); - signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); - signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); + signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); + signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); + signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0'); + signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0'); + signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); + signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0'); + signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); + signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); + signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); + signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0'); + signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); + signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0'); --Slow Control channel signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); @@ -231,10 +230,10 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal link_debug_in_S : std_logic_vector(31 downto 0); signal general_reset_i : std_logic := '1'; - signal soda_counter_i : unsigned(3 downto 0); +-- signal soda_counter_i : unsigned(31 downto 0); - attribute syn_keep of soda_counter_i : signal is true; +-- attribute syn_keep of soda_counter_i : signal is true; -- fix signal names for constraining attribute syn_preserve of clk_100_osc : signal is true; attribute syn_keep of clk_100_osc : signal is true; @@ -770,17 +769,38 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_ORANGE <= SFP_LOS(3); --med_stat_op(8); - LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10); - LED_GREEN <= med_stat_op(12); --tx_pll_lol - LED_RED <= med_stat_op(11); --rx_cdr_lol +-- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8); +-- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10); +-- LED_GREEN <= med_stat_op(12); --tx_pll_lol +-- LED_RED <= med_stat_op(11); --rx_cdr_lol + LED_ORANGE <= SFP_LOS(1); --'1' when (time_counter(26)='0') else '0'; + LED_YELLOW <= SFP_LOS(2); --'1' when (time_counter(26)='0') else '0'; + LED_GREEN <= SFP_LOS(3); --time_counter(26); + LED_RED <= SFP_LOS(4); --time_counter(26); - LED_RX(1) <= med_stat_op(8); - LED_RX(2) <= med_stat_op(10); - LED_RX(3) <= med_stat_op(9); - LED_RX(4) <= med_stat_op(6); - LED_RX(5) <= '0'; - LED_RX(6) <= '1'; +--------------------------------------------------------------------------- +-- GREEN LED under sfp +--------------------------------------------------------------------------- + LED_LINKOK(1) <= SFP_LOS(1); + LED_LINKOK(2) <= SFP_LOS(2); + LED_LINKOK(3) <= SFP_LOS(3); + LED_LINKOK(4) <= SFP_LOS(4); + LED_LINKOK(5) <= SFP_LOS(5); + LED_LINKOK(6) <= SFP_LOS(6); + + LED_RX(1) <= '1' when (med_stat_op(10)='0') else '0'; -- rx_allow + LED_RX(2) <= '1'; + LED_RX(3) <= '1'; + LED_RX(4) <= '1'; + LED_RX(5) <= '1'; + LED_RX(6) <= '1'; + + LED_TX(1) <= '1' when (med_stat_op(9)='0') else '0'; -- tx_allow + LED_TX(2) <= '1'; + LED_TX(3) <= '1'; + LED_TX(4) <= '1'; + LED_TX(5) <= '1'; + LED_TX(6) <= '1'; --------------------------------------------------------------------------- -- DEBUG @@ -790,19 +810,18 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- --- clock_counter_proc : process(rxup_half_clk, --) --- begin --- if rising_edge(rxup_half_clk, --) then --- time_counter <= time_counter + 1; --- end if; --- end process; --- process(rxup_full_clk) --clk_soda_i) --- begin --- if rising_edge(rxup_full_clk) then --- soda_counter_i <= soda_counter_i+1; --- end if; --- end process; + + blink : process (clk_200_osc) + begin + if rising_edge(clk_200_osc) then + if (time_counter = x"FFFFFFFF") then + time_counter <= x"00000000"; + else + time_counter <= time_counter + 1; + end if; + end if; + end process; end trb3_periph_sodahub_arch; \ No newline at end of file diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd index 450bcca..e97cf83 100644 --- a/code/trb3_periph_sodasource.vhd +++ b/code/trb3_periph_sodasource.vhd @@ -25,16 +25,6 @@ entity trb3_periph_sodasource is CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! - --Trigger - --TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out - --TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - --Serdes Clocks - do not use - --CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible - --CLK_SERDES_INT_RIGHT_P : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems - --CLK_SERDES_INT_RIGHT_N : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems - -- PCSA_REFCLKP : in std_logic; -- PL! external refclock straight into serdes - -- PCSA_REFCLKN : in std_logic; -- PL! external refclock straight into serdes - --serdes I/O - connect as you like, no real use SERDES_ADDON_TX : out std_logic_vector(15 downto 0); SERDES_ADDON_RX : in std_logic_vector(15 downto 0); @@ -51,12 +41,7 @@ entity trb3_periph_sodasource is SFP_MOD0 : in std_logic_vector(6 downto 1); SFP_TXDIS : out std_logic_vector(6 downto 1); SFP_LOS : in std_logic_vector(6 downto 1); - --SFP_MOD1 : inout std_logic_vector(6 downto 1); - --SFP_MOD2 : inout std_logic_vector(6 downto 1); - --SFP_RATESEL : out std_logic_vector(6 downto 1); - --SFP_TXFAULT : in std_logic_vector(6 downto 1); - - --Flash ROM & Reboot + --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; FLASH_DIN : out std_logic; @@ -224,6 +209,7 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is --SODA signal SOB_S : std_logic := '0'; + signal soda_40mhz_cycle_S : std_logic := '0'; -- fix signal names for constraining attribute syn_preserve of soda_rx_clock_full : signal is true; attribute syn_keep of soda_rx_clock_full : signal is true; @@ -241,6 +227,8 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is attribute syn_keep of tx_dlm_i : signal is true; attribute syn_preserve of rx_dlm_i : signal is true; attribute syn_keep of rx_dlm_i : signal is true; + attribute syn_preserve of soda_40mhz_cycle_S : signal is true; + attribute syn_keep of soda_40mhz_cycle_S : signal is true; begin @@ -281,24 +269,6 @@ gen_200_PLL : if USE_125_MHZ = c_NO generate ); end generate; -gen_125 : if USE_125_MHZ = c_YES generate - clk_100_osc <= CLK_GPLL_LEFT; - clk_200_osc <= CLK_GPLL_LEFT; -end generate; - ---gen_sync_clocks : if SYNC_MODE = c_YES generate --- clk_sys_i <= soda_tx_clock_half; --- clk_200_i <= soda_tx_clock_full; --- clk_100_osc <= soda_tx_clock_half; --- clk_200_osc <= soda_tx_clock_full; ---end generate; - ---gen_local_clocks : if SYNC_MODE = c_NO generate --- clk_sys_i <= clk_100_osc; --- clk_200_ip <= clk_200_osc; ---end generate; - - --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) --------------------------------------------------------------------------- @@ -545,81 +515,86 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down IS_SYNC_SLAVE => c_NO ) port map( - OSCCLK => clk_200_osc, - SYSCLK => clk_100_osc, - RESET => reset_i, - CLEAR => clear_i, + OSCCLK => clk_200_osc, + SYSCLK => clk_100_osc, + RESET => reset_i, + CLEAR => clear_i, --Internal Connection for TrbNet data -> not used a.t.m. - MED_DATA_IN => med_data_out(31 downto 16), - MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3), - MED_DATAREADY_IN => med_dataready_out(1), - MED_READ_OUT => med_read_in(1), - MED_DATA_OUT => med_data_in(31 downto 16), - MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3), - MED_DATAREADY_OUT => med_dataready_in(1), - MED_READ_IN => med_read_out(1), - RX_HALF_CLK_OUT => soda_rx_clock_half, - RX_FULL_CLK_OUT => soda_rx_clock_full, - TX_HALF_CLK_OUT => soda_tx_clock_half, - TX_FULL_CLK_OUT => soda_tx_clock_full, - - RX_DLM => rx_dlm_i, - RX_DLM_WORD => rx_dlm_word, - TX_DLM => tx_dlm_i, - TX_DLM_WORD => tx_dlm_word, + MED_DATA_IN => med_data_out(31 downto 16), + MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3), + MED_DATAREADY_IN => med_dataready_out(1), + MED_READ_OUT => med_read_in(1), + MED_DATA_OUT => med_data_in(31 downto 16), + MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3), + MED_DATAREADY_OUT => med_dataready_in(1), + MED_READ_IN => med_read_out(1), + RX_HALF_CLK_OUT => soda_rx_clock_half, + RX_FULL_CLK_OUT => soda_rx_clock_full, + TX_HALF_CLK_OUT => soda_tx_clock_half, + TX_FULL_CLK_OUT => soda_tx_clock_full, + + RX_DLM => rx_dlm_i, + RX_DLM_WORD => rx_dlm_word, + TX_DLM => tx_dlm_i, + TX_DLM_WORD => tx_dlm_word, TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL! LINK_PHASE_OUT => link_phase_S, --PL! --SFP Connection - SD_RXD_P_IN => SERDES_ADDON_RX(0), - SD_RXD_N_IN => SERDES_ADDON_RX(1), - SD_TXD_P_OUT => SERDES_ADDON_TX(0), - SD_TXD_N_OUT => SERDES_ADDON_TX(1), - SD_REFCLK_P_IN => '0', - SD_REFCLK_N_IN => '0', - SD_PRSNT_N_IN => SFP_MOD0(1), - SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1), - - SCI_DATA_IN => sci2_data_in, - SCI_DATA_OUT => sci2_data_out, - SCI_ADDR => sci2_addr, - SCI_READ => sci2_read, - SCI_WRITE => sci2_write, - SCI_ACK => sci2_ack, - SCI_NACK => sci2_nack, + SD_RXD_P_IN => SERDES_ADDON_RX(0), + SD_RXD_N_IN => SERDES_ADDON_RX(1), + SD_TXD_P_OUT => SERDES_ADDON_TX(0), + SD_TXD_N_OUT => SERDES_ADDON_TX(1), + SD_REFCLK_P_IN => '0', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => SFP_MOD0(1), + SD_LOS_IN => SFP_LOS(1), + SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1), + + SCI_DATA_IN => sci2_data_in, + SCI_DATA_OUT => sci2_data_out, + SCI_ADDR => sci2_addr, + SCI_READ => sci2_read, + SCI_WRITE => sci2_write, + SCI_ACK => sci2_ack, + SCI_NACK => sci2_nack, -- Status and control port - STAT_OP => med_stat_op(31 downto 16), - CTRL_OP => med_ctrl_op(31 downto 16), - STAT_DEBUG => open, - CTRL_DEBUG => (others => '0') + STAT_OP => med_stat_op(31 downto 16), + CTRL_OP => med_ctrl_op(31 downto 16), + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') ); SFP_TXDIS(1) <= sfp_txdis_S(1); --------------------------------------------------------------------------- --- The Soda Central +-- Burst- and 40MHz cycle generator --------------------------------------------------------------------------- -THE_SOB_SOURCE : soda_start_of_burst_faker +THE_SOB_SOURCE : soda_start_of_burst_control generic map( - CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns + CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns + CYCLE_PERIOD => cSODA_CYCLE_PERIOD, -- cycle-period in ns BURST_PERIOD => cBURST_PERIOD -- burst-period in ns ) port map( - SYSCLK => soda_tx_clock_half, --clk_100_osc, PL! 30062014 + SODA_CLK => clk_200_osc, RESET => reset_i, - SODA_BURST_PULSE_OUT => SOB_S - ); - - + SODA_BURST_PULSE_OUT => SOB_S, + SODA_40MHZ_CYCLE_OUT => soda_40mhz_cycle_S + ); + +--------------------------------------------------------------------------- +-- The Soda Central +--------------------------------------------------------------------------- THE_SODA_SOURCE : soda_source port map( SYSCLK => soda_tx_clock_half, --clk_100_osc, --clk_sys_i, PL! 30062014 SODACLK => soda_tx_clock_full, --clk_200_osc, -- PL! 30062014 RESET => reset_i, - --Internal Connection + SODA_BURST_PULSE_IN => SOB_S, + SODA_CYCLE_IN => soda_40mhz_cycle_S, RX_DLM_WORD_IN => rx_dlm_word, RX_DLM_IN => rx_dlm_i, @@ -639,10 +614,39 @@ THE_SODA_SOURCE : soda_source --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_ORANGE <= SFP_LOS(1); --med_stat_op(8); - LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10); - LED_GREEN <= med_stat_op(12); --tx_pll_lol - LED_RED <= med_stat_op(11); --rx_cdr_lol +-- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8); +-- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10); +-- LED_GREEN <= med_stat_op(12); --tx_pll_lol +-- LED_RED <= med_stat_op(11); --rx_cdr_lol + LED_ORANGE <= '1' when (med_stat_op(26)='0') else '0'; + LED_YELLOW <= '1' when (med_stat_op(26)='0') else '0'; + LED_GREEN <= med_stat_op(11); + LED_RED <= med_stat_op(10); + + +--------------------------------------------------------------------------- +-- GREEN LED under sfp +--------------------------------------------------------------------------- + LED_LINKOK(1) <= SFP_LOS(1); --med_stat_op(8); + LED_LINKOK(2) <= SFP_LOS(2); + LED_LINKOK(3) <= SFP_LOS(3); + LED_LINKOK(4) <= SFP_LOS(4); + LED_LINKOK(5) <= SFP_LOS(5); + LED_LINKOK(6) <= SFP_LOS(6); + + LED_RX(1) <= '1' when (med_stat_op(10)='0') else '0'; -- rx_allow + LED_RX(2) <= '1'; + LED_RX(3) <= '1'; + LED_RX(4) <= '1'; + LED_RX(5) <= '1'; + LED_RX(6) <= '1'; + + LED_TX(1) <= '1' when (med_stat_op(9)='0') else '0'; -- tx_allow + LED_TX(2) <= '1'; + LED_TX(3) <= '1'; + LED_TX(4) <= '1'; + LED_TX(5) <= '1'; + LED_TX(6) <= '1'; --------------------------------------------------------------------------- -- Test Connector @@ -651,13 +655,16 @@ THE_SODA_SOURCE : soda_source --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- -process - begin - wait until rising_edge(soda_tx_clock_half); --clk_100_osc); PL! 30062014 - time_counter <= time_counter + 1; -end process; - - + blink : process (clk_100_osc) + begin + if rising_edge(clk_100_osc) then + if (time_counter = x"FFFFFFFF") then + time_counter <= x"00000000"; + else + time_counter <= time_counter + 1; + end if; + end if; + end process; end trb3_periph_sodasource_arch; \ No newline at end of file diff --git a/ctsh.lpf b/ctsh.lpf index a9e079d..0cadf6a 100644 --- a/ctsh.lpf +++ b/ctsh.lpf @@ -2,6 +2,7 @@ rvl_alias "soda_rxup_full_clk" "trb_media_and_soda_sync_uplink/sync_rx_full_clk_ BLOCK RESETPATHS; BLOCK ASYNCPATHS; BLOCK RD_DURING_WR_PATHS ; +BLOCK JTAGPATHS ; ################################################################# # Clock I/O ################################################################# diff --git a/soda_hub.ldf b/soda_hub.ldf index d0a5205..e773792 100644 --- a/soda_hub.ldf +++ b/soda_hub.ldf @@ -335,15 +335,15 @@ - - - + + + diff --git a/soda_hub_frankfurt.lpf b/soda_hub_frankfurt.lpf index 7974e58..6f8c310 100644 --- a/soda_hub_frankfurt.lpf +++ b/soda_hub_frankfurt.lpf @@ -130,8 +130,7 @@ LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186 DEFINE PORT GROUP "SFP_group" "SFP*" ; IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; - -################################################################# +################################################################# # Additional Lines to AddOn ################################################################# #Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 @@ -142,8 +141,7 @@ IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; #LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 #LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 #LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 - +#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 ################################################################# # Flash ROM and Reboot ################################################################# @@ -155,7 +153,6 @@ DEFINE PORT GROUP "FLASH_group" "FLASH*" ; IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; LOCATE COMP "PROGRAMN" SITE "B11" ; IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; - ################################################################# # Misc ################################################################# @@ -168,8 +165,7 @@ IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; #terminated differential pair to pads LOCATE COMP "SUPPL" SITE "C14" ; -#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; - +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25; ################################################################# # LED ################################################################# @@ -179,8 +175,6 @@ LOCATE COMP "LED_RED" SITE "A15" ; LOCATE COMP "LED_YELLOW" SITE "A16" ; DEFINE PORT GROUP "LED_group" "LED*" ; IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; - - ################################################################# #GSR_NET NET "GSR_N"; ################################################################# diff --git a/soda_hub_groningen.lpf b/soda_hub_groningen.lpf index 8191b20..4147b84 100644 --- a/soda_hub_groningen.lpf +++ b/soda_hub_groningen.lpf @@ -1,20 +1,13 @@ -rvl_alias "rxup_full_clk" "rxup_full_clk"; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; -BLOCK JTAGPATHS ; -################################################################# -# Basic Settings -################################################################# -SYSCONFIG MCCLK_FREQ = 20; -# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; -################################################################# -# Clock I/O -################################################################# -LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; -LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; +rvl_alias "rxup_full_clk" "rxup_full_clk"; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; +BLOCK JTAGPATHS ; +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; +LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ; LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY??? LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; #LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; @@ -23,196 +16,196 @@ LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; #LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; #LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL! DEFINE PORT GROUP "CLK_group" "*CLK*" ; -IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; -################################################################# -# To central FPGA -################################################################# -LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ; -LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ; -LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ; -LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ; -LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ; -LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ; -LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ; -LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ; -LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ; -LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ; -LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ; -LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ; -DEFINE PORT GROUP "FPGA_group" "FPGA*" ; -IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -LOCATE COMP "TEST_LINE[0]" SITE "A5" ; -LOCATE COMP "TEST_LINE[1]" SITE "A6" ; -LOCATE COMP "TEST_LINE[2]" SITE "G8" ; -LOCATE COMP "TEST_LINE[3]" SITE "F9" ; -LOCATE COMP "TEST_LINE[4]" SITE "D9" ; -LOCATE COMP "TEST_LINE[5]" SITE "D10" ; -LOCATE COMP "TEST_LINE[6]" SITE "F10" ; -LOCATE COMP "TEST_LINE[7]" SITE "E10" ; -LOCATE COMP "TEST_LINE[8]" SITE "A8" ; -LOCATE COMP "TEST_LINE[9]" SITE "B8" ; -LOCATE COMP "TEST_LINE[10]" SITE "G10" ; -LOCATE COMP "TEST_LINE[11]" SITE "G9" ; -LOCATE COMP "TEST_LINE[12]" SITE "C9" ; -LOCATE COMP "TEST_LINE[13]" SITE "C10" ; -LOCATE COMP "TEST_LINE[14]" SITE "H10" ; -LOCATE COMP "TEST_LINE[15]" SITE "H11" ; -DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; -################################################################# -# Connection to AddOn -################################################################# -LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1 -LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3 -LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5 -LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7 +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; +################################################################# +# To central FPGA +################################################################# +LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ; +LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ; +LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ; +LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ; +LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ; +LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ; +LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ; +LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ; +LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ; +LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ; +LOCATE COMP "FPGA5_COMM_10" SITE "V10" ; +LOCATE COMP "FPGA5_COMM_11" SITE "W10" ; +DEFINE PORT GROUP "FPGA_group" "FPGA*" ; +IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +LOCATE COMP "TEST_LINE_0" SITE "A5" ; +LOCATE COMP "TEST_LINE_1" SITE "A6" ; +LOCATE COMP "TEST_LINE_2" SITE "G8" ; +LOCATE COMP "TEST_LINE_3" SITE "F9" ; +LOCATE COMP "TEST_LINE_4" SITE "D9" ; +LOCATE COMP "TEST_LINE_5" SITE "D10" ; +LOCATE COMP "TEST_LINE_6" SITE "F10" ; +LOCATE COMP "TEST_LINE_7" SITE "E10" ; +LOCATE COMP "TEST_LINE_8" SITE "A8" ; +LOCATE COMP "TEST_LINE_9" SITE "B8" ; +LOCATE COMP "TEST_LINE_10" SITE "G10" ; +LOCATE COMP "TEST_LINE_11" SITE "G9" ; +LOCATE COMP "TEST_LINE_12" SITE "C9" ; +LOCATE COMP "TEST_LINE_13" SITE "C10" ; +LOCATE COMP "TEST_LINE_14" SITE "H10" ; +LOCATE COMP "TEST_LINE_15" SITE "H11" ; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ; + +################################################################# +# Connection to AddOn +################################################################# +LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0 #1 +LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1 #3 +LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2 #5 +LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3 #7 #LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9 #LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11 #LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13 -LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15 -LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17 +LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C #15 +LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6 #17 #LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19 -LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21 -LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23 -LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25 -LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27 +LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8 #21 +LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9 #23 +LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0 #25 +LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1 #27 #LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29 #LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31 #LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33 -LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35 -LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 +LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5 #35 +LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2 #LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 -LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2 -LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4 -LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6 -LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8 +LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0 #2 +LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1 #4 +LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2 #6 +LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3 #8 #LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10 #LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12 #LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 -LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 -LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18 +LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3 +LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6 #18 #LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20 -LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22 -LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24 -LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26 -LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28 +LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8 #22 +LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9 #24 +LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0 #26 +LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1 #28 #LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30 #LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32 #LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34 -LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36 -LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38 +LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5 #36 +LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T #38 #LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40 -LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169 -LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171 -LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173 -LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175 +LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0 #169 +LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1 #171 +LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2 #173 +LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3 #175 #LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177 #LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179 #LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181 -LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183 -LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185 +LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C #183 +LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6 #185 #LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187 -LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170 -LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172 -LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174 -LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176 +LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0 #170 +LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1 #172 +LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2 #174 +LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3 #176 #LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178 #LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180 #LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182 -LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184 -LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186 +LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C #184 +LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6 #186 #LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188 -DEFINE PORT GROUP "SFP_group" "SFP*" ; -IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; -################################################################# -# Additional Lines to AddOn -################################################################# -#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 -#all lines are input only -#line 4/5 go to PLL input -#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 -#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 -#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 -#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 -#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 -################################################################# -# Flash ROM and Reboot -################################################################# -LOCATE COMP "FLASH_CLK" SITE "B12" ; -LOCATE COMP "FLASH_CS" SITE "E11" ; -LOCATE COMP "FLASH_DIN" SITE "E12" ; -LOCATE COMP "FLASH_DOUT" SITE "A12" ; -DEFINE PORT GROUP "FLASH_group" "FLASH*" ; -IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; -LOCATE COMP "PROGRAMN" SITE "B11" ; -IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -################################################################# -# Misc -################################################################# -LOCATE COMP "TEMPSENS" SITE "A13" ; -IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; -#coding of FPGA number -LOCATE COMP "CODE_LINE[1]" SITE "AA20" ; -LOCATE COMP "CODE_LINE[0]" SITE "Y21" ; -IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ; -#terminated differential pair to pads -LOCATE COMP "SUPPL" SITE "C14" ; -#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; -################################################################# -# LED -################################################################# -LOCATE COMP "LED_GREEN" SITE "F12" ; -LOCATE COMP "LED_ORANGE" SITE "G13" ; -LOCATE COMP "LED_RED" SITE "A15" ; -LOCATE COMP "LED_YELLOW" SITE "A16" ; -DEFINE PORT GROUP "LED_group" "LED*" ; -IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; - - -################################################################# -#GSR_NET NET "GSR_N"; -################################################################# -# Locate Serdes and media interfaces -################################################################# -LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; -MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; -MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; -#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only -MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; -MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; +################################################################# +# Additional Lines to AddOn +################################################################# +#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 +#all lines are input only +#line 4/5 go to PLL input +#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 +#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "B12" ; +LOCATE COMP "FLASH_CS" SITE "E11" ; +LOCATE COMP "FLASH_DIN" SITE "E12" ; +LOCATE COMP "FLASH_DOUT" SITE "A12" ; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ; +LOCATE COMP "PROGRAMN" SITE "B11" ; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13" ; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20" ; +LOCATE COMP "CODE_LINE_0" SITE "Y21" ; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; +#terminated differential pair to pads +LOCATE COMP "SUPPL" SITE "C14" ; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25; +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12" ; +LOCATE COMP "LED_ORANGE" SITE "G13" ; +LOCATE COMP "LED_RED" SITE "A15" ; +LOCATE COMP "LED_YELLOW" SITE "A16" ; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ; +################################################################# +#GSR_NET NET "GSR_N"; +################################################################# +# Locate Serdes and media interfaces +################################################################# +LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ; +#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only +MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; +MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ; #MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only #MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; -MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ; - -BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ; -BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*"; -BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*"; - +MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; +MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ; + +BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ; +BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*"; +BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*"; + #UGROUP "SPIlogic" BBOX 20 20 # BLKNAME THE_SPI_RELOAD; #LOCATE UGROUP "SPIlogic" SITE "R10C150D" ; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[0]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[1]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[2]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[3]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[0]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[1]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[2]"; -PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[3]"; - -## IOBUF ALLPORTS ; -USE PRIMARY NET "clk_200_osc" ; -USE PRIMARY NET "clk_100_osc" ; -USE PRIMARY NET "rxup_full_clk" ; -FREQUENCY NET "clk_200_osc" 200.000000 MHz ; -FREQUENCY NET "clk_100_osc" 100.000000 MHz ; -FREQUENCY NET "rxup_full_clk" 200.000000 MHz ; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_0"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_1"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_2"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_3"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_0"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_1"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_2"; +PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_3"; + +## IOBUF ALLPORTS ; +USE PRIMARY NET "clk_200_osc" ; +USE PRIMARY NET "clk_100_osc" ; +FREQUENCY NET "clk_200_osc" 200.000000 MHz ; +FREQUENCY NET "clk_100_osc" 100.000000 MHz ; +FREQUENCY NET "rxup_full_clk" 200.000000 MHz ; diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl index af88054..c6f73dc 100644 --- a/soda_hub_probe.rvl +++ b/soda_hub_probe.rvl @@ -1,25 +1,19 @@ - + - + + - - - - - - - - + @@ -30,7 +24,24 @@ - + + + + + + + + + + + + + + + + + + @@ -41,195 +52,112 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + - diff --git a/soda_source.ldf b/soda_source.ldf index 0b067a1..d78233a 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -17,6 +17,12 @@ + + + + + + @@ -26,9 +32,6 @@ - - - @@ -320,9 +323,6 @@ - - - diff --git a/soda_source.lpf b/soda_source.lpf index a6527e4..b0f3552 100644 --- a/soda_source.lpf +++ b/soda_source.lpf @@ -1,16 +1,9 @@ -rvl_alias "clk_raw_internal" "clk_raw_internal"; +rvl_alias "clk_100_osc" "clk_100_osc"; RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; ################################################################# -# Basic Settings -################################################################# -# SYSCONFIG MCCLK_FREQ = 2.5; -# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; -################################################################# # Clock I/O ################################################################# LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ; @@ -25,14 +18,6 @@ LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ; DEFINE PORT GROUP "CLK_group" "*CLK*" ; IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ; ################################################################# -# Trigger I/O -################################################################# -#Trigger from fan-out -#LOCATE COMP "TRIGGER_LEFT" SITE "V3"; -#LOCATE COMP "TRIGGER_RIGHT" SITE "N24"; -#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; -#IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ; -################################################################# # To central FPGA ################################################################# LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ; @@ -184,13 +169,6 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# SYSCONFIG MCCLK_FREQ=20 ; -# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; -################################################################# -# Reset Nets -################################################################# -#GSR_NET NET "GSR_N"; ################################################################# # Locate Serdes and media interfaces ################################################################# @@ -205,7 +183,6 @@ LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ; REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE; LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ; LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ; - #LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ; #LOCATE UGROUP "THE_SYNC_LINK/media_downlink_group" REGION "MEDIA_DOWNLINK_REGION" ; #USE SECONDARY NET "THE_MEDIA_UPLINK/rx_clock_half_c" "MEDIA_DOWNLINK_REGION" ; @@ -214,18 +191,10 @@ MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ; MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ; MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ; MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; +MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; BLOCK JTAGPATHS ; ## IOBUF ALLPORTS ; #USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; #USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ; -#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ; -#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ; -#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" 200.000000 MHz ; -#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" 100.000000 MHz ; -#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" ; -#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" ; -#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" ; -#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" ; -USE PRIMARY NET "THE_SYNC_LINK/CLK_RX_FULL_OUT_c" ; -USE PRIMARY NET "clk_sys_internal_c" ; -MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ; +FREQUENCY NET "clk_200_osc" 200.000000 MHz ; +FREQUENCY NET "clk_100_osc" 100.000000 MHz ; diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl index 177026e..afd1dc8 100644 --- a/soda_source_probe.rvl +++ b/soda_source_probe.rvl @@ -1,9 +1,9 @@ - + - + - + @@ -12,136 +12,125 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + - - - - - - - - - + + + + + + + + + + + - - - - - - - - - - - + + - - - - - - - - - + + + + + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - + + + - diff --git a/trb3_soda_hub.xcf b/trb3_soda_hub.xcf index 7d73139..4f73858 100644 --- a/trb3_soda_hub.xcf +++ b/trb3_soda_hub.xcf @@ -1,6 +1,6 @@ - + JTAG @@ -45,8 +45,8 @@ 1 0 - /local/lemmens/lattice/soda/trb3_periph_sodahub_20150120.bit - 01/20/15 10:28:57 + /local/lemmens/lattice/soda/trb3_periph_sodahub_20150304.bit + 03/04/15 14:53:50 Fast Program - + 4 Lattice LatticeECP3 @@ -103,6 +103,7 @@ /local/lemmens/lattice/soda/trb3_periph_sodaclient_20150113.bit 01/13/15 10:01:17 + N/A Fast Program - + 5 Lattice LatticeECP3 @@ -131,8 +132,9 @@ 1 0 - /local/lemmens/lattice/soda/trb3_periph_sodasource_20141126.bit - 11/25/14 14:12:00 + /local/lemmens/lattice/soda/trb3_periph_sodasource_20150303.bit + 03/03/15 17:13:40 + N/A Fast Program - + 6 Lattice ispCLOCK @@ -192,13 +194,19 @@ 1 0 + /local/lemmens/lattice/trb3/base/clockmanager/CM2.jed + 04/10/13 09:35:41 + 0x18FB Erase,Program,Verify