From: Adrian Weber Date: Tue, 12 Jan 2021 16:25:55 +0000 (+0100) Subject: change of the calibration clock to a derived clock from the recovered clock via a... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=89cb26cd5ca83c847ce126d3f5933a74aa4933bc;p=dirich.git change of the calibration clock to a derived clock from the recovered clock via a 240->50 PLL --- diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj index 32fc35f..a8a7b83 100644 --- a/combiner_cts/combiner.prj +++ b/combiner_cts/combiner.prj @@ -260,6 +260,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in240_out50.vhd" #TDC Calibration add_file -vhdl -lib work "./code_EBR/Calibration.vhd" diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd index ca13409..e83fb58 100644 --- a/combiner_cts/combiner.vhd +++ b/combiner_cts/combiner.vhd @@ -252,6 +252,8 @@ architecture arch of combiner is signal reset_via_cri_long, reset_via_cri_timer, last_reset_via_cri_long, make_reset : std_logic; signal reset_via_cri : std_logic := '0'; signal last_cri_resetPulse : std_logic; + + signal clk_cal : std_logic; attribute syn_keep of bus_mbs_rx : signal is true; attribute syn_preserve of bus_mbs_rx : signal is true; @@ -356,7 +358,18 @@ THE_CLOCK_RESET : entity work.clock_reset_handler_240 end if; last_reset_via_cri_long <= reset_via_cri_long; make_reset <= last_reset_via_cri_long and not reset_via_cri_long; - end process; + end process; + + + +-- generation of TDC calibration clock from recovered clock +THE_CAL_PLL : entity work.pll_in240_out50 + port map( + CLK => med2int(INTERFACE_NUM).clk_full, -- recovered 240MHz clk + CLKOP => clk_cal, -- 50MHz calibration Clock (multiple of 5ns) + LOCK => open + ); + --------------------------------------------------------------------------- -- TrbNet Uplink --------------------------------------------------------------------------- @@ -1137,7 +1150,7 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface CLK_READOUT => clk_sys, -- Clock for the readout REFERENCE_TIME => cts_trigger_out, -- Reference time input HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals - HIT_CAL_IN => clk_full_osc,--clk_cal, -- Hits for calibrating the TDC --FIXME: here we need a good cal clock! + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC -- Trigger signals from handler BUSRDO_RX => cts_rdo_rx, BUSRDO_TX => cts_rdo_additional(INCLUDE_ETM),--_TDCcal