From: Jan Michel Date: Tue, 23 Aug 2022 14:26:26 +0000 (+0200) Subject: update and cleanup of OEP design X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8a96e19db48df0e6dfbabec00f0bf6b2c30bedc1;p=mdcupgrade.git update and cleanup of OEP design add automatic ADC readings to OEP --- diff --git a/DBO/config.vhd b/DBO/config.vhd index 4d4e5d9..144af43 100644 --- a/DBO/config.vhd +++ b/DBO/config.vhd @@ -32,9 +32,10 @@ package config is constant INIT_ADDRESS : std_logic_vector := x"F6DC"; constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"91"; - constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_UART : integer := c_NO; --300 slices constant INCLUDE_SPI : integer := c_NO; --300 slices - constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_ADC : integer := c_NO; + constant INCLUDE_LCD : integer := c_NO; --800 slices constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices --input monitor and trigger generation logic diff --git a/OEP/config.vhd b/OEP/config.vhd index 7a539d5..96b8026 100644 --- a/OEP/config.vhd +++ b/OEP/config.vhd @@ -26,7 +26,8 @@ package config is constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"90"; constant INCLUDE_UART : integer := c_NO; --300 slices - constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_SPI : integer := c_NO; --300 slices + constant INCLUDE_ADC : integer := c_YES; --300 slices constant INCLUDE_LCD : integer := c_NO; --800 slices constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices diff --git a/OEP/config_compile_frankfurt.pl b/OEP/config_compile_frankfurt.pl index f234c89..310aee4 100644 --- a/OEP/config_compile_frankfurt.pl +++ b/OEP/config_compile_frankfurt.pl @@ -7,8 +7,8 @@ Speedgrade => '8', TOPNAME => "mdcoep", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", -lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', -synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/', +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', nodelist_file => '../nodelist_frankfurt.txt', pinout_file => 'oep', diff --git a/OEP/mdcoep.prj b/OEP/mdcoep.prj index d1d4f54..1bdf659 100644 --- a/OEP/mdcoep.prj +++ b/OEP/mdcoep.prj @@ -114,6 +114,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" + #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" @@ -153,11 +155,12 @@ add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" diff --git a/OEP/mdcoep.vhd b/OEP/mdcoep.vhd index 2db9887..757e30a 100644 --- a/OEP/mdcoep.vhd +++ b/OEP/mdcoep.vhd @@ -45,9 +45,10 @@ entity mdcoep is ADC_CS : out std_logic; --LED - LED : out std_logic_vector(7 downto 0) + LED : out std_logic_vector(7 downto 0); --Other Connectors + TEST : out std_logic_vector(8 downto 1) ); @@ -89,9 +90,6 @@ architecture arch of mdcoep is signal med_stat_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); signal rdack, wrack : std_logic; - - signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to 0); signal ctrlbus_tx, bustdc_tx, bussci_tx, bussci2_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX; signal ctrlbus_rx, bustdc_rx, bussci_rx, bussci2_rx, bustools_rx, bustc_rx, bus_master_out : CTRLBUS_RX; @@ -139,7 +137,6 @@ begin THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync_2 generic map( - IS_SYNC_SLAVE => (c_YES,c_NO) ) port map( @@ -208,61 +205,10 @@ begin STAT_DEBUG => open, --med_stat_debug(63 downto 0), CTRL_DEBUG => open ); - ---------------------------------------------------------------------------- --- Endpoint ---------------------------------------------------------------------------- --- THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record --- generic map ( --- ADDRESS_MASK => x"FFFF", --- BROADCAST_BITMASK => x"FF", --- REGIO_INIT_ENDPOINT_ID => x"0001", --- REGIO_USE_1WIRE_INTERFACE => c_I2C, --- TIMING_TRIGGER_RAW => c_YES, --- --Configure data handler --- DATA_INTERFACE_NUMBER => 1, --- DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, --- DATA_BUFFER_WIDTH => 32, --- DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, --- TRG_RELEASE_AFTER_DATA => c_YES, --- HEADER_BUFFER_DEPTH => 9, --- HEADER_BUFFER_FULL_THRESH => 2**9-16 --- ) --- --- port map( --- -- Misc --- CLK => clk_sys, --- RESET => reset_i, --- CLK_EN => '1', --- --- -- Media direction port --- MEDIA_MED2INT => med2int(0), --- MEDIA_INT2MED => int2med(0), --- --- --Timing trigger in --- TRG_TIMING_TRG_RECEIVED_IN => TRG, --- --- READOUT_RX => readout_rx, --- READOUT_TX => readout_tx, --- --- --Slow Control Port --- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 --- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 --- BUS_RX => ctrlbus_rx, --- BUS_TX => ctrlbus_tx, --- BUS_MASTER_IN => bus_master_in, --- BUS_MASTER_OUT => bus_master_out, --- BUS_MASTER_ACTIVE => bus_master_active, --- --- ONEWIRE_INOUT => open, --- I2C_SCL => I2C_SCL, --- I2C_SDA => I2C_SDA, --- --Timing registers --- TIMERS_OUT => timer --- ); --- --- +--------------------------------------------------------------------------- +-- The Hub +--------------------------------------------------------------------------- THE_HUB : entity work.trb_net16_hub_base generic map( HUB_USED_CHANNELS => (1,1,0,1), @@ -275,6 +221,10 @@ begin HARDWARE_VERSION => HARDWARE_INFO, INCLUDED_FEATURES => INCLUDED_FEATURES, INIT_ENDPOINT_ID => x"0001", + INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_800a4000_00000000" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", CLOCK_FREQUENCY => CLOCK_FREQUENCY, BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) @@ -340,8 +290,6 @@ begin --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- - - THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( PORT_NUMBER => 4, @@ -399,7 +347,7 @@ begin --Trigger & Monitor MONITOR_INPUTS => monitor_inputs_i, TRIG_GEN_INPUTS => trigger_inputs_i, - TRIG_GEN_OUTPUTS(1 downto 0) => open, --GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(1 downto 0) => open, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -421,8 +369,15 @@ begin --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- +monitor_inputs_i <= (others => '0'); +trigger_inputs_i <= (others => '0'); + + +TEST(1) <= ADC_CS; +TEST(2) <= ADC_MOSI; +TEST(3) <= ADC_MISO; +TEST(4) <= ADC_SCK; - --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- @@ -433,12 +388,7 @@ begin LED(3) <= (med2int(1).stat_op(10) or med2int(1).stat_op(11)) and not led_off; LED(4) <= med2int(1).stat_op(9) and not led_off; -------------------------------------------------------------------------------- --- No trigger/data endpoint included -------------------------------------------------------------------------------- --- readout_tx(0).data_finished <= '1'; --- readout_tx(0).data_write <= '0'; --- readout_tx(0).busy_release <= '1'; + end architecture; diff --git a/OEP/par.p2t b/OEP/par.p2t index 9e4ef4d..4c0769f 100644 --- a/OEP/par.p2t +++ b/OEP/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 2 +-t 5 -c 2 -e 2 -i 10 diff --git a/code/pasttrec_spi/README.md b/code/pasttrec_spi/README.md index 1c4f40e..c7c3416 100755 --- a/code/pasttrec_spi/README.md +++ b/code/pasttrec_spi/README.md @@ -25,7 +25,9 @@ The maximum number of connected PASTTREC chips to the whole system is 16. Every The last parameter SPI_CHIP_IDs should be filled with all chip ids used in a system. The two least significant bytes set the id for first PASTTREC in the first SPI bunch, while the SPI_CHIP_IDs(2k + 1 downto 2k) sets chips id for PASTTREC #k+1. Example: 2 SPI bunches with 2 PASTTRECs in each. First bunch’ chip ids: 00 01. Second bunch’ chip ids: 01 10. Then SPI_CHIP_IDs must be filled with x"000000" & “10010100”. + ### Port map + | Name | Type | Mode | Description | | ----------- | ---------- | ---- | ----------------------------------- | | CLK | std_logic | In | Clock signal | diff --git a/code/pasttrec_spi/readme.pdf b/code/pasttrec_spi/readme.pdf new file mode 100644 index 0000000..64aaa43 Binary files /dev/null and b/code/pasttrec_spi/readme.pdf differ