From: Michael Boehmer Date: Wed, 16 Feb 2022 10:55:43 +0000 (+0100) Subject: adopted to new MII X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8ae851cf6ca71185cf3d9720d6fb56558da1b191;p=trb3sc.git adopted to new MII --- diff --git a/hub/trb3sc_hub.lpf b/hub/trb3sc_hub.lpf index ff14d2f..e772c1c 100644 --- a/hub/trb3sc_hub.lpf +++ b/hub/trb3sc_hub.lpf @@ -29,6 +29,15 @@ USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[2]"; USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[3]"; USE SECONDARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[1]"; +# read from SCI can be delayed due to long read strobe +MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +# write strobe can be delayed due to A/D being stable after access +MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; + +# SCI write signal problem... +#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i; +#BLOCK INTERCLOCKDOMAIN PATHS; + ################################ FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index d747323..f2852a6 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -265,6 +265,7 @@ gen_PCSA : if USE_BACKPLANE = c_YES generate SYNC_TX_PLL_IN => sync_tx_quad_i, LINK_TX_READY_IN => link_tx_ready_i, DESTROY_LINK_IN => x"0", + WAP_REQUESTED_IN => x"0", --SFP Connection SD_PRSNT_N_IN(0) => BACK_GPIO(1), SD_PRSNT_N_IN(1) => '1', @@ -339,6 +340,7 @@ gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate SYNC_TX_PLL_IN => sync_tx_quad_i, LINK_TX_READY_IN => link_tx_ready_i, DESTROY_LINK_IN => x"0", + WAP_REQUESTED_IN => x"0", --SFP Connection SD_PRSNT_N_IN(0) => HUB_MOD0(5), SD_PRSNT_N_IN(1) => HUB_MOD0(6), @@ -417,6 +419,7 @@ gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate SYNC_TX_PLL_IN => sync_tx_quad_i, LINK_TX_READY_IN => link_tx_ready_i, DESTROY_LINK_IN => x"0", + WAP_REQUESTED_IN => x"0", --SFP Connection SD_PRSNT_N_IN(0) => HUB_MOD0(5), SD_PRSNT_N_IN(1) => HUB_MOD0(6), @@ -508,6 +511,7 @@ end generate; SYNC_TX_PLL_IN => sync_tx_quad_i, LINK_TX_READY_IN => link_tx_ready_i, DESTROY_LINK_IN => x"0", + WAP_REQUESTED_IN => x"0", --SFP Connection SD_PRSNT_N_IN(0) => HUB_MOD0(3), SD_PRSNT_N_IN(1) => HUB_MOD0(4), @@ -578,6 +582,7 @@ gen_PCSD : if INCLUDE_GBE = c_NO generate SYNC_TX_PLL_IN => sync_tx_quad_i, LINK_TX_READY_IN => link_tx_ready_i, DESTROY_LINK_IN => x"0", + WAP_REQUESTED_IN => x"0", --SFP Connection SD_PRSNT_N_IN(0) => SFP_MOD0(0), SD_PRSNT_N_IN(1) => HUB_MOD0(8), diff --git a/tdctemplate/trb3sc_tdctemplate.lpf b/tdctemplate/trb3sc_tdctemplate.lpf index c6e8082..0598a2e 100644 --- a/tdctemplate/trb3sc_tdctemplate.lpf +++ b/tdctemplate/trb3sc_tdctemplate.lpf @@ -15,3 +15,12 @@ MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/clk_125_rx_from_pcs[0]" 125 MHz; LOCATE COMP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; + +# read from SCI can be delayed due to long read strobe +MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +# write strobe can be delayed due to A/D being stable after access +MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; + +# SCI write signal problem... +#BLOCK NET gen_PCSB.THE_MEDIA_PCSB/sci_write_i; +#BLOCK INTERCLOCKDOMAIN PATHS; diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 7e63290..bae8485 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -265,6 +265,7 @@ end generate; DESTROY_LINK_IN(1) => '0', DESTROY_LINK_IN(2) => '0', DESTROY_LINK_IN(3) => '0', + WAP_REQUESTED_IN => x"0", --SFP Connection SD_PRSNT_N_IN(0) => '1', SD_LOS_IN(0) => '1',