From: Jan Michel Date: Mon, 4 Aug 2014 11:35:28 +0000 (+0200) Subject: Added regio bus handler version using records for bus signals. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8befc679fc4ea6e6a3cbf113a402ae7164ff3c4a;p=trbnet.git Added regio bus handler version using records for bus signals. --- diff --git a/trb_net16_regio_bus_handler_record.vhd b/trb_net16_regio_bus_handler_record.vhd index 5ac10dd..7963344 100644 --- a/trb_net16_regio_bus_handler_record.vhd +++ b/trb_net16_regio_bus_handler_record.vhd @@ -1,11 +1,9 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.trb_net_components.all; entity trb_net16_regio_bus_handler_record is generic( @@ -38,10 +36,6 @@ end entity; architecture regio_bus_handler_arch of trb_net16_regio_bus_handler_record is - -- Placer Directives --- attribute HGROUP : string; - -- for whole architecture --- attribute HGROUP of regio_bus_handler_arch : architecture is "Bus_handler_group"; signal port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS; signal next_port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS; @@ -114,30 +108,32 @@ begin --Map Data Outputs --------------------------------------------------------------------- - BUS_READ_ENABLE_OUT <= buf_BUS_READ_OUT(PORT_NUMBER-1 downto 0); - BUS_WRITE_ENABLE_OUT<= buf_BUS_WRITE_OUT(PORT_NUMBER-1 downto 0); - gen_bus_outputs : for i in 0 to PORT_NUMBER-1 generate - BUS_DATA_OUT(i*32+31 downto i*32) <= buf_BUS_DATA_OUT; + gen_outputs : for i in 0 to PORT_NUMBER-1 generate + BUS_RX(i).read <= buf_BUS_READ_OUT(i); + BUS_RX(i).write <= buf_BUS_WRITE_OUT(i); + BUS_RX(i).data <= buf_BUS_DATA_OUT; + BUS_RX(i).timeout <= DAT_TIMEOUT_IN; port_mask_disabled : if PORT_MASK_ENABLE = 0 generate - BUS_ADDR_OUT(i*16+15 downto i*16) <= buf_BUS_ADDR_OUT; + BUS_RX(i).addr <= buf_BUS_ADDR_OUT; + end generate; + port_mask_enabled : if PORT_MASK_ENABLE = 1 generate + BUS_RX(i).addr(PORT_ADDR_MASK(i)-1 downto 0) <= buf_BUS_ADDR_OUT(PORT_ADDR_MASK(i)-1 downto 0); + BUS_RX(i).addr(15 downto PORT_ADDR_MASK(i)) <= (others => '0'); end generate; - port_mask_enabled : if PORT_MASK_ENABLE = 1 generate - BUS_ADDR_OUT(i*16+15 downto i*16+PORT_ADDR_MASK(i)) <= (others => '0'); - BUS_ADDR_OUT(i*16+PORT_ADDR_MASK(i)-1 downto i*16) - <= buf_BUS_ADDR_OUT(PORT_ADDR_MASK(i)-1 downto 0); - end generate; - BUS_TIMEOUT_OUT(i) <= DAT_TIMEOUT_IN; end generate; --------------------------------------------------------------------- --Pack Data Inputs and Dummy Input --------------------------------------------------------------------- - buf_BUS_DATA_IN(PORT_NUMBER*32-1 downto 0) <= BUS_DATA_IN; - buf_BUS_DATAREADY_IN(PORT_NUMBER-1 downto 0) <= BUS_DATAREADY_IN; - buf_BUS_WRITE_ACK_IN(PORT_NUMBER-1 downto 0) <= BUS_WRITE_ACK_IN; - buf_BUS_NO_MORE_DATA_IN(PORT_NUMBER-1 downto 0) <= BUS_NO_MORE_DATA_IN; - buf_BUS_UNKNOWN_ADDR_IN(PORT_NUMBER-1 downto 0) <= BUS_UNKNOWN_ADDR_IN; + gen_inputs : for i in 0 to PORT_NUMBER-1 generate + buf_BUS_DATA_IN(i*32+31 downto i*32) <= BUS_TX(i).data; + buf_BUS_DATAREADY_IN(i) <= BUS_TX(i).ack or BUS_TX(i).rack; + buf_BUS_WRITE_ACK_IN(i) <= BUS_TX(i).ack or BUS_TX(i).wack; + buf_BUS_NO_MORE_DATA_IN(i) <= BUS_TX(i).nack; + buf_BUS_UNKNOWN_ADDR_IN(i) <= BUS_TX(i).unknown; + end generate; + buf_BUS_DATA_IN(PORT_NUMBER*32+31 downto PORT_NUMBER*32) <= (others => '0'); buf_BUS_DATAREADY_IN(PORT_NUMBER) <= '0'; buf_BUS_WRITE_ACK_IN(PORT_NUMBER) <= '0';