From: palka Date: Tue, 8 Jan 2008 12:40:48 +0000 (+0000) Subject: trb in cts X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8ceac8c0870a6dde88034a0efd3f0ec46b7d23f7;p=trbv2.git trb in cts --- diff --git a/trb_cts/compile_cts.pl b/trb_cts/compile_cts.pl new file mode 100755 index 0000000..fd53741 --- /dev/null +++ b/trb_cts/compile_cts.pl @@ -0,0 +1,141 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +# +########################################### +# +# Command line for synplify_pro +# + + +use FileHandle; + + +$ENV{LM_LICENSE_FILE}="1709\@hadeb05"; + + + +$PLD_DEVICE="xc4vlx40-10-ff1148"; +$TOPNAME="cts"; + + + +#set -e +#set -o errexit + +system("env| grep LM_"); + +#$c="/opt/Synplicity/fpga_861/bin/synplify_pro -batch $TOPNAME"."_syn.prj"; +$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; +#$c="/opt/Synplicity/fpga_8804/bin/synplify_pro -batch $TOPNAME"."_syn.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +my $fh = new FileHandle("; +$fh -> close; + +#if ($r) { +#$c="cat $TOPNAME.srr"; +#system($c); +#exit 129; +#} + +foreach (@a) +{ + if(/\@E:/) + { + $c="cat $TOPNAME.srr"; + system($c); + print "bdabdhsadbhjasdhasldhbas"; + exit 129; + } +} +# +# Command line to synthesize +# + +#chdir ".."; +#$c="xst -intstyle xflow -ifn $TOPNAME.xst -ofn $TOPNAME.syr"; +#execute($c); +#chdir "workdir"; + +# +# Command line for ngdbuild +# +#$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf ../$TOPNAME.ngc $TOPNAME.ngd"; +$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf -sd ../ $TOPNAME.edf $TOPNAME.ngd"; +execute($c); +# +# Command line for fpgafit +# +$c="map -detail -u -p $PLD_DEVICE -cm speed -pr b -k 4 -c 100 -tx off -intstyle xflow -o $TOPNAME"."_map.ncd $TOPNAME.ngd $TOPNAME.pcf"; +execute($c); + +# +# Command line for Place & Route +# + +$c="par -w -intstyle xflow -ol std -t 1 $TOPNAME"."_map.ncd $TOPNAME.ncd $TOPNAME.pcf"; +execute($c); + +# +# Command line for genarate programming file (.bit) +# + + +foreach (<$TOPNAME"."_pad.txt>) { + @a=split (/\s*\|\s*/,$_); + if( ($a[2] ne "" && + $a[2] ne "Signal Name") && + $a[13] ne "LOCATED" + ) + { + print "error, pins were assigned automatically:\n$_\n"; + exit; + } +} + +print "_pad.txt tested for automatically assigned pins\n"; + +#$c="bitgen -w -intstyle ise -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No $TOPNAME"; +$c="bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DisableBandgap:No -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No $TOPNAME.ncd"; + +execute($c); +# +# Command line for generate .stapl file +# + +$c="XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch ../impact_batch_cts.txt"; + +execute($c); + + +#ssh depc152 'cd ~/files/vhdl/xilinx; . ~/bin/xilinx_setup; XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch conf_xilinx_impact.txt ' + +# +#to download file on ETRAX chip +# + +#$c="lftp root:pass@hades18;put RPCBoardContrller;exit"; +#execute($c) + +chdir ".."; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/trb_cts/cts.stapl b/trb_cts/cts.stapl new file mode 100644 index 0000000..0a204e7 --- /dev/null +++ b/trb_cts/cts.stapl @@ -0,0 +1,3240 @@ +NOTE "CREATOR" "Xilinx iMPACT Software"; +NOTE "DATE" "2007/12/06"; +NOTE "STAPL_VERSION" "JESD71"; +NOTE "ALG_VERSION" "1"; +NOTE "DEVICE" "UNSPECIFIED"; +NOTE "CHECKSUM" "UNSPECIFIED"; +NOTE "IDCODE" "UNSPECIFIED"; +NOTE "USERCODE" "UNSPECIFIED"; +NOTE "TARGET" "UNSPECIFIED"; +NOTE "STACK_DEPTH" "4"; +NOTE "MAX_FREQ" "1000000"; +ACTION RUN_XILINX_PROC "Run Xilinx Procedure" = XILINX_PROC; +DATA MAINDATA; +INTEGER I = 0; +INTEGER D = 0; +ENDDATA; +PROCEDURE XILINX_PROC USES ADJUST_DELAY, MAINDATA; +BOOLEAN X = 0; +IRSTOP IDLE; +DRSTOP IDLE; +STATE RESET IDLE; +POSTIR 0 ; +PREIR 0 ; +POSTDR 0 ; +PREDR 0 ; +POSTIR 0 ; +PREIR 0 ; +PREDR 0 ; +POSTDR 0 ; +' //Loading device with 'idcode' instruction. +IRSCAN 10, $03c9 + ; +DRSCAN 32, $00000000 +, COMPARE $f16a4093 +, $0fffffff +, X; +IF (!X) THEN GOTO F; +POSTIR 0 ; +PREIR 0 ; +POSTDR 0 ; +PREDR 0 ; +POSTIR 0 ; +PREIR 0 ; +POSTDR 0 ; +PREDR 0 ; +POSTIR 0 ; +PREIR 0 ; +PREDR 0 ; +POSTDR 0 ; +' //Loading device with 'idcode' instruction. +IRSCAN 10, $03c9 + ; +DRSCAN 32, $00000000 +, COMPARE $f16a4093 +, $0fffffff +, X; +IF (!X) THEN GOTO F; +' //Loading device with 'bypass' instruction. +IRSCAN 10, $03ff + ; +' // Loading device with a `jprogram` instruction. +IRSCAN 10, $03cb + ; +D = 1; +WAIT D CYCLES; +' // Loading device with a `bypass` instruction. +IRSCAN 10, $03ff + ; +D = 21000; +WAIT D CYCLES; +' // Loading device with a `cfg_in` instruction. +IRSCAN 10, $03c5 + ; +D = 100000; +WAIT D CYCLES; +' // Check init_complete in ircapture. +' //Loading device with 'Bypass' instruction. +IRSCAN 10, $03ff +, COMPARE $0010 +, $0010 +, X; +IF (!X) THEN GOTO F; +' STATE RESET; +' // Loading device with a `cfg_in` instruction. +IRSCAN 10, $03c5 +, COMPARE $0000 +, $0000 +, X; +IF (!X) THEN GOTO F; +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +DRSCAN 12259744, @q8s50000000@@l@@lAPggP8000003080010000E20000G000006081020GPrfC0e004GM9Go +1D00GI00000C0m00400060C0W2040006080WqC82421YW09G05G03m@3W@dV@F@x@yp@pV@F +__@uV@7Vy@ud@dUz@ql@dU_@qt@7U@@m@_Fym@3VCX88P0000GYa6a3G280G0YbC10081000 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+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@n000m0000G7PWfIW1040W0000W +210000O001080000WH00000208102Y00XG0W880G240e020C0X6ZPmWa6O86W4G0W00Ge48n +1300e40000030C0010000030e00ZUm000eyggJuZUm000B1vEy3 + ; +' // Loading device with a `jstart` instruction. +IRSCAN 10, $03cc + ; +D = 12; +WAIT D CYCLES; +' //Loading device with 'bypass' instruction. +IRSCAN 10, $03ff + ; +' //Loading device with 'bypass' instruction. +IRSCAN 10, $03ff + ; +POSTIR 0 ; +PREIR 0 ; +PREDR 0 ; +POSTDR 0 ; +POSTIR 0 ; +PREIR 0 ; +PREDR 0 ; +POSTDR 0 ; +' // Loading device with a `jstart` instruction. +IRSCAN 10, $03cc + ; +D = 12; +WAIT D CYCLES; +' //Checking done pin status. +' //Loading device with 'Bypass' instruction. +IRSCAN 10, $03ff +, COMPARE $0021 +, $0020 +, X; +IF (!X) THEN GOTO F; +POSTIR 0 ; +PREIR 0 ; +POSTDR 0 ; +PREDR 0 ; +IRSCAN 10, $03ff + ; +DRSCAN 1, $00 + ; + +SUCCESS: +PRINT "Successful File Execution."; +EXIT 0; + +F: +PRINT "File Execution Failure."; +EXIT 16; + +ENDPROC; + +DATA TMPDATA; +INTEGER TMP_DELAY; +ENDDATA; + +PROCEDURE ADJUST_BIG_DELAY USES TMPDATA, MAINDATA; +TMP_DELAY = D / 100; +TMP_DELAY = TMP_DELAY * 25; +D = D + TMP_DELAY; +ENDPROC; + +PROCEDURE ADJUST_SMALL_DELAY USES TMPDATA, MAINDATA; +TMP_DELAY = D * 25; +TMP_DELAY = TMP_DELAY / 100; +D = D + TMP_DELAY; +ENDPROC; + +PROCEDURE ADJUST_DELAY USES MAINDATA, ADJUST_BIG_DELAY, ADJUST_SMALL_DELAY; +IF D > 2500 THEN CALL ADJUST_BIG_DELAY; +IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY; +ENDPROC; + +CRC DF32; diff --git a/trb_cts/cts.ucf b/trb_cts/cts.ucf new file mode 100644 index 0000000..667e663 --- /dev/null +++ b/trb_cts/cts.ucf @@ -0,0 +1,637 @@ + # NET +<1> LOC = AE28; + # NET +<2> LOC ="L2| IOSTANDARD = "LVTTL"; + # NET +<3> LOC ="AJ18| IOSTANDARD = "LVTTL"; + # NET ADDON_TO_TRB_CLKINN LOC ="G16| IOSTANDARD = "LVTTL"; + # NET ADDON_TO_TRB_CLKINP LOC ="G17| IOSTANDARD = "LVTTL"; + NET ADO_LV<0> LOC ="AC9"; + NET ADO_LV<1> LOC ="AC8"; + NET ADO_LV<2> LOC ="AG3"; + NET ADO_LV<3> LOC ="AF3"; + NET ADO_LV<4> LOC ="AF6"; + NET ADO_LV<5> LOC ="AE6"; + NET ADO_LV<6> LOC ="AF5"; + NET ADO_LV<7> LOC ="AF4"; + NET ADO_LV<8> LOC ="AL1"; + NET ADO_LV<9> LOC ="AK1"; + NET ADO_LV<10> LOC ="AJ2"; + NET ADO_LV<11> LOC ="AJ1"; + NET ADO_LV<12> LOC ="AB6"; + NET ADO_LV<13> LOC ="AB5"; + NET ADO_LV<14> LOC ="AC3"; + NET ADO_LV<15> LOC ="AC2"; + NET ADO_LV<16> LOC ="Y11"; + NET ADO_LV<17> LOC ="AA11"; + NET ADO_LV<18> LOC ="AD2"; + NET ADO_LV<19> LOC ="AD1"; + NET ADO_LV<20> LOC ="Y14"; + NET ADO_LV<21> LOC ="AA13"; + NET ADO_LV<22> LOC ="AC5"; + NET ADO_LV<23> LOC ="AC4"; + NET ADO_LV<24> LOC ="AF1"; + NET ADO_LV<25> LOC ="AE1"; + NET ADO_LV<26> LOC ="AE3"; + NET ADO_LV<27> LOC ="AE2"; + NET ADO_LV<28> LOC ="AD6"; + NET ADO_LV<29> LOC ="AD5"; + NET ADO_LV<30> LOC ="AC7"; + NET ADO_LV<31> LOC ="AB8"; + NET ADO_LV<32> LOC ="Y16"; + NET ADO_LV<33> LOC ="AA15"; + NET ADO_LV<34> LOC ="AE4"; + NET ADO_LV<35> LOC ="AD4"; + NET ADO_LV<36> LOC ="AH3"; + NET ADO_LV<37> LOC ="AH2"; + NET ADO_LV<38> LOC ="AG2"; + NET ADO_LV<39> LOC ="AG1"; + NET ADO_LV<40> LOC ="AK3"; + NET ADO_LV<41> LOC ="AK2"; + NET ADO_LV<42> LOC ="AF8"; + NET ADO_LV<43> LOC ="AE8"; + NET ADO_LV<44> LOC ="AH5"; + NET ADO_LV<45> LOC ="AH4"; + NET ADO_LV<46> LOC ="AB13"; + NET ADO_LV<47> LOC ="AB12"; + NET ADO_LV<48> LOC ="AM2"; + NET ADO_LV<49> LOC ="AM1"; + NET ADO_LV<50> LOC ="AG8"; + NET ADO_LV<51> LOC ="AG7"; +# NET ADO_LV<52> LOC ="AM3"; +# NET ADO_LV<53> LOC ="AL3"; +# NET ADO_LV<54> LOC ="AK22"; +# NET ADO_LV<55> LOC ="AK23"; +# NET ADO_LV<56> LOC ="AL28"; +# NET ADO_LV<57> LOC ="AL29"; +# NET ADO_LV<58> LOC ="AP25"; +# NET ADO_LV<59> LOC ="AP26"; +# NET ADO_LV<60> LOC ="AJ27"; +# NET ADO_LV<61> LOC ="AH27"; +# NET ADO_TTL<0> LOC ="AL11"| IOSTANDARD = "LVTTL"; +# NET ADO_TTL<1> LOC ="AL10"| IOSTANDARD = "LVTTL"; + NET ADO_CLK1 LOC ="AL11"| IOSTANDARD = "LVTTL"; + NET ADO_CLK2 LOC ="AL10"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<2> LOC ="AE11"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<3> LOC ="AF11"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<4> LOC ="AM12"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<5> LOC ="AM11"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<6> LOC ="AL9"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<7> LOC ="AK9"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<8> LOC ="AP11"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<9> LOC ="AP10"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<10> LOC ="AH10"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<11> LOC ="AG10"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<12> LOC ="AN12"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<13> LOC ="AP12"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<14> LOC ="AP9"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<15> LOC ="AN9"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<16> LOC ="AH12"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<17> LOC ="AG11"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<18> LOC ="AN7"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<19> LOC ="AM7"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<20> LOC ="AN10"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<21> LOC ="AM10"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<22> LOC ="AF10"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<23> LOC ="AE9"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<24> LOC ="AJ12"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<25> LOC ="L33"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<26> LOC ="L34"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<27> LOC ="M32"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<28> LOC ="M33"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<29> LOC ="D5"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<30> LOC ="G7"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<31> LOC ="G6"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<32> LOC ="E14"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<33> LOC ="D14"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<34> LOC ="AL20"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<35> LOC ="AJ15"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<36> LOC ="AJ14"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<37> LOC ="AG20"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<38> LOC ="AH20"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<39> LOC ="AG15"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<40> LOC ="AH14"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<41> LOC ="AL16"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<42> LOC ="AK16"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<43> LOC ="C28"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<44> LOC ="L26"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<45> LOC ="B32"| IOSTANDARD = "LVTTL"; + NET ADO_TTL<46> LOC ="B33"| IOSTANDARD = "LVTTL"; + # NET A_CS1B LOC ="P9"| IOSTANDARD = "LVTTL"; + # NET A_CS<1> LOC ="P10"| IOSTANDARD = "LVTTL"; + # NET A_DATA_READY LOC ="B12"| IOSTANDARD = "LVTTL"; + # NET A_RESERVED LOC ="J11"| IOSTANDARD = "LVTTL"; + # NET A_SCK LOC ="H3"| IOSTANDARD = "LVTTL"; + # NET A_SCKB LOC ="H2"| IOSTANDARD = "LVTTL"; + # NET A_SDI LOC ="F1"| IOSTANDARD = "LVTTL"; + # NET A_SDIB LOC ="G1"| IOSTANDARD = "LVTTL"; + # NET A_SDO LOC ="J4"| IOSTANDARD = "LVTTL"; + # NET A_SDOB LOC ="K4"| IOSTANDARD = "LVTTL"; + # NET A_TDC_BU_RESET LOC ="AK27"| IOSTANDARD = "LVTTL"; + # NET A_TDC_BU_RESETB LOC ="AK28"| IOSTANDARD = "LVTTL"; + # NET A_TDC_ERROR LOC ="F11"| IOSTANDARD = "LVTTL"; + # NET A_TDC_EV_RESET LOC ="AK24"; + # NET A_TDC_EV_RESETB LOC ="AJ24"; + # NET A_TDC_POWERUP LOC ="H8"| IOSTANDARD = "LVTTL"; + # NET A_TEMP LOC ="B7"| IOSTANDARD = "LVTTL"; + # NET A_TEST1B LOC ="N7"| IOSTANDARD = "LVTTL"; + # NET A_TEST2B LOC ="L4"| IOSTANDARD = "LVTTL"; + # NET A_TEST<1> LOC ="M7"| IOSTANDARD = "LVTTL"; + # NET A_TEST<2> LOC ="L5"| IOSTANDARD = "LVTTL"; + # NET A_TRIGGER LOC ="J6"; + # NET A_TRIGGERB LOC ="J5"; + # NET B_CS1B LOC ="G5"| IOSTANDARD = "LVTTL"; + # NET B_CS<1> LOC ="F5"| IOSTANDARD = "LVTTL"; + # NET B_DATA_READY LOC ="A8"| IOSTANDARD = "LVTTL"; + # NET B_RESERVED LOC ="C7"| IOSTANDARD = "LVTTL"; + # NET B_SCK LOC ="C4"| IOSTANDARD = "LVTTL"; + # NET B_SCKB LOC ="C3"| IOSTANDARD = "LVTTL"; + # NET B_SDI LOC ="R11"| IOSTANDARD = "LVTTL"; + # NET B_SDIB LOC ="T11"| IOSTANDARD = "LVTTL"; + # NET B_SDO LOC ="G3"| IOSTANDARD = "LVTTL"; + # NET B_SDOB LOC ="G2"| IOSTANDARD = "LVTTL"; + # NET B_TDC_BU_RESET LOC ="AG25"; + # NET B_TDC_BU_RESETB LOC ="AG26"; + # NET B_TDC_ERROR LOC ="A6"| IOSTANDARD = "LVTTL"; + # NET B_TDC_EV_RESET LOC ="AG23"; + # NET B_TDC_EV_RESETB LOC ="AF24"; + # NET B_TDC_POWERUP LOC ="H7"| IOSTANDARD = "LVTTL"; + # NET B_TEMP LOC ="A10"| IOSTANDARD = "LVTTL"; + # NET B_TEST2B LOC ="L9"| IOSTANDARD = "LVTTL"; + # NET B_TEST1B LOC ="E4"| IOSTANDARD = "LVTTL"; + # NET B_TEST<1> LOC ="D4"| IOSTANDARD = "LVTTL"; + # NET B_TEST<2> LOC ="M10"| IOSTANDARD = "LVTTL"; + # NET B_TRIGGER LOC ="H5"; + # NET B_TRIGGERB LOC ="H4"; + # NET C_CS1B LOC ="R9"| IOSTANDARD = "LVTTL"; + # NET C_CS<1> LOC ="T10"| IOSTANDARD = "LVTTL"; + # NET C_DATA_READY LOC ="B8"| IOSTANDARD = "LVTTL"; + # NET C_RESERVED LOC ="F8"| IOSTANDARD = "LVTTL"; + # NET C_SCK LOC ="P7"| IOSTANDARD = "LVTTL"; + # NET C_SCKB LOC ="P6"| IOSTANDARD = "LVTTL"; + # NET C_SDI LOC ="D1"| IOSTANDARD = "LVTTL"; + # NET C_SDIB LOC ="E1"| IOSTANDARD = "LVTTL"; + # NET C_SDO LOC ="F4"| IOSTANDARD = "LVTTL"; + # NET C_SDOB LOC ="F3"| IOSTANDARD = "LVTTL"; + # NET C_TDC_BU_RESET LOC ="AP31"; + # NET C_TDC_BU_RESETB LOC ="AP32"; + # NET C_TDC_ERROR LOC ="B6"| IOSTANDARD = "LVTTL"; + # NET C_TDC_EV_RESET LOC ="AP27"; + # NET C_TDC_EV_RESETB LOC ="AN27"; + # NET C_TDC_POWERUP LOC ="K8"| IOSTANDARD = "LVTTL"; + # NET C_TEMP LOC ="A9"| IOSTANDARD = "LVTTL"; + # NET C_TEST2B LOC ="N12"| IOSTANDARD = "LVTTL"; + # NET C_TEST1B LOC ="D2"| IOSTANDARD = "LVTTL"; + # NET C_TEST<1> LOC ="C2"| IOSTANDARD = "LVTTL"; + # NET C_TEST<2> LOC ="N13"| IOSTANDARD = "LVTTL"; + # NET C_TOKEN_OUT_TTL LOC ="F6"| IOSTANDARD = "LVTTL"; + # NET C_TRIGGER LOC ="N10"; + # NET C_TRIGGERB LOC ="N9"; + NET DBAD LOC ="M28"| IOSTANDARD = "LVTTL"; + NET DGOOD LOC ="H34"| IOSTANDARD = "LVTTL"; + NET DINT LOC ="L31"| IOSTANDARD = "LVTTL"; + NET DSPADDR<0> LOC ="AA23"| IOSTANDARD = "LVTTL"; + NET DSPADDR<1> LOC ="AA24"| IOSTANDARD = "LVTTL"; + NET DSPADDR<2> LOC ="AJ34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<3> LOC ="AH34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<4> LOC ="AD27"| IOSTANDARD = "LVTTL"; + NET DSPADDR<5> LOC ="AC27"| IOSTANDARD = "LVTTL"; + NET DSPADDR<6> LOC ="AB25"| IOSTANDARD = "LVTTL"; + NET DSPADDR<7> LOC ="AB26"| IOSTANDARD = "LVTTL"; + NET DSPADDR<8> LOC ="AG30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<9> LOC ="AG31"| IOSTANDARD = "LVTTL"; + NET DSPADDR<10> LOC ="AH32"| IOSTANDARD = "LVTTL"; + NET DSPADDR<11> LOC ="AH33"| IOSTANDARD = "LVTTL"; + NET DSPADDR<12> LOC ="AF29"| IOSTANDARD = "LVTTL"; + NET DSPADDR<13> LOC ="AF30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<14> LOC ="AA28"| IOSTANDARD = "LVTTL"; + NET DSPADDR<15> LOC ="AA29"| IOSTANDARD = "LVTTL"; + NET DSPADDR<16> LOC ="W24"| IOSTANDARD = "LVTTL"; + NET DSPADDR<17> LOC ="Y24"| IOSTANDARD = "LVTTL"; + NET DSPADDR<18> LOC ="AB30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<19> LOC ="AA30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<20> LOC ="W25"| IOSTANDARD = "LVTTL"; + NET DSPADDR<21> LOC ="Y26"| IOSTANDARD = "LVTTL"; + NET DSPADDR<22> LOC ="AE33"| IOSTANDARD = "LVTTL"; + NET DSPADDR<23> LOC ="AE34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<24> LOC ="AC32"| IOSTANDARD = "LVTTL"; + NET DSPADDR<25> LOC ="AC33"| IOSTANDARD = "LVTTL"; + NET DSPADDR<26> LOC ="AC29"| IOSTANDARD = "LVTTL"; + NET DSPADDR<27> LOC ="AC30"| IOSTANDARD = "LVTTL"; + NET DSPADDR<28> LOC ="AD34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<29> LOC ="AC34"| IOSTANDARD = "LVTTL"; + NET DSPADDR<30> LOC ="AH18"| IOSTANDARD = "LVTTL"; + NET DSPADDR<31> LOC ="AK18"| IOSTANDARD = "LVTTL"; + NET DSPDAT<0> LOC ="AA25"| IOSTANDARD = "LVTTL"; + NET DSPDAT<1> LOC ="AA26"| IOSTANDARD = "LVTTL"; + NET DSPDAT<2> LOC ="AE32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<3> LOC ="AD32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<4> LOC ="AC28"| IOSTANDARD = "LVTTL"; + NET DSPDAT<5> LOC ="AB28"| IOSTANDARD = "LVTTL"; + NET DSPDAT<6> LOC ="AD30"| IOSTANDARD = "LVTTL"; + NET DSPDAT<7> LOC ="AD31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<8> LOC ="AG32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<9> LOC ="AG33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<10> LOC ="AF33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<11> LOC ="AF34"| IOSTANDARD = "LVTTL"; + NET DSPDAT<12> LOC ="AE29"| IOSTANDARD = "LVTTL"; + NET DSPDAT<13> LOC ="AD29"| IOSTANDARD = "LVTTL"; + NET DSPDAT<14> LOC ="AF31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<15> LOC ="AE31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<16> LOC ="AK31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<17> LOC ="AK32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<18> LOC ="AK33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<19> LOC ="AK34"| IOSTANDARD = "LVTTL"; + NET DSPDAT<20> LOC ="AM32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<21> LOC ="AM33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<22> LOC ="AJ31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<23> LOC ="AJ32"| IOSTANDARD = "LVTTL"; + NET DSPDAT<24> LOC ="AB22"| IOSTANDARD = "LVTTL"; + NET DSPDAT<25> LOC ="AB23"| IOSTANDARD = "LVTTL"; + NET DSPDAT<26> LOC ="AL33"| IOSTANDARD = "LVTTL"; + NET DSPDAT<27> LOC ="AL34"| IOSTANDARD = "LVTTL"; + NET DSPDAT<28> LOC ="AM31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<29> LOC ="AL31"| IOSTANDARD = "LVTTL"; + NET DSPDAT<30> LOC ="AJ30"| IOSTANDARD = "LVTTL"; + NET DSPDAT<31> LOC ="AH30"| IOSTANDARD = "LVTTL"; + NET DSP_ACK LOC ="AB15"| IOSTANDARD = "LVTTL"; + NET DSP_BM LOC ="AH19"| IOSTANDARD = "LVTTL"; + NET DSP_BMS LOC ="AF15"| IOSTANDARD = "LVTTL"; + NET DSP_BOFF LOC ="AK14"| IOSTANDARD = "LVTTL"; + NET DSP_BRST LOC ="AN20"| IOSTANDARD = "LVTTL"; + # NET DSP_BUSLOCK LOC ="AC19"| IOSTANDARD = "LVTTL"; + # NET DSP_DMAR<0> LOC ="AD17"| IOSTANDARD = "LVTTL"; + # NET DSP_DMAR<1> LOC ="AC17"| IOSTANDARD = "LVTTL"; + # NET DSP_DMAR<2> LOC ="AM20"| IOSTANDARD = "LVTTL"; + # NET DSP_DMAR<3> LOC ="AL19"| IOSTANDARD = "LVTTL"; + # NET DSP_FLAG<0> LOC ="AE21"| IOSTANDARD = "LVTTL"; + # NET DSP_FLAG<1> LOC ="AF21"| IOSTANDARD = "LVTTL"; + # NET DSP_FLAG<2> LOC ="AP15"| IOSTANDARD = "LVTTL"; + # NET DSP_FLAG<3> LOC ="AN15"| IOSTANDARD = "LVTTL"; + NET DSP_HBG LOC ="AD16"| IOSTANDARD = "LVTTL"; + NET DSP_HBR LOC ="AB18"| IOSTANDARD = "LVTTL"; + # NET DSP_IOEN LOC ="AL18"| IOSTANDARD = "LVTTL"; + # NET DSP_IORD LOC ="AB16"| IOSTANDARD = "LVTTL"; + # NET DSP_IOWR LOC ="AB17"| IOSTANDARD = "LVTTL"; + NET DSP_IRQ<0> LOC ="AG21"| IOSTANDARD = "LVTTL"; + NET DSP_IRQ<1> LOC ="AF20"| IOSTANDARD = "LVTTL"; + NET DSP_IRQ<2> LOC ="AF14"| IOSTANDARD = "LVTTL"; + NET DSP_IRQ<3> LOC ="AG13"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATIP<0> LOC ="AK29"| IOSTANDARD = "LVTTL"; + # NET DSP_L0ACKI LOC ="AM18"| IOSTANDARD = "LVTTL"; + # NET DSP_L1ACKO LOC ="AM15"| IOSTANDARD = "LVTTL"; + # NET DSP_L0BCMPI LOC ="AM16"| IOSTANDARD = "LVTTL"; + # NET DSP_L0BCMPO LOC ="AD21"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATIN<0> LOC ="AJ29"| IOSTANDARD = "LVTTL"; + # NET DSP_L1BCMPO LOC ="AJ20"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATOP<0> LOC ="AK21"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATON<0> LOC ="AM23"| IOSTANDARD = "LVTTL"; + # NET DSP_L0ACKO LOC ="AM17"| IOSTANDARD = "LVTTL"; + # NET DSP_L1CLKINN LOC ="AL30"| IOSTANDARD = "LVTTL"; + # NET DSP_L1CLKOUTP LOC ="K18"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATIN<0> LOC ="AM25"| IOSTANDARD = "LVTTL"; + # NET DSP_L0CLKINP LOC ="AP29"| IOSTANDARD = "LVTTL"; + # NET DSP_L1CLKOUTN LOC ="K17"| IOSTANDARD = "LVTTL"; + # NET DSP_L1BCMPI LOC ="AL15"| IOSTANDARD = "LVTTL"; + # NET DSP_L0CLKOUTN LOC ="AL25"| IOSTANDARD = "LVTTL"; + # NET DSP_L1CLKINP LOC ="AM30"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATOP<0> LOC ="AL23"| IOSTANDARD = "LVTTL"; + # NET DSP_L1ACKI LOC ="AD20"| IOSTANDARD = "LVTTL"; + # NET DSP_L0CLKINN LOC ="AN29"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATIP<0> LOC ="AN25"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATON<0> LOC ="AL21"| IOSTANDARD = "LVTTL"; + # NET DSP_L0CLKOUTP LOC ="AL24"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATIN<1> LOC ="AN24"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATIP<1> LOC ="AF28"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATIN<1> LOC ="AE27"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATON<1> LOC ="AN23"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATOP<1> LOC ="AN22"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATOP<1> LOC ="AH28"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATIP<1> LOC ="AP24"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATON<1> LOC ="AH29"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATON<2> LOC ="AH25"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATOP<2> LOC ="AJ25"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATIP<2> LOC ="AF26"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATOP<2> LOC ="AP30"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATIP<2> LOC ="AM26"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATIN<2> LOC ="AE26"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATON<2> LOC ="AN30"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATIN<2> LOC ="AM27"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATIP<3> LOC ="AN32"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATIP<3> LOC ="AP21"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATOP<3> LOC ="AL26"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATIN<3> LOC ="AP22"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATON<3> LOC ="AG28"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATOP<3> LOC ="AG27"| IOSTANDARD = "LVTTL"; + # NET DSP_L1DATIN<3> LOC ="AN33"| IOSTANDARD = "LVTTL"; + # NET DSP_L0DATON<3> LOC ="AK26"| IOSTANDARD = "LVTTL"; + # NET DSP_MSH LOC ="AL14"| IOSTANDARD = "LVTTL"; + NET DSP_RD LOC ="AJ22"| IOSTANDARD = "LVTTL"; + NET DSP_RESET LOC ="AG22"| IOSTANDARD = "LVTTL"; + NET DSP_RESET_OUT LOC ="AH22"| IOSTANDARD = "LVTTL"; + # NET DSP_TMROE LOC ="AP20"| IOSTANDARD = "LVTTL"; + NET DSP_WRH LOC ="AJ21"| IOSTANDARD = "LVTTL"; + NET DSP_WRL LOC ="AC15"| IOSTANDARD = "LVTTL"; + NET DWAIT LOC ="H33"| IOSTANDARD = "LVTTL"; + # NET D_CS1B LOC ="M2"| IOSTANDARD = "LVTTL"; + # NET D_CS<1> LOC ="M3"| IOSTANDARD = "LVTTL"; + # NET D_DATA_READY LOC ="E11"| IOSTANDARD = "LVTTL"; + # NET D_RESERVED LOC ="G8"| IOSTANDARD = "LVTTL"; + # NET D_SCK LOC ="M6"| IOSTANDARD = "LVTTL"; + # NET D_SCKB LOC ="M5"| IOSTANDARD = "LVTTL"; + # NET D_SDI LOC ="K3"| IOSTANDARD = "LVTTL"; + # NET D_SDIB LOC ="L3"| IOSTANDARD = "LVTTL"; + # NET D_SDO LOC ="K2"| IOSTANDARD = "LVTTL"; + # NET D_SDOB LOC ="K1"| IOSTANDARD = "LVTTL"; + # NET D_TDC_BU_RESET LOC ="K6"; + # NET D_TDC_BU_RESETB LOC ="L6"; + # NET D_TDC_ERROR LOC ="H12"| IOSTANDARD = "LVTTL"; + # NET D_TDC_EV_RESET LOC ="L8"; + # NET D_TDC_EV_RESETB LOC ="M8"; + # NET D_TDC_POWERUP LOC ="J7"| IOSTANDARD = "LVTTL"; + # NET D_TEMP LOC ="C14"| IOSTANDARD = "LVTTL"; + # NET D_TEST1B LOC ="M1"| IOSTANDARD = "LVTTL"; + # NET D_TEST2B LOC ="P5"| IOSTANDARD = "LVTTL"; + # NET D_TEST<1> LOC ="L1"| IOSTANDARD = "LVTTL"; + # NET D_TEST<2> LOC ="N5"| IOSTANDARD = "LVTTL"; + # NET D_TRIGGER LOC ="P12"; + # NET D_TRIGGERB LOC ="P11"; + NET ETRAX_IRQ LOC ="AK12"| IOSTANDARD = "LVTTL"; + NET FS_PB<0> LOC ="AL5"| IOSTANDARD = "LVTTL"; + NET FS_PB<1> LOC ="AL4"| IOSTANDARD = "LVTTL"; + NET FS_PB<2> LOC ="AK4"| IOSTANDARD = "LVTTL"; + NET FS_PB<3> LOC ="AJ4"| IOSTANDARD = "LVTTL"; + NET FS_PB<4> LOC ="AP4"| IOSTANDARD = "LVTTL"; + NET FS_PB<5> LOC ="AN4"| IOSTANDARD = "LVTTL"; + NET FS_PB<6> LOC ="AD10"| IOSTANDARD = "LVTTL"; + NET FS_PB<7> LOC ="AD9"| IOSTANDARD = "LVTTL"; + NET FS_PB<8> LOC ="AN14"| IOSTANDARD = "LVTTL"; + NET FS_PB<9> LOC ="AP14"| IOSTANDARD = "LVTTL"; + NET FS_PB<10> LOC ="AJ6"| IOSTANDARD = "LVTTL"; + NET FS_PB<11> LOC ="AJ5"| IOSTANDARD = "LVTTL"; + NET FS_PB<12> LOC ="AK7"| IOSTANDARD = "LVTTL"; + NET FS_PB<13> LOC ="AJ7"| IOSTANDARD = "LVTTL"; + NET FS_PB<14> LOC ="AN3"| IOSTANDARD = "LVTTL"; + NET FS_PB<15> LOC ="AN2"| IOSTANDARD = "LVTTL"; + NET FS_PB<16> LOC ="AK13"| IOSTANDARD = "LVTTL"; + NET FS_PB<17> LOC ="AL13"| IOSTANDARD = "LVTTL"; + NET FS_PC<0> LOC ="AL6"| IOSTANDARD = "LVTTL"; + NET FS_PC<1> LOC ="AK6"| IOSTANDARD = "LVTTL"; + NET FS_PC<2> LOC ="AL8"| IOSTANDARD = "LVTTL"; + NET FS_PC<3> LOC ="AK8"| IOSTANDARD = "LVTTL"; + NET FS_PC<4> LOC ="AH8"| IOSTANDARD = "LVTTL"; + NET FS_PC<5> LOC ="AH7"| IOSTANDARD = "LVTTL"; + NET FS_PC<6> LOC ="AM13"| IOSTANDARD = "LVTTL"; + NET FS_PC<7> LOC ="AN13"| IOSTANDARD = "LVTTL"; + NET FS_PC<8> LOC ="AM6"| IOSTANDARD = "LVTTL"; + NET FS_PC<9> LOC ="AM5"| IOSTANDARD = "LVTTL"; + NET FS_PC<10> LOC ="AJ10"| IOSTANDARD = "LVTTL"; + NET FS_PC<11> LOC ="AJ9"| IOSTANDARD = "LVTTL"; + NET FS_PC<12> LOC ="AP5"| IOSTANDARD = "LVTTL"; + NET FS_PC<13> LOC ="AN5"| IOSTANDARD = "LVTTL"; + NET FS_PC<14> LOC ="AP6"| IOSTANDARD = "LVTTL"; + NET FS_PC<15> LOC ="AP7"| IOSTANDARD = "LVTTL"; + NET FS_PC<16> LOC ="AM8"| IOSTANDARD = "LVTTL"; + NET FS_PC<17> LOC ="AN8"| IOSTANDARD = "LVTTL"; + # NET FS_PE<0> LOC ="V18"| IOSTANDARD = "LVTTL"; + # NET FS_PE<1> LOC ="V13"| IOSTANDARD = "LVTTL"; + # NET FS_PE<2> LOC ="V14"| IOSTANDARD = "LVTTL"; + # NET FS_PE<3> LOC ="W17"| IOSTANDARD = "LVTTL"; + # NET GET_DATA LOC ="B13"| IOSTANDARD = "LVTTL"; + # NET GND LOC ="V22"| IOSTANDARD = "LVTTL"; + # NET N<18064815> LOC ="T16"| IOSTANDARD = "LVTTL"; + # NET N<18064816> LOC ="U17"| IOSTANDARD = "LVTTL"; + # NET N<18064817> LOC ="U21"| IOSTANDARD = "LVTTL"; + # NET N<18064818> LOC ="Y18"| IOSTANDARD = "LVTTL"; + # NET N<18064820> LOC ="T18"| IOSTANDARD = "LVTTL"; + # NET N<23483794> LOC ="W20"| IOSTANDARD = "LVTTL"; + # NET N<23492722> LOC ="V20"| IOSTANDARD = "LVTTL"; + # NET N<23538587> LOC ="U22"| IOSTANDARD = "LVTTL"; + # NET N<23548060> LOC ="R17"| IOSTANDARD = "LVTTL"; + # NET N<23548615> LOC ="U15"| IOSTANDARD = "LVTTL"; + # NET N<24265542> LOC ="W21"| IOSTANDARD = "LVTTL"; + # NET N<24267225> LOC ="U13"| IOSTANDARD = "LVTTL"; + # NET N<24269436> LOC ="F15"| IOSTANDARD = "LVTTL"; + # NET N<24269444> LOC ="D15"| IOSTANDARD = "LVTTL"; + # NET N<24326445> LOC ="AJ11"| IOSTANDARD = "LVTTL"; + # NET N<24328654> LOC ="AK11"| IOSTANDARD = "LVTTL"; + # NET N<33988559> LOC ="J31"| IOSTANDARD = "LVTTL"; + # NET N<33988561> LOC ="K31"| IOSTANDARD = "LVTTL"; + # NET N<34495448> LOC ="E22"| IOSTANDARD = "LVTTL"; + # NET N<34503651> LOC ="D22"| IOSTANDARD = "LVTTL"; + # NET N<36044982> LOC ="AK17"| IOSTANDARD = "LVTTL"; + # NET N<36648023> LOC ="AG18"| IOSTANDARD = "LVTTL"; + # NET N<36648025> LOC ="AG17"| IOSTANDARD = "LVTTL"; + # NET N<36648033> LOC ="AE17"| IOSTANDARD = "LVTTL"; + # NET N<36648035> LOC ="AE16"| IOSTANDARD = "LVTTL"; + # NET N<36650772> LOC ="AJ17"| IOSTANDARD = "LVTTL"; + # NET N<36650774> LOC ="AH17"| IOSTANDARD = "LVTTL"; + # NET N<36704661> LOC ="AN28"| IOSTANDARD = "LVTTL"; + # NET N<36704663> LOC ="AM28"| IOSTANDARD = "LVTTL"; + # NET N<38694350> LOC ="AG5"| IOSTANDARD = "LVTTL"; + # NET N<38697708> LOC ="AG6"| IOSTANDARD = "LVTTL"; + # NET N<38810822> LOC ="K19"| IOSTANDARD = "LVTTL"; + # NET N<38810824> LOC ="J19"| IOSTANDARD = "LVTTL"; + # NET N<38810850> LOC ="E16"| IOSTANDARD = "LVTTL"; + # NET N<38810852> LOC ="F16"| IOSTANDARD = "LVTTL"; + # NET N<38813734> LOC ="G13"| IOSTANDARD = "LVTTL"; + # NET N<38813742> LOC ="M17"| IOSTANDARD = "LVTTL"; + # NET N<38813744> LOC ="N17"| IOSTANDARD = "LVTTL"; + # NET N<38813770> LOC ="M18"| IOSTANDARD = "LVTTL"; + # NET N<38813772> LOC ="L18"| IOSTANDARD = "LVTTL"; + # NET N<38813774> LOC ="F13"| IOSTANDARD = "LVTTL"; + # NET N<38821674> LOC ="D19"| IOSTANDARD = "LVTTL"; + # NET N<38821676> LOC ="C19"| IOSTANDARD = "LVTTL"; + # NET N<38821684> LOC ="C18"| IOSTANDARD = "LVTTL"; + # NET N<38821698> LOC ="C17"| IOSTANDARD = "LVTTL"; + # NET N<38821700> LOC ="D17"| IOSTANDARD = "LVTTL"; + # NET N<38821702> LOC ="E19"| IOSTANDARD = "LVTTL"; + # NET N<38824618> LOC ="C15"| IOSTANDARD = "LVTTL"; + # NET N<38824620> LOC ="M16"| IOSTANDARD = "LVTTL"; + # NET N<38824628> LOC ="N15"| IOSTANDARD = "LVTTL"; + # NET N<38824642> LOC ="D20"| IOSTANDARD = "LVTTL"; + # NET N<38824644> LOC ="C20"| IOSTANDARD = "LVTTL"; + # NET N<38824646> LOC ="D16"| IOSTANDARD = "LVTTL"; + # NET N<38827574> LOC ="A20"| IOSTANDARD = "LVTTL"; + # NET N<38827602> LOC ="B20"| IOSTANDARD = "LVTTL"; + # NET N<38857742> LOC ="AH23"| IOSTANDARD = "LVTTL"; + # NET N<38857748> LOC ="AH24"| IOSTANDARD = "LVTTL"; + # NET N<41716249> LOC ="W19"| IOSTANDARD = "LVTTL"; + # NET N<44929647> LOC ="J2"| IOSTANDARD = "LVTTL"; + # NET N<44929649> LOC ="J1"| IOSTANDARD = "LVTTL"; + # NET N<44985997> LOC ="J17"| IOSTANDARD = "LVTTL"; + # NET N<44986035> LOC ="H17"| IOSTANDARD = "LVTTL"; + # NET N<45004261> LOC ="AK19"| IOSTANDARD = "LVTTL"; + # NET N<45004289> LOC ="AJ19"| IOSTANDARD = "LVTTL"; + # NET N<45476888> LOC ="K16"| IOSTANDARD = "LVTTL"; + # NET N<45476902> LOC ="L16"| IOSTANDARD = "LVTTL"; + # NET N<46190669> LOC ="E18"| IOSTANDARD = "LVTTL"; + # NET N<46190671> LOC ="E17"| IOSTANDARD = "LVTTL"; + # NET N<46461605> LOC ="E8"| IOSTANDARD = "LVTTL"; + # NET N<46464939> LOC ="E7"| IOSTANDARD = "LVTTL"; + # NET N<46481442> LOC ="AD19"| IOSTANDARD = "LVTTL"; + # NET N<46481444> LOC ="AE19"| IOSTANDARD = "LVTTL"; + # NET N<46736961> LOC ="AC25"| IOSTANDARD = "LVTTL"; + # NET N<46741878> LOC ="AD26"| IOSTANDARD = "LVTTL"; + # NET REF_TDC_CLK LOC ="F18"; + # NET REF_TDC_CLKB LOC ="G18"; + NET RESET_VIRT LOC ="AF16"| IOSTANDARD = "LVTTL"; + NET SFP_LOS LOC ="M27"| IOSTANDARD = "LVTTL"; + # NET SFP_MOD<0> LOC ="R23"| IOSTANDARD = "LVTTL"; + # NET SFP_MOD<1> LOC ="K32"| IOSTANDARD = "LVTTL"; + # NET SFP_MOD<2> LOC ="K33"| IOSTANDARD = "LVTTL"; + # NET SFP_RATE_SEL LOC ="P27"| IOSTANDARD = "LVTTL"; + NET SFP_TX_DIS LOC ="N27"| IOSTANDARD = "LVTTL"; + # NET SFP_TX_FAULT LOC ="J32"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<0> LOC ="D12"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<1> LOC ="C12"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<2> LOC ="B10"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<3> LOC ="C10"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<4> LOC ="A11"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<5> LOC ="B11"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<6> LOC ="C9"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<7> LOC ="C8"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<8> LOC ="G12"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<9> LOC ="G11"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<10> LOC ="F10"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<11> LOC ="G10"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<12> LOC ="D11"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<13> LOC ="D10"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<14> LOC ="H10"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<15> LOC ="H9"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<16> LOC ="A14"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<17> LOC ="A13"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<18> LOC ="D7"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<19> LOC ="D6"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<20> LOC ="D9"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<21> LOC ="E9"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<22> LOC ="A4"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<23> LOC ="A3"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<24> LOC ="E13"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<25> LOC ="E12"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<26> LOC ="A5"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<27> LOC ="B5"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<28> LOC ="J9"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<29> LOC ="K9"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<30> LOC ="B3"| IOSTANDARD = "LVTTL"; + #NET TDC_OUT<31> LOC ="B2"| IOSTANDARD = "LVTTL"; + #NET TDC_RESET LOC ="C5"| IOSTANDARD = "LVTTL"; + NET TLK_CLK LOC ="AG16"| IOSTANDARD = "LVTTL"; + NET TLK_ENABLE LOC ="R24"| IOSTANDARD = "LVTTL"; + NET TLK_LCKREFN LOC ="L28"| IOSTANDARD = "LVTTL"; + NET TLK_LOOPEN LOC ="R19"| IOSTANDARD = "LVTTL"; + NET TLK_PRBSEN LOC ="H32"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<0> LOC ="G30"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<1> LOC ="G31"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<2> LOC ="J29"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<3> LOC ="J30"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<4> LOC ="E32"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<5> LOC ="E33"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<6> LOC ="N25"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<7> LOC ="P26"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<8> LOC ="P22"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<9> LOC ="R21"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<10> LOC ="F33"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<11> LOC ="F34"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<12> LOC ="K28"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<13> LOC ="K29"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<14> LOC ="G32"| IOSTANDARD = "LVTTL"; + NET TLK_RXD<15> LOC ="G33"| IOSTANDARD = "LVTTL"; + NET TLK_RX_CLK LOC ="AF18"| IOSTANDARD = "LVTTL"; + NET TLK_RX_DV LOC ="M30"| IOSTANDARD = "LVTTL"; + NET TLK_RX_ER LOC ="P20"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<0> LOC ="H27"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<1> LOC ="H28"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<2> LOC ="C32"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<3> LOC ="D32"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<4> LOC ="J27"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<5> LOC ="K27"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<6> LOC ="M25"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<7> LOC ="M26"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<8> LOC ="N22"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<9> LOC ="N23"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<10> LOC ="H29"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<11> LOC ="H30"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<12> LOC ="C33"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<13> LOC ="C34"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<14> LOC ="D34"| IOSTANDARD = "LVTTL"; + NET TLK_TXD<15> LOC ="E34"| IOSTANDARD = "LVTTL"; + NET TLK_TX_EN LOC ="L29"| IOSTANDARD = "LVTTL"; + NET TLK_TX_ER LOC ="P24"| IOSTANDARD = "LVTTL"; + # NET TOKEN_IN LOC ="E6"| IOSTANDARD = "LVTTL"; + # NET TOKEN_OUT LOC ="C13"| IOSTANDARD = "LVTTL"; + NET VIRT_CLK LOC ="H19"; + NET VIRT_CLKB LOC ="H18"; + # NET VIRT_TCK LOC ="K34"| IOSTANDARD = "LVTTL"; + # NET VIRT_TDI LOC ="M31"| IOSTANDARD = "LVTTL"; + # NET VIRT_TDO LOC ="N30"| IOSTANDARD = "LVTTL"; + # NET VIRT_TMS LOC ="J34"| IOSTANDARD = "LVTTL"; + # NET VIRT_TRST LOC ="N29"| IOSTANDARD = "LVTTL"; + # NET VIR_TRIG LOC ="E3"; + # NET VIR_TRIGB LOC ="E2"; + NET VSD_A<0> LOC ="F23"| IOSTANDARD = "LVTTL"; + NET VSD_A<1> LOC ="E23"| IOSTANDARD = "LVTTL"; + NET VSD_A<2> LOC ="D26"| IOSTANDARD = "LVTTL"; + NET VSD_A<3> LOC ="E26"| IOSTANDARD = "LVTTL"; + NET VSD_A<4> LOC ="F24"| IOSTANDARD = "LVTTL"; + NET VSD_A<5> LOC ="E24"| IOSTANDARD = "LVTTL"; + NET VSD_A<6> LOC ="D27"| IOSTANDARD = "LVTTL"; + NET VSD_A<7> LOC ="E27"| IOSTANDARD = "LVTTL"; + NET VSD_A<8> LOC ="G23"| IOSTANDARD = "LVTTL"; + NET VSD_A<9> LOC ="H24"| IOSTANDARD = "LVTTL"; + NET VSD_A<10> LOC ="A28"| IOSTANDARD = "LVTTL"; + NET VSD_A<11> LOC ="A29"| IOSTANDARD = "LVTTL"; + NET VSD_A<12> LOC ="B25"| IOSTANDARD = "LVTTL"; + NET VSD_BA<0> LOC ="C25"| IOSTANDARD = "LVTTL"; + NET VSD_BA<1> LOC ="J25"| IOSTANDARD = "LVTTL"; + NET VSD_CAS LOC ="G28"| IOSTANDARD = "LVTTL"; + NET VSD_CKE LOC ="D30"| IOSTANDARD = "LVTTL"; + NET VSD_CLOCK LOC ="B28"| IOSTANDARD = "LVTTL"; + NET VSD_CSEH LOC ="G27"| IOSTANDARD = "LVTTL"; + NET VSD_CSEL LOC ="D31"| IOSTANDARD = "LVTTL"; + NET VSD_D<0> LOC ="B23"| IOSTANDARD = "LVTTL"; + NET VSD_D<1> LOC ="A23"| IOSTANDARD = "LVTTL"; + NET VSD_D<2> LOC ="A26"| IOSTANDARD = "LVTTL"; + NET VSD_D<3> LOC ="B26"| IOSTANDARD = "LVTTL"; + NET VSD_D<4> LOC ="A24"| IOSTANDARD = "LVTTL"; + NET VSD_D<5> LOC ="A25"| IOSTANDARD = "LVTTL"; + NET VSD_D<6> LOC ="G25"| IOSTANDARD = "LVTTL"; + NET VSD_D<7> LOC ="H25"| IOSTANDARD = "LVTTL"; + NET VSD_D<8> LOC ="C23"| IOSTANDARD = "LVTTL"; + NET VSD_D<9> LOC ="C24"| IOSTANDARD = "LVTTL"; + NET VSD_D<10> LOC ="F25"| IOSTANDARD = "LVTTL"; + NET VSD_D<11> LOC ="F26"| IOSTANDARD = "LVTTL"; + NET VSD_D<12> LOC ="D24"| IOSTANDARD = "LVTTL"; + NET VSD_D<13> LOC ="D25"| IOSTANDARD = "LVTTL"; + NET VSD_D<14> LOC ="B27"| IOSTANDARD = "LVTTL"; + NET VSD_D<15> LOC ="C27"| IOSTANDARD = "LVTTL"; + NET VSD_D<16> LOC ="C22"| IOSTANDARD = "LVTTL"; + NET VSD_D<17> LOC ="B22"| IOSTANDARD = "LVTTL"; + NET VSD_D<18> LOC ="A30"| IOSTANDARD = "LVTTL"; + NET VSD_D<19> LOC ="B30"| IOSTANDARD = "LVTTL"; + NET VSD_D<20> LOC ="K24"| IOSTANDARD = "LVTTL"; + NET VSD_D<21> LOC ="J24"| IOSTANDARD = "LVTTL"; + NET VSD_D<22> LOC ="C29"| IOSTANDARD = "LVTTL"; + NET VSD_D<23> LOC ="C30"| IOSTANDARD = "LVTTL"; + NET VSD_D<24> LOC ="B21"| IOSTANDARD = "LVTTL"; + NET VSD_D<25> LOC ="A21"| IOSTANDARD = "LVTTL"; + NET VSD_D<26> LOC ="E28"| IOSTANDARD = "LVTTL"; + NET VSD_D<27> LOC ="F28"| IOSTANDARD = "LVTTL"; + NET VSD_D<28> LOC ="A31"| IOSTANDARD = "LVTTL"; + NET VSD_D<29> LOC ="B31"| IOSTANDARD = "LVTTL"; + NET VSD_D<30> LOC ="E31"| IOSTANDARD = "LVTTL"; + NET VSD_D<31> LOC ="F31"| IOSTANDARD = "LVTTL"; + NET VSD_DQML<0> LOC ="F30"| IOSTANDARD = "LVTTL"; + NET VSD_DQML<1> LOC ="D29"| IOSTANDARD = "LVTTL"; + NET VSD_DQML<2> LOC ="E29"| IOSTANDARD = "LVTTL"; + NET VSD_DQML<3> LOC ="L25"| IOSTANDARD = "LVTTL"; + NET VSD_RAS LOC ="F29"| IOSTANDARD = "LVTTL"; + NET VSD_WE LOC ="K26"| IOSTANDARD = "LVTTL"; + OFFSET=OUT 19.0 ns AFTER "VIRT_CLK" HIGH; + OFFSET=IN 3.5 ns BEFORE "VIRT_CLK" HIGH; +# OFFSET=IN 2.5 ns BEFORE "REF_TDC_CLK" HIGH; + NET "VIRT_CLK" TNM_NET =VIRT_CLK; + TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9 ns; + +NET "ADO_CLK2" TNM_NET =ADO_CLK2; +TIMESPEC TS_ADO_CLK2 =PERIOD "ADO_CLK2" 16 ns; + +#NET "REF_TDC_CLK" TNM_NET = REF_TDC_CLK; +#TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 10 ns; diff --git a/trb_cts/cts.vhd b/trb_cts/cts.vhd new file mode 100644 index 0000000..e3de16d --- /dev/null +++ b/trb_cts/cts.vhd @@ -0,0 +1,1041 @@ +library IEEE; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.all; +library ieee; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.all; + +entity cts is + port ( + ------------------------------------------------------------------------- + -- GENERAL + ------------------------------------------------------------------------- + VIRT_CLK : in std_logic; + VIRT_CLKB : in std_logic; + RESET_VIRT : in std_logic; + DBAD : out std_logic; --diode + DGOOD : out std_logic; --diode + DINT : out std_logic; --diode + DWAIT : out std_logic; --diode + ------------------------------------------------------------------------- + -- ETRAX connections + ------------------------------------------------------------------------- + FS_PB : out std_logic_vector (17 downto 0); + FS_PC : inout std_logic_vector (17 downto 0); + ETRAX_IRQ : out std_logic; --check what is the correct value + ------------------------------------------------------------------------- + -- TEST SIGNALS - for RPC + ------------------------------------------------------------------------- + -- A_TEST1B LOC = N7; + -- A_TEST2B LOC = L4; + -- A_TEST1 LOC = M7; + -- A_TEST2 LOC = L5; + -- B_TEST2B LOC = L9; + -- B_TEST1B LOC = E4; + -- B_TEST1 LOC = D4; + -- B_TEST2 LOC = M10; + -- C_TEST2B LOC = N12; + -- C_TEST1B LOC = D2; + -- C_TEST<1> LOC = C2; + -- C_TEST<2> LOC = N13; + -- D_TEST1B LOC = M1; + -- D_TEST2B LOC = P5; + -- D_TEST<1> LOC = L1; + -- D_TEST<2> LOC = N5; + ------------------------------------------------------------------------- + -- SHARC + ------------------------------------------------------------------------- + DSPADDR : out std_logic_vector (31 downto 0); + DSPDAT : inout std_logic_vector (31 downto 0); + DSP_ACK : in std_logic; + DSP_BM : inout std_logic; + DSP_BMS : out std_logic; --LOC = AF15; + DSP_BOFF : out std_logic; -- LOC = AK14; + DSP_BRST : inout std_logic; + DSP_HBG : in std_logic; + DSP_HBR : out std_logic; + DSP_IRQ : out std_logic_vector (3 downto 0); +-- --link0 +-- DSP_L0DATIP : out std_logic_vector (3 downto 0); +-- DSP_L0DATIN : out std_logic_vector (3 downto 0); +-- DSP_L0DATOP : in std_logic_vector (3 downto 0); +-- DSP_L0DATON : in std_logic_vector (3 downto 0); +-- DSP_L0CLKINP : out std_logic; +-- DSP_L0CLKINN : out std_logic; +-- DSP_L0CLKOUTP : in std_logic; +-- DSP_L0CLKOUTN : in std_logic; +-- DSP_L0BCMPO : in std_logic; +-- DSP_L0ACKO : in std_logic; +-- DSP_L0BCMPI : out std_logic; +-- DSP_L0ACKI : out std_logic; +-- --link1 +-- DSP_L1DATIP : out std_logic_vector (3 downto 0); +-- DSP_L1DATIN : out std_logic_vector (3 downto 0); +-- DSP_L1DATOP : in std_logic_vector (3 downto 0); +-- DSP_L1DATON : in std_logic_vector (3 downto 0); +-- DSP_L1CLKINP : out std_logic; +-- DSP_L1CLKINN : out std_logic; +-- DSP_L1CLKOUTP : in std_logic; +-- DSP_L1CLKOUTN : in std_logic; +-- DSP_L1ACKO : in std_logic; +-- DSP_L1BCMPO : in std_logic; +-- DSP_L1BCMPI : out std_logic; +-- DSP_L1ACKI : out std_logic; +-- DSP_TMROE : LOC = AP20; --link data widt now is 4 bit --pullup + DSP_RD : out std_logic; + DSP_RESET : out std_logic; + DSP_RESET_OUT : in std_logic; + DSP_WRH : out std_logic; + DSP_WRL : out std_logic; + -- DSP_MSH LOC = AL14; + -- DSP_IOEN LOC = AL18; + -- DSP_IORD LOC = AB16; + -- DSP_IOWR LOC = AB17; + -- DSP_BUSLOCK LOC = AC19; + -- DSP_DMAR : std_logic_vector (3 downto 0); + -- DSP_FLAG : std_logic_vector (3 downto 0); + ------------------------------------------------------------------------- + -- SDRAM + ------------------------------------------------------------------------- + VSD_A : out std_logic_vector (12 downto 0); + VSD_BA : out std_logic_vector (1 downto 0); + VSD_CAS : out std_logic; + VSD_CKE : out std_logic; + VSD_CLOCK : out std_logic; + VSD_CSEH : out std_logic; + VSD_CSEL : out std_logic; + VSD_D : inout std_logic_vector (31 downto 0); + VSD_DQML : out std_logic_vector (3 downto 0); + VSD_RAS : out std_logic; + VSD_WE : out std_logic; + ------------------------------------------------------------------------- + -- TLK + ------------------------------------------------------------------------- + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector (15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector (15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + ------------------------------------------------------------------------- + -- SFP + ------------------------------------------------------------------------- + SFP_LOS : in std_logic; + -- SFP_MOD<0> LOC = R23; + -- SFP_MOD<1> LOC = K32; + -- SFP_MOD<2> LOC = K33; + -- SFP_RATE_SEL : out std_logic; + SFP_TX_DIS : out std_logic; + SFP_TX_FAULT : in std_logic; + ------------------------------------------------------------------------- + -- ADDON board + ------------------------------------------------------------------------- +-- ADDON_TO_TRB_CLKINN : in std_logic; +-- ADDON_TO_TRB_CLKINP : in std_logic; + ADO_CLK1 : in std_logic; + ADO_CLK2 : in std_logic; + ADO_LV : in std_logic_vector(51 downto 0); --lvds signal + ADO_TTL : inout std_logic_vector(46 downto 2) + ); + end cts; +architecture cts of cts is + component etrax_interface + port ( + CLK : in std_logic; + RESET : in std_logic; + DATA_BUS : in std_logic_vector(31 downto 0); + ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0); + ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0); + DATA_VALID : in std_logic; + ETRAX_BUS_BUSY : out std_logic; + ETRAX_IS_READY_TO_READ : out std_logic; + TDC_TCK : out std_logic; + TDC_TDI : out std_logic; + TDC_TMS : out std_logic; + TDC_TRST : out std_logic; + TDC_TDO : in std_logic; + TDC_RESET : out std_logic; + EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); + EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); + EXTERNAL_ACK : out std_logic; + EXTERNAL_VALID : in std_logic; + EXTERNAL_MODE : out std_logic_vector(15 downto 0); + FPGA_REGISTER_00 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_01 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_02 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_03 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_04 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_05 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_06 : out std_logic_vector(31 downto 0); + FPGA_REGISTER_07 : out std_logic_vector(31 downto 0); + FPGA_REGISTER_08 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_09 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0A : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); + EXTERNAL_RESET : out std_logic; + LVL2_VALID : in std_logic + ); + end component; + component trb_net16_endpoint_0_trg_1_api + generic ( + API_TYPE : integer range 0 to 1; + INIT_DEPTH : integer range 0 to 6; + REPLY_DEPTH : integer range 0 to 6; + FIFO_TO_INT_DEPTH : integer range 0 to 6; + FIFO_TO_APL_DEPTH : integer range 0 to 6; + SBUF_VERSION : integer range 0 to 1; + MUX_WIDTH : integer range 1 to 5; + MUX_SECURE_MODE : integer range 0 to 1; + DAT_CHANNEL : integer range 0 to 3; + DATA_WIDTH : integer; + NUM_WIDTH : integer); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (15 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (15 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + APL_DATA_IN : in std_logic_vector (15 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0); + APL_WRITE_IN : in std_logic; + APL_FIFO_FULL_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_DATA_OUT : out std_logic_vector (15 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_LOCKED : out std_logic_vector (31 downto 0); + STAT_INIT_BUFFER : out std_logic_vector (31 downto 0); + STAT_REPLY_BUFFER : out std_logic_vector (31 downto 0); + STAT_api_control_signals : out std_logic_vector(31 downto 0); + STAT_MPLEX : out std_logic_vector(31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + CTRL_LOCKED : in std_logic_vector (31 downto 0); + STAT_CTRL_INIT_BUFFER : in std_logic_vector (31 downto 0); + STAT_CTRL_REPLY_BUFFER : in std_logic_vector (31 downto 0); + MPLEX_CTRL : in std_logic_vector (31 downto 0); + API_STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + API_STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)); + end component; + component trbv2_tlk_api + port ( + RESET : in std_logic; + CLK : in std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector(15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector(15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_VALID_OUT : out std_logic; + TLK_API_REGISTER_00 : out std_logic_vector(31 downto 0)); + end component; + component vulom_interface + port ( + CLK : in std_logic; + DATA_CLK : in std_logic; + RESET : in std_logic; + DATA_IN : in std_logic_vector(1 downto 0); + BUSY : out std_logic; + API_DATA : out std_logic_vector(47 downto 0); + API_RUN_OUT : in std_logic; + API_SHORT_TRANSFER : out std_logic; + API_DTYPE : out std_logic_vector(3 downto 0); + API_SEND : out std_logic; + API_WRITE_IN : out std_logic; + API_TARGET_ADDRESS : out std_logic_vector(15 downto 0); + API_SEQNR_OUT : in std_logic_vector(7 downto 0); + VULOM_INT_REG : out std_logic_vector(31 downto 0); + INTERFACE_CONTROL : in std_logic_vector(3 downto 0); + EVENT_REGISTER_00 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_01 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_02 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_03 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_04 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_05 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_06 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_07 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_08 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_09 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_0a : out std_logic_vector(31 downto 0); + EVENT_REGISTER_0b : out std_logic_vector(31 downto 0); + EVENT_REGISTER_0c : out std_logic_vector(31 downto 0); + START_READOUT : out std_logic; + LVL1_TRANSFER_BUSY : in std_logic + ); + end component; + component dsp_interface + port ( + -- signal to/from dsp + HBR_OUT : out std_logic; -- Host Bus Request to DSP + HBG_IN : in std_logic; -- Host Bus Grant from DSP + RD_OUT : out std_logic; -- read/write enable of DSP + DSP_DATA_OUT : out std_logic_vector(31 downto 0); + DSP_DATA_IN : in std_logic_vector(31 downto 0); + ADDRESS_DSP : out std_logic_vector(31 downto 0); + WRL : out std_logic; --when dsp slave is output + WRH : out std_logic; --when dsp slave is output + BM_IN : in std_logic; --Bus Master. For debug + DSP_RESET : out std_logic; + BRST : inout std_logic; + ACK : in std_logic; + --internal data and address bus + CLK : in std_logic; + RESET : in std_logic; + R_W_ENABLE : in std_logic; + TRIGGER : in std_logic; + INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); --63 downto 0 + INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); --63 downto 0 + INTERNAL_ADDRESS : in std_logic_vector(31 downto 0); + VALID_DATA_SENT : out std_logic; + ACKNOWLEDGE : in std_logic; + DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0) + ); + end component; + component dtu_interface + port ( + CLK : in std_logic; + RESET : in std_logic; + LVL1_TRIGGER_BUS : in std_logic; + LVL1_DATA_TRIGGER_BUS : in std_logic; + LVL1_DATA_BUS : in std_logic_vector(3 downto 0); + LVL1_ERROR_BUS : out std_logic; + LVL1_BUSY_BUS : out std_logic; + LVL1_TRIGGER : out std_logic; + LVL1_CODE : out std_logic_vector(3 downto 0); + LVL1_TAG : out std_logic_vector(7 downto 0); + LVL1_BUSY : in std_logic; + LVL2_TRIGGER_BUS : in std_logic; + LVL2_DATA_TRIGGER_BUS : in std_logic; + LVL2_DATA_BUS : in std_logic_vector(3 downto 0); + LVL2_ERROR_BUS : out std_logic; + LVL2_BUSY_BUS : out std_logic; + LVL2_TRIGGER : out std_logic; + LVL2_CODE : out std_logic_vector(3 downto 0); + LVL2_TAG : out std_logic_vector(7 downto 0); + LVL2_BUSY : in std_logic; + LVL2_TRB_ACK : in std_logic; + DTU_DEBUG_00 : out std_logic_vector( 31 downto 0)); + end component; + + component sdram_interface + port ( +--connection with sdram + CLK_SDRAM : out std_logic; + CKE : out std_logic; + CS : out std_logic; + RAS : out std_logic; + CAS : out std_logic; + WE : out std_logic; + DQM : out std_logic_vector(3 downto 0); + BA : out std_logic_vector (1 downto 0); + A : out std_logic_vector(12 downto 0); + DQ : inout std_logic_vector(31 downto 0); +--internal signals + CLK : in std_logic; + RESET : in std_logic; + TRIGGER : in std_logic; + INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); + INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + INTERNAL_ADDRESS : in std_logic_vector(31 downto 0); + INTERNAL_MODE : in std_logic_vector(15 downto 0); + VALID_DATA_SENT : out std_logic; + DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0) + ); + end component; + component fpga_to_etrax_data_flow + port ( + CLK : in std_logic; + RESET : in std_logic; + START_READOUT : in std_logic; + HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0); + COUNTER_0 : in std_logic_vector(31 downto 0); + COUNTER_1 : in std_logic_vector(31 downto 0); + COUNTER_2 : in std_logic_vector(31 downto 0); + COUNTER_3 : in std_logic_vector(31 downto 0); + COUNTER_4 : in std_logic_vector(31 downto 0); + COUNTER_5 : in std_logic_vector(31 downto 0); + COUNTER_6 : in std_logic_vector(31 downto 0); + COUNTER_7 : in std_logic_vector(31 downto 0); + COUNTER_8 : in std_logic_vector(31 downto 0); + COUNTER_9 : in std_logic_vector(31 downto 0); + COUNTER_a : in std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector (31 downto 0); + DATA_VALID : out std_logic; + ETRAX_IS_READY_TO_READ : in std_logic; + LVL1_BUSY : out std_logic; + CTS_ETRAX_REGISTER_00 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_01 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_02 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_03 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_04 : out std_logic_vector(31 downto 0)); + end component; + component simpleupcounter_32bit + port ( + QOUT : out std_logic_vector(31 downto 0); + UP : in std_logic; + CLK : in std_logic; + CLR : in std_logic); + end component; + + ----------------------------------------------------------------------------- + -- EDGE TO PULSE + ----------------------------------------------------------------------------- + component edge_to_pulse + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; +------------------------------------------------------------------------------- +-- SIGNALS +------------------------------------------------------------------------------- +--general + signal CLK : std_logic; + signal ADDON_CLK1 : std_logic; + signal ADDON_CLK2 : std_logic; + signal etrax_bus_busy_i : std_logic; --should go to busy logic !? + signal etrax_is_ready_to_read_i : std_logic; +--tlk + signal tlk_rx_clk_io : std_logic; + signal tlk_clk_io : std_logic; + signal tlk_rx_clk_r : std_logic; + signal tlk_clk_r : std_logic; + signal tlk_register_00_i : std_logic_vector(31 downto 0); + signal tlk_register_01_i : std_logic_vector(31 downto 0); + signal link_status_i : std_logic_vector(3 downto 0); +--dsp + signal dsp_register_00_i : std_logic_vector(31 downto 0); + signal dsp_strobe_i : std_logic; + signal dsp_external_valid_i : std_logic; + signal dsp_hbr_i : std_logic; + signal dspdat_out_i : std_logic_vector(31 downto 0); + signal dspdat_in_i : std_logic_vector(31 downto 0); + signal dsp_data_out_i : std_logic_vector(31 downto 0); + signal dspaddr_i : std_logic_vector(31 downto 0); + signal DSP_WRL_i: std_logic; + signal DSP_RD_i: std_logic; + signal dsp_data_reg_in_i : std_logic_vector(31 downto 0); + signal dsp_data_reg_out_i : std_logic_vector(31 downto 0); + signal dsp_bm_reg : std_logic; + signal dsp_link_data_in_0 : std_logic_vector(3 downto 0); + signal dsp_link_data_out_0 : std_logic_vector(3 downto 0); + signal dsp_link_clk_in_0 : std_logic; + signal dsp_link_clk_out_0 : std_logic; + signal dsp_link_data_in_1 : std_logic_vector(3 downto 0); + signal dsp_link_data_out_1 : std_logic_vector(3 downto 0); + signal dsp_link_clk_in_1 : std_logic; + signal dsp_link_clk_out_1 : std_logic; +--etrax <-> interface + signal external_address_i : std_logic_vector(31 downto 0); + signal external_data_in_i : std_logic_vector(31 downto 0); + signal external_data_out_i : std_logic_vector(31 downto 0); + signal external_ack_i : std_logic; + signal external_valid_i : std_logic; + signal external_mode_i : std_logic_vector(15 downto 0); + signal external_reset_i : std_logic; + signal external_reset : std_logic; +--registers + signal fpga_register_01_i : std_logic_vector(31 downto 0); + signal fpga_register_02_i : std_logic_vector(31 downto 0); + signal fpga_register_03_i : std_logic_vector(31 downto 0); + signal fpga_register_04_i : std_logic_vector(31 downto 0); + signal fpga_register_05_i : std_logic_vector(31 downto 0); + signal fpga_register_06_i : std_logic_vector(31 downto 0); + signal fpga_register_07_i : std_logic_vector(31 downto 0); + signal fpga_register_08_i : std_logic_vector(31 downto 0); + signal fpga_register_09_i : std_logic_vector(31 downto 0); + signal fpga_register_0a_i : std_logic_vector(31 downto 0); + signal fpga_register_0b_i : std_logic_vector(31 downto 0); + signal fpga_register_0c_i : std_logic_vector(31 downto 0); + signal fpga_register_0d_i : std_logic_vector(31 downto 0); +--lvds bus + signal lvds_add_on_data : std_logic_vector(31 downto 0); +--sdram + signal sdram_register_00_i : std_logic_vector(31 downto 0); + signal sdram_external_valid_i : std_logic; + signal sdram_data_out_i : std_logic_vector(31 downto 0); + signal vsd_cs_i : std_logic; + signal sdram_data_i : std_logic_vector(31 downto 0); + signal sdram_address_i : std_logic_vector(31 downto 0); +--api + signal med_packet_num_in_i : std_logic_vector(1 downto 0); + signal apl_run_out_i : std_logic; + signal apl_seqnr_out_i : std_logic_vector(7 downto 0); +--vulom interface + signal vulom_int_reg_00 : std_logic_vector(31 downto 0); + signal med_data_out_i_saved : std_logic_vector(63 downto 0); + signal TLK_TX_EN_i : std_logic; + signal TLK_TXD_i : std_logic_vector(15 downto 0); + signal TLK_CLK_i : std_logic; + signal trb_busy1 : std_logic; + signal trb_busy2 : std_logic; + signal busy1_pulse : std_logic; + signal busy2_pulse : std_logic; + signal busy_all : std_logic; + signal counter_0_i : std_logic_vector(31 downto 0); + signal counter_1_i : std_logic_vector(31 downto 0); + signal counter_2_i : std_logic_vector(31 downto 0); + signal counter_3_i : std_logic_vector(31 downto 0); + signal counter_4_i : std_logic_vector(31 downto 0); + signal counter_5_i : std_logic_vector(31 downto 0); + signal counter_6_i : std_logic_vector(31 downto 0); + signal counter_7_i : std_logic_vector(31 downto 0); + signal counter_8_i : std_logic_vector(31 downto 0); + signal counter_9_i : std_logic_vector(31 downto 0); + signal counter_a_i : std_logic_vector(31 downto 0); + signal counter_b_i : std_logic_vector(31 downto 0); + signal counter_c_i : std_logic_vector(31 downto 0); + signal start_readout_i : std_logic; + signal lvl1_busy_i : std_logic; + signal data_valid_i : std_logic; + signal data_out_i : std_logic_vector(31 downto 0); +--cts_etrax + signal cts_etrax_register_00_i : std_logic_vector(31 downto 0); + signal cts_etrax_register_01_i : std_logic_vector(31 downto 0); + signal cts_etrax_register_02_i : std_logic_vector(31 downto 0); + signal cts_etrax_register_03_i : std_logic_vector(31 downto 0); + signal cts_etrax_register_04_i : std_logic_vector(31 downto 0); + signal cts_etrax_register_05_i : std_logic_vector(31 downto 0); +--trbv2_med_api + signal media_data_valid_in_i : std_logic; + signal media_data_valid_out_i : std_logic; + signal media_data_out_i : std_logic_vector(15 downto 0); + signal media_data_in_i : std_logic_vector(15 downto 0); + signal tlk_api_register_00_i : std_logic_vector(31 downto 0); + + +begin + ------------------------------------------------------------------------------ + -- LVDS signals + ------------------------------------------------------------------------------ + -- CLK + IBUFGDS_CLK : IBUFGDS + generic map ( + IOSTANDARD => "LVDS_25_DCI") + port map ( + O => CLK,--CLK, + I => VIRT_CLK, + IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port) + ); + ADDON_BUFG : BUFR + port map( + CE => '1', + CLR => '0', + I => ADO_CLK2, + O => ADDON_CLK2 + ); + -- ADD_LVDS + + LVDS_ADO_SIGNAL: for lvds_line in 0 to 25 generate + IBUFDS_LVDS_0 : IBUFDS + generic map ( + IOSTANDARD => "LVDS_25_DCI" + ) + port map ( + I => ADO_LV(lvds_line*2), + IB => ADO_LV(lvds_line*2+1), + O => lvds_add_on_data(lvds_line) + ); + end generate LVDS_ADO_SIGNAL; + +--Shark links +-- DSP_L0DATIP : out std_logic_vector (3 downto 0); +-- DSP_L0DATIN : out std_logic_vector (3 downto 0); +-- DSP_L0DATOP : in std_logic_vector (3 downto 0); +-- DSP_L0DATON : in std_logic_vector (3 downto 0); +-- DSP_L0CLKINP : out std_logic; +-- DSP_L0CLKINN : out std_logic; +-- DSP_L0CLKOUTP : in std_logic; +-- DSP_L0CLKOUTN : in std_logic; +-- DSP_DATA_LINK0_OUT_0 : IBUFDS +-- generic map ( +-- IOSTANDARD => "LVDS_25" +-- ) +-- port map ( +-- I => , +-- IB =>, +-- O => +-- ); +-- DSP_DATA_LINK0_OUT_1 : IBUFDS +-- generic map ( +-- IOSTANDARD => "LVDS_25" +-- ) +-- port map ( +-- I => , +-- IB =>, +-- O => +-- ); +-- DSP_DATA_LINK0_OUT_2 : IBUFDS +-- generic map ( +-- IOSTANDARD => "LVDS_25" +-- ) +-- port map ( +-- I => , +-- IB =>, +-- O => +-- ); +-- DSP_DATA_LINK0_OUT_3 : IBUFDS +-- generic map ( +-- IOSTANDARD => "LVDS_25" +-- ) +-- port map ( +-- I => , +-- IB =>, +-- O => +-- ); +-- DSP_DATA_LINK0_IN_0 : OBUFDS +-- generic map ( +-- IOSTANDARD => "LVDS_25" +-- ) +-- port map ( +-- I => , +-- IB =>, +-- O => dsp_link_data_in_0(0) +-- ); +-- DSP_DATA_LINK0_IN_1 : OBUFDS +-- generic map ( +-- IOSTANDARD => "LVDS_25" +-- ) +-- port map ( +-- I => , +-- IB =>, +-- O => dsp_link_data_in_0(1) +-- ; +-- DSP_DATA_LINK0_IN_2 : OBUFDS +-- generic map ( +-- IOSTANDARD => "LVDS_25" +-- ) +-- port map ( +-- I => , +-- IB =>, +-- O =>dsp_link_data_in_0(2) +-- ); +-- DSP_DATA_LINK0_IN_3 : OBUFDS +-- generic map ( +-- IOSTANDARD => "LVDS_25" +-- ) +-- port map ( +-- I => , +-- IB =>, +-- O => dsp_link_data_in_0(3) +-- ); + +----------------------------------------------------------------------------- +-- Component Instance +----------------------------------------------------------------------------- +-- not_link_status_i <= link_status_i(3); +-- apl_error_pattern_in_i <= (others => '0'); + +------------------------------------------------------------------------------- +-- api +------------------------------------------------------------------------------- + API_INST: trb_net16_endpoint_0_trg_1_api + generic map ( + API_TYPE => 1, + INIT_DEPTH => 1, + REPLY_DEPTH => 1, + FIFO_TO_INT_DEPTH => 1, + FIFO_TO_APL_DEPTH => 1, + SBUF_VERSION => 0, + MUX_WIDTH => 1, + MUX_SECURE_MODE => 0, + DAT_CHANNEL => 0, + DATA_WIDTH => 16, + NUM_WIDTH => 2) + port map ( + CLK => CLK, + RESET => external_reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => media_data_valid_in_i, + MED_DATA_OUT => media_data_in_i, + MED_PACKET_NUM_OUT => open,--MED_PACKET_NUM_OUT_i, + MED_READ_IN => '1', + MED_DATAREADY_IN => media_data_valid_out_i, + MED_DATA_IN => media_data_out_i, + MED_PACKET_NUM_IN => med_packet_num_in_i, + MED_READ_OUT => open, --MED_READ_OUT_i, enable reading + --data from trbv2_tlk_api_fifo + MED_ERROR_IN => "000",--MED_ERROR_IN_i, - if there is + --link lok + APL_DATA_IN => x"0000", + APL_PACKET_NUM_IN => "00", + APL_WRITE_IN => '0', + APL_FIFO_FULL_OUT => open, + APL_SHORT_TRANSFER_IN => '1', + APL_DTYPE_IN => counter_0_i(3 downto 0), + APL_ERROR_PATTERN_IN => x"12345678", + APL_SEND_IN => start_readout_i, + APL_TARGET_ADDRESS_IN => x"FFFF", + APL_DATA_OUT => open, + APL_PACKET_NUM_OUT => open, + APL_TYP_OUT => open, + APL_DATAREADY_OUT => open, + APL_READ_IN => '1', + APL_RUN_OUT => apl_run_out_i, + APL_MY_ADDRESS_IN => x"0001", + APL_SEQNR_OUT => apl_seqnr_out_i, + STAT_GEN => open,--STAT_GEN_i, + STAT_LOCKED => open,--STAT_LOCKED_i, + STAT_INIT_BUFFER => open,--STAT_INIT_BUFFER_i, + STAT_REPLY_BUFFER => open,--STAT_REPLY_BUFFER_i, + STAT_api_control_signals => open,--STAT_api_control_signals_i, + STAT_MPLEX => open,--STAT_MPLEX_i, + CTRL_GEN => x"00000000",--CTRL_GEN_i, + CTRL_LOCKED => x"00000000", + STAT_CTRL_INIT_BUFFER => x"00000000",--STAT_CTRL_INIT_BUFFER_i, + STAT_CTRL_REPLY_BUFFER => x"00000000",--STAT_CTRL_REPLY_BUFFER_i, + MPLEX_CTRL => x"00000000",--MPLEX_CTRL_i, + API_STAT_FIFO_TO_INT => open,--API_STAT_FIFO_TO_INT_i, + API_STAT_FIFO_TO_APL => open--API_STAT_FIFO_TO_APL_i + ); + COUNTER_FOR_API: process (CLK, external_reset_i) + begin + if rising_edge(CLK) then + if external_reset_i = '1' then + med_packet_num_in_i <= (others => '0'); + elsif media_data_valid_out_i = '1' then + med_packet_num_in_i <= med_packet_num_in_i + 1; + end if; + end if; + end process COUNTER_FOR_API; +------------------------------------------------------------------------------- +-- media to api, api to media +------------------------------------------------------------------------------- + TLK_RX_CLK_BUFR: BUFR + port map( + CE => '1', + CLR => '0', + I => TLK_RX_CLK, + O => tlk_rx_clk_r + ); + TLK_CLK_BUFR: BUFR + port map( + CE => '1', + CLR => '0', + I => TLK_CLK, + O => tlk_clk_r + ); + SFP_TX_DIS <= '0'; + OPTICAL_MEDIA_TO_FROM_API: trbv2_tlk_api + port map ( + RESET => external_reset_i, + CLK => CLK, + TLK_CLK => tlk_clk_r, + TLK_ENABLE => TLK_ENABLE, + TLK_LCKREFN => TLK_LCKREFN, + TLK_LOOPEN => TLK_LOOPEN, + TLK_PRBSEN => TLK_PRBSEN, + TLK_RXD => TLK_RXD, + TLK_RX_CLK => tlk_rx_clk_r, + TLK_RX_DV => TLK_RX_DV, + TLK_RX_ER => TLK_RX_ER, + TLK_TXD => TLK_TXD, + TLK_TX_EN => TLK_TX_EN, + TLK_TX_ER => TLK_TX_ER, + DATA_OUT => media_data_out_i, + DATA_IN => media_data_in_i, + DATA_VALID_IN => media_data_valid_in_i, + DATA_VALID_OUT => media_data_valid_out_i, + TLK_API_REGISTER_00 => tlk_api_register_00_i); + fpga_register_0a_i <= media_data_valid_in_i & media_data_valid_out_i & media_data_out_i & media_data_in_i(13 downto 0); +------------------------------------------------------------------------------- +-- Vulom interafce +------------------------------------------------------------------------------- + VULOM_INT : vulom_interface + port map ( + CLK => CLK, + DATA_CLK => ADDON_CLK2, + RESET => external_reset_i, + DATA_IN => ADO_TTL(3 downto 2), --lvds_add_on_data (3 downto 0), + BUSY => ADO_TTL(4), --lvds_add_on_data (4), + API_DATA => open, + API_RUN_OUT => apl_run_out_i, + API_SHORT_TRANSFER => open, + API_DTYPE => open, + API_SEND => open, + API_WRITE_IN => open, + API_TARGET_ADDRESS => open, + API_SEQNR_OUT => apl_seqnr_out_i,--x"00", + VULOM_INT_REG => vulom_int_reg_00, + INTERFACE_CONTROL => fpga_register_06_i(11 downto 8), + EVENT_REGISTER_00 => counter_0_i, + EVENT_REGISTER_01 => counter_1_i, + EVENT_REGISTER_02 => counter_2_i, + EVENT_REGISTER_03 => counter_3_i, + EVENT_REGISTER_04 => counter_4_i, + EVENT_REGISTER_05 => counter_5_i, + EVENT_REGISTER_06 => counter_6_i, + EVENT_REGISTER_07 => counter_7_i, + EVENT_REGISTER_08 => counter_8_i, + EVENT_REGISTER_09 => counter_9_i, + EVENT_REGISTER_0a => counter_a_i, + EVENT_REGISTER_0b => counter_b_i, + EVENT_REGISTER_0c => counter_c_i, + START_READOUT => start_readout_i, + LVL1_TRANSFER_BUSY => lvl1_busy_i + ); + -------------------------------------------------------------------------- + -- event from cts to etrax + -------------------------------------------------------------------------- + FPGA_ETRAX_INT : fpga_to_etrax_data_flow + port map ( + CLK => CLK, + RESET => external_reset_i, + START_READOUT => start_readout_i, + HOW_MANY_ADD_DATA => x"0a", + COUNTER_0 => counter_0_i, + COUNTER_1 => counter_1_i, + COUNTER_2 => counter_2_i, + COUNTER_3 => counter_3_i, + COUNTER_4 => counter_4_i, + COUNTER_5 => counter_5_i, + COUNTER_6 => counter_6_i, + COUNTER_7 => counter_7_i, + COUNTER_8 => counter_8_i, + COUNTER_9 => counter_9_i, + COUNTER_a => counter_a_i, + DATA_OUT => data_out_i, + DATA_VALID => data_valid_i, + ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i, + LVL1_BUSY => lvl1_busy_i, + CTS_ETRAX_REGISTER_00 => cts_etrax_register_00_i, + CTS_ETRAX_REGISTER_01 => cts_etrax_register_01_i, + CTS_ETRAX_REGISTER_02 => cts_etrax_register_02_i, + CTS_ETRAX_REGISTER_03 => cts_etrax_register_03_i, + CTS_ETRAX_REGISTER_04 => cts_etrax_register_04_i); + ADO_TTL(3 downto 2) <= (others => 'Z'); + ADO_TTL(15 downto 10) <= TLK_TXD_i (5 downto 0); + ADO_TTL(9) <= TLK_TX_EN_i; + +-- ADO_TTL(8) <= not TLK_CLK_i; +-- ADO_TTL(15) <= TLK_TX_EN_i; +-- ADO_TTL(13) <= TLK_TX_EN_i; +-- ADO_TTL(14) <= 'Z'; +-- ADO_TTL(12) <= 'Z'; +-- BUSY_1_PULSER : edge_to_pulse +-- port map ( +-- clock => CLK, +-- en_clk => '1', +-- signal_in => ADO_TTL(14), +-- pulse => busy1_pulse); +-- BUSY_2_PULSER : edge_to_pulse +-- port map ( +-- clock => CLK, +-- en_clk => '1', +-- signal_in => ADO_TTL(12), +-- pulse => busy2_pulse); +-- SAVE_BUSY: process (CLK, external_reset_i) +-- begin +-- if rising_edge(CLK) then +-- if external_reset_i = '1' or (trb_busy1 = '1' and trb_busy2 = '1' ) then +-- trb_busy1 <= '0'; +-- trb_busy2 <= '0'; +-- elsif busy1_pulse = '1' then +-- trb_busy1 <= '1'; +-- trb_busy2 <= trb_busy2; +-- elsif busy2_pulse = '1' then +-- trb_busy1 <= trb_busy1; +-- trb_busy2 <= '1'; +-- elsif busy1_pulse = '1' and busy2_pulse = '1'then +-- trb_busy1 <= '1'; +-- trb_busy2 <= '1'; +-- else +-- trb_busy1 <= trb_busy1; +-- trb_busy2 <= trb_busy2; +-- end if; +-- end if; +-- end process SAVE_BUSY; +-- busy_all <= trb_busy1 and trb_busy2; + MULTIPLEX_DATA_TO_ETRAX: process(CLK,external_reset_i,external_mode_i) + begin + if rising_edge(CLK) then + if external_reset_i = '1' then + external_data_in_i <= (others => '0'); + elsif external_mode_i(7 downto 0) = x"01" then + external_data_in_i <= dsp_data_out_i; + elsif external_mode_i(7 downto 0) = x"02" then + external_data_in_i <= sdram_data_out_i; + else + external_data_in_i <= x"0000"&external_mode_i; + end if; + end if; + end process MULTIPLEX_DATA_TO_ETRAX; + -------------------------------------------------------------------------- + -- etrax interface, sending events, control and status + -------------------------------------------------------------------------- + ETRAX_INTERFACE_LOGIC : etrax_interface + port map ( + CLK => CLK, + RESET => '0', + DATA_BUS => data_out_i, + ETRAX_DATA_BUS_B => FS_PB, + ETRAX_DATA_BUS_C => FS_PC, + DATA_VALID => data_valid_i, + ETRAX_BUS_BUSY => etrax_bus_busy_i, + ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i, + TDC_TCK => open, + TDC_TDI => open, + TDC_TMS => open, + TDC_TRST => open, + TDC_TDO => '0', + TDC_RESET => open, --TDC_RESET, + EXTERNAL_ADDRESS => external_address_i, + EXTERNAL_DATA_OUT => external_data_out_i, + EXTERNAL_DATA_IN => external_data_in_i, + EXTERNAL_ACK => external_ack_i, + EXTERNAL_VALID => external_valid_i, + EXTERNAL_MODE => external_mode_i, + FPGA_REGISTER_00 => x"00000000", + FPGA_REGISTER_01 => fpga_register_01_i,--ppp tlk_register_00_i, + FPGA_REGISTER_02 => fpga_register_02_i,--ppp tlk_register_01_i, + FPGA_REGISTER_03 => fpga_register_03_i,--ppp tdc_register_00_i,--x"abbaab02", + FPGA_REGISTER_04 => fpga_register_04_i, --ppp busy_register_00_i, + FPGA_REGISTER_05 => fpga_register_05_i,--lvds_add_on_data(31 downto 0),--tdc_register_04_i,--fpga_register_05_i, --ppp trigger_register_00_i, + FPGA_REGISTER_06 => fpga_register_06_i,--open, -- ppp x"abbaab05", + FPGA_REGISTER_07 => fpga_register_07_i, + FPGA_REGISTER_08 => fpga_register_08_i, + FPGA_REGISTER_09 => fpga_register_09_i, + FPGA_REGISTER_0a => fpga_register_0a_i, + FPGA_REGISTER_0b => x"00000000",--fpga_register_0b_i, + FPGA_REGISTER_0c => x"00000000",--fpga_register_0c_i, + FPGA_REGISTER_0d => x"00000000",--fpga_register_0d_i, + EXTERNAL_RESET => external_reset, + LVL2_VALID => '0' + ); + fpga_register_01_i <= vulom_int_reg_00; + fpga_register_02_i <= '0' & "000" & "00"& TLK_RX_DV & TLK_RX_ER & TLK_RXD & x"00";-- + --apl_seqnr_out_i; + fpga_register_03_i <= x"bacd0000";--med_data_out_i_saved(31 downto 0); + fpga_register_04_i <= x"00001234";--med_data_out_i_saved(63 downto 32); + ADO_TTL(5)<= vulom_int_reg_00(0); + ADO_TTL(6) <= vulom_int_reg_00(1);--K_RX_ER; + ADO_TTL(7) <= ADDON_CLK1;--vulom_int_reg_00(2); + SYNCH_RESET: process (CLK) + begin -- process SYNCH_RESET + if rising_edge(CLK) then -- rising clock edge + external_reset_i <= external_reset; + else + external_reset_i <= external_reset_i; + end if; + end process SYNCH_RESET; + + dsp_strobe_i <= '1' when external_mode_i(7 downto 0) = x"01" and external_ack_i = '1' else '0'; + DSP_IRQ <= x"1"; + DSP_BMS <= '1' when fpga_register_06_i(3) = '0' else 'Z'; + DSP_BM <= '0' when fpga_register_06_i(3) = '0' else 'Z'; +-- DSP_INTERFACE_LOGIC: dsp_interface +-- port map ( +-- HBR_OUT => dsp_hbr_i, +-- HBG_IN => DSP_HBG, +-- RD_OUT => DSP_RD_i, +-- DSP_DATA_OUT => dspdat_out_i,--DSPDAT to DSP, +-- DSP_DATA_IN => dspdat_in_i,--DSPDAT to FPGA, +-- ADDRESS_DSP => dspaddr_i,--DSPADDR, +-- WRL => DSP_WRL_i, +-- WRH => DSP_WRH, +-- BM_IN => DSP_BM, +-- DSP_RESET => open, +-- BRST => DSP_BRST, +-- ACK => DSP_ACK, +-- CLK => CLK, +-- RESET => external_reset_i, +-- R_W_ENABLE => external_mode_i(15), +-- TRIGGER => dsp_strobe_i, +-- INTERNAL_DATA_IN => external_data_out_i, +-- INTERNAL_DATA_OUT => dsp_data_out_i,--external_data_in_i, +-- INTERNAL_ADDRESS => external_address_i, +-- VALID_DATA_SENT => dsp_external_valid_i, +-- ACKNOWLEDGE => dsp_strobe_i, +-- DEBUGSTATE_MACHINE => dsp_register_00_i); +-- SDRAM_INTERFACE_LOGIC: sdram_interface +-- port map ( +-- CLK_SDRAM => VSD_CLOCK, +-- CKE => VSD_CKE, +-- CS => vsd_cs_i, +-- RAS => VSD_RAS, +-- CAS => VSD_CAS, +-- WE => VSD_WE, +-- DQM => VSD_DQML, +-- BA => VSD_BA, +-- A => VSD_A, +-- DQ => VSD_D, +-- CLK => CLK, +-- RESET => external_reset_i, +-- TRIGGER => external_ack_i, +-- INTERNAL_DATA_IN => external_data_out_i, +-- INTERNAL_DATA_OUT => sdram_data_out_i, +-- INTERNAL_ADDRESS => external_address_i, +-- INTERNAL_MODE => external_mode_i, +-- VALID_DATA_SENT => sdram_external_valid_i, +-- DEBUGSTATE_MACHINE => sdram_register_00_i); + VSD_CSEH <= vsd_cs_i; + VSD_CSEL <= vsd_cs_i; + ETRAX_IRQ <= '1'; + DINT <= etrax_bus_busy_i; + DWAIT <= fpga_register_06_i(6); --'0'enable clock for TDC + DSP_RESET <= fpga_register_06_i(4); + DSP_HBR <= dsp_hbr_i; + DSPDAT <= dspdat_out_i; + dspdat_in_i <= DSPDAT; + DSP_WRL <= DSP_WRL_i; + DSP_RD <= DSP_RD_i; + DSP_DATA_REGISTER: process (CLK, external_reset_i) + begin -- process DSP_DATA_REGISTER + if CLK'event and CLK = '1' then + if external_reset_i = '1' then + dsp_data_reg_in_i <= x"00000000"; + dsp_data_reg_out_i <= x"00000000"; + dsp_bm_reg <= '0'; + sdram_data_i <= x"00000000"; + else + dsp_bm_reg <= DSP_BM; + dsp_data_reg_in_i <= DSPDAT; + dsp_data_reg_out_i <= dspdat_out_i; + sdram_data_i <= VSD_D ; + end if; + end if; + end process DSP_DATA_REGISTER; + + DSPADDR <= dspaddr_i; + DSP_BOFF <= fpga_register_06_i(5); + +end cts; diff --git a/trb_cts/cts_etrax_interface.vhd b/trb_cts/cts_etrax_interface.vhd new file mode 100644 index 0000000..f7206df --- /dev/null +++ b/trb_cts/cts_etrax_interface.vhd @@ -0,0 +1,520 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VComponents.all; +entity fpga_to_etrax_data_flow is + port ( + CLK : in std_logic; + RESET : in std_logic; + START_READOUT : in std_logic; + HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0); + COUNTER_0 : in std_logic_vector(31 downto 0); + COUNTER_1 : in std_logic_vector(31 downto 0); + COUNTER_2 : in std_logic_vector(31 downto 0); + COUNTER_3 : in std_logic_vector(31 downto 0); + COUNTER_4 : in std_logic_vector(31 downto 0); + COUNTER_5 : in std_logic_vector(31 downto 0); + COUNTER_6 : in std_logic_vector(31 downto 0); + COUNTER_7 : in std_logic_vector(31 downto 0); + COUNTER_8 : in std_logic_vector(31 downto 0); + COUNTER_9 : in std_logic_vector(31 downto 0); + COUNTER_a : in std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector (31 downto 0); --data to ETRAX (LVL2) + DATA_VALID : out std_logic; -- The DATA_OUT can be written + ETRAX_IS_READY_TO_READ : in std_logic; + LVL1_BUSY : out std_logic; + CTS_ETRAX_REGISTER_00 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_01 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_02 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_03 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_04 : out std_logic_vector(31 downto 0) + ); +end fpga_to_etrax_data_flow; +architecture fpga_to_etrax_data_flow of fpga_to_etrax_data_flow is + component edge_to_pulse + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; + component up_down_counter_16_bit + port ( + QOUT : out std_logic_vector(15 downto 0); + UP : in std_logic; + DOWN : in std_logic; + CLK : in std_logic; + CLR : in std_logic + ); + end component; + component BUFG + port( + O: out std_ulogic; + I: in std_ulogic + ); + end component; + component up_counter_8bit + port ( + QOUT : out std_logic_vector(7 downto 0); + UP : in std_logic; + CLK : in std_logic; + CLR : in std_logic); + end component; + component lvl1_fifo + port ( + clk : IN std_logic; + din : IN std_logic_VECTOR(31 downto 0); + rd_en : IN std_logic; + rst : IN std_logic; + wr_en : IN std_logic; + data_count : OUT std_logic_VECTOR(13 downto 0); + dout : OUT std_logic_VECTOR(31 downto 0); + empty : OUT std_logic; + full : OUT std_logic); + end component; + signal tdc_ready : std_logic; + signal counter_0_i : std_logic_vector(31 downto 0); + signal counter_1_i : std_logic_vector(31 downto 0); + signal counter_2_i : std_logic_vector(31 downto 0); + signal counter_3_i : std_logic_vector(31 downto 0); + signal counter_4_i : std_logic_vector(31 downto 0); + signal counter_5_i : std_logic_vector(31 downto 0); + signal counter_6_i : std_logic_vector(31 downto 0); + signal counter_7_i : std_logic_vector(31 downto 0); + signal counter_8_i : std_logic_vector(31 downto 0); + signal counter_9_i : std_logic_vector(31 downto 0); + signal counter_a_i : std_logic_vector(31 downto 0); + signal add_data_counter : std_logic_vector(7 downto 0):=(others => '0'); + signal add_data_pulse : std_logic; + signal first_header : std_logic_vector(31 downto 0):=(others => '0'); + signal second_header : std_logic_vector(31 downto 0):=(others => '0'); + signal words_in_event : std_logic_vector(15 downto 0):=(others => '0'); + signal tdc_data_valid_i : std_logic; + signal how_many_words_in_event : std_logic_vector(16 downto 0); + signal delay_up : std_logic; + signal delay_clr : std_logic; + signal delay_qout : std_logic_vector(7 downto 0); + signal lvl1_trigger_pulse_start : std_logic; + signal lvl1_trigger_pulse_delay : std_logic; + type DELAY_FSM_TRIGG is + (IDLE ,DELAY_1,DELAY_2); + signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG; + type LVL1_START_FSM is + (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_TOKEN, SAVE_ADD_DATA_1, SAVE_ADD_DATA_2, SAVE_ADD_DATA_3, SAVE_ADD_DATA_4, SEND_LVL2_TRIGG); + signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM; + type LVL2_START_FSM is + (IDLE, READOUT_WORD1, READOUT_WORD2 ,SAVE_EVENT_SIZE ,SEND_DATA1); + signal LVL2_START_fsm_currentstate, LVL2_START_fsm_nextstate : LVL2_START_FSM; + signal lvl1_busy_i : std_logic; + signal lvl1_busy_ff : std_logic; + signal lvl1_memory_busy_i : std_logic; + signal lvl2_busy_i : std_logic; + signal lvl1_trigger_pulse : std_logic; + signal lvl1_tdc_trigg_i : std_logic; + signal lvl1_tdc_trigg_ff : std_logic; + + signal trigger_register_00_i : std_logic_vector(5 downto 0); + signal lvl2_busy_end_pulse : std_logic; + signal not_tdc_data_valid_i : std_logic; + + signal not_tdc_clk : std_logic; + signal test_counter_0 : std_logic_vector(7 downto 0); + signal test_counter_1 : std_logic_vector(7 downto 0); + signal test_counter_2 : std_logic_vector(7 downto 0); + signal test_counter_3 : std_logic_vector(7 downto 0); + signal add_data_i : std_logic_vector(31 downto 0); + signal lvl1_fifo_out : std_logic_vector(31 downto 0); + signal lvl1_fifo_in : std_logic_vector(31 downto 0); + signal lvl1_fifo_counter : std_logic_vector(13 downto 0); + signal lvl1_fifo_empty : std_logic; + signal lvl1_fifo_full : std_logic; + signal lvl1_fifo_wr_en : std_logic; + signal lvl1_fifo_rd_en : std_logic; + signal lvl1_or_lvl2_is_busy : std_logic; + signal trigger_with_gen_pulse : std_logic; + signal lvl1_tag_minus1 : std_logic_vector(15 downto 0); + signal lvl2_debug : std_logic_vector(2 downto 0); + signal tdc_start_i : std_logic; + signal lvl2_busy_start_pulse : std_logic; + + signal lvl1_tdc_trigg_i_fsm : std_logic; + signal lvl1_fifo_wr_en_fsm : std_logic; + signal lvl1_fifo_in_fsm : std_logic_vector(31 downto 0); + signal lvl1_buffer_rd_en_fsm : std_logic; + signal lvl1_busy_i_fsm : std_logic; + signal lvl1_fifo_rd_en_fsm : std_logic; + signal tdc_data_valid_i_fsm : std_logic; +begin + + + CTS_ETRAX_REGISTER : process (CLK, RESET) + begin + if rising_edge(CLK) then + CTS_ETRAX_REGISTER_00(0) <= '0'; + CTS_ETRAX_REGISTER_00(1) <= '0'; + CTS_ETRAX_REGISTER_00(2) <= '0'; + CTS_ETRAX_REGISTER_00(3) <= '0'; + CTS_ETRAX_REGISTER_00(13 downto 4) <= (others => '0'); + CTS_ETRAX_REGISTER_00(14) <= lvl1_busy_i; + CTS_ETRAX_REGISTER_00(15) <= lvl1_or_lvl2_is_busy;--lvl1_memory_busy_i; + CTS_ETRAX_REGISTER_00(30) <= lvl1_fifo_wr_en; + CTS_ETRAX_REGISTER_00(31) <= lvl2_busy_i; + CTS_ETRAX_REGISTER_00(29 downto 16) <= lvl1_fifo_counter; + CTS_ETRAX_REGISTER_01(26 downto 0) <= lvl2_debug & trigger_register_00_i(5 downto 2) & "00" & trigger_register_00_i(1 downto 0)& how_many_words_in_event(15 downto 0); + CTS_ETRAX_REGISTER_01(31 downto 27) <= (others => '0'); + CTS_ETRAX_REGISTER_02(31 downto 0) <= (others => '0'); + CTS_ETRAX_REGISTER_03(31 downto 0) <= lvl1_fifo_out; + CTS_ETRAX_REGISTER_04(31 downto 0) <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0; + end if; + end process CTS_ETRAX_REGISTER; + LVL1_FIFO_LVL2: lvl1_fifo + port map ( + clk => CLK, + din => lvl1_fifo_in, + rd_en => lvl1_fifo_rd_en, + rst => RESET, + wr_en => lvl1_fifo_wr_en, + data_count => lvl1_fifo_counter, + dout => lvl1_fifo_out, + empty => lvl1_fifo_empty, + full => lvl1_fifo_full); + DATA_OUT <= lvl1_fifo_out; + LVL1_START : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + LVL1_START_fsm_currentstate <= IDLE; + lvl1_tdc_trigg_i <= '0'; + lvl1_fifo_wr_en <= '0'; + lvl1_busy_i <= '0'; + lvl1_tdc_trigg_i <= '0'; + else + LVL1_START_fsm_currentstate <= LVL1_START_fsm_nextstate; + lvl1_tdc_trigg_i <= lvl1_tdc_trigg_i_fsm; + lvl1_fifo_wr_en <= lvl1_fifo_wr_en_fsm; + lvl1_fifo_in <= lvl1_fifo_in_fsm ; + lvl1_busy_i <= lvl1_busy_i_fsm; + lvl1_tdc_trigg_i <= lvl1_tdc_trigg_i_fsm; + end if; + end if; + end process LVL1_START; + + + LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate, START_READOUT, add_data_counter, lvl1_or_lvl2_is_busy, how_many_add_data, add_data_i, second_header, first_header) + begin + lvl1_tdc_trigg_i_fsm <= '0'; + lvl1_fifo_wr_en_fsm <= '0'; + lvl1_busy_i_fsm <= '0'; + LVL1_START_fsm_nextstate <= IDLE; + lvl1_fifo_in_fsm <= first_header; + case (LVL1_START_fsm_currentstate) is + when IDLE => + trigger_register_00_i(5 downto 2) <= x"1"; + lvl1_fifo_wr_en_fsm <= '0'; + lvl1_fifo_in_fsm <= first_header; + lvl1_busy_i_fsm <= '0'; + if START_READOUT = '1' then + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_1; + else + LVL1_START_fsm_nextstate <= IDLE; + end if; + when SAVE_ADD_DATA_1 => + trigger_register_00_i(5 downto 2) <= x"7"; + lvl1_fifo_in_fsm <= first_header; + lvl1_fifo_wr_en_fsm <= '1'; + lvl1_busy_i_fsm <= '1'; + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_2; + when SAVE_ADD_DATA_2 => + trigger_register_00_i(5 downto 2) <= x"8"; + lvl1_fifo_in_fsm <= second_header; + lvl1_fifo_wr_en_fsm <= '1'; + lvl1_busy_i_fsm <= '1'; + if HOW_MANY_ADD_DATA = x"00" then + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_4; + else + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_3; + end if; + when SAVE_ADD_DATA_3 => + trigger_register_00_i(5 downto 2) <= x"9"; + lvl1_fifo_in_fsm <= add_data_i; + lvl1_fifo_wr_en_fsm <= '1'; + lvl1_busy_i_fsm <= '1'; + if add_data_counter = x"0f" then + LVL1_START_fsm_nextstate <= SEND_LVL2_TRIGG; + else + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_3; + end if; + when SEND_LVL2_TRIGG => + trigger_register_00_i(5 downto 2) <= x"c"; + lvl1_fifo_in_fsm <= first_header; + lvl1_fifo_wr_en_fsm <= '0'; + lvl1_busy_i_fsm <= '1'; + lvl1_tdc_trigg_i_fsm <= '0'; + LVL1_START_fsm_nextstate <= IDLE; + when others => + trigger_register_00_i(5 downto 2) <= x"d"; + lvl1_fifo_in_fsm <= first_header; + lvl1_fifo_wr_en_fsm <= '0'; + lvl1_busy_i_fsm <= '1'; + lvl1_tdc_trigg_i_fsm <= '0'; + LVL1_START_fsm_nextstate <= IDLE; + end case; + end process LVL1_START_FSM_PROC; +-- not_tdc_clk <= TDC_CLK; + + SAVE_DATA : process (CLK, RESET,lvl1_tdc_trigg_i) + begin + if rising_edge(CLK) then + if RESET = '1' then + counter_a_i <= (others => '0'); + counter_9_i <= (others => '0'); + counter_8_i <= (others => '0'); + counter_7_i <= (others => '0'); + counter_6_i <= (others => '0'); + counter_5_i <= (others => '0'); + counter_4_i <= (others => '0'); + counter_3_i <= (others => '0'); + counter_2_i <= (others => '0'); + counter_1_i <= (others => '0'); + counter_0_i <= (others => '0'); + + + elsif START_READOUT = '1' then + counter_a_i <= COUNTER_a; + counter_9_i <= COUNTER_9; + counter_8_i <= COUNTER_8; + counter_7_i <= COUNTER_7; + counter_6_i <= COUNTER_6; + counter_5_i <= COUNTER_5; + counter_4_i <= COUNTER_4; + counter_3_i <= COUNTER_3; + counter_2_i <= COUNTER_2; + counter_1_i <= COUNTER_1; + counter_0_i <= COUNTER_0; + end if; + end if; + end process SAVE_DATA; + CHOOSE_DATA : process (CLK, RESET, add_data_counter) + begin + if rising_edge(CLK) then + if RESET = '1' then + add_data_i <= x"00000000"; + else + case add_data_counter(3 downto 0) is + when "0000" => add_data_i <= counter_a_i; + when "0001" => add_data_i <= counter_9_i; + when "0010" => add_data_i <= counter_8_i; + when "0011" => add_data_i <= counter_7_i; + when "0100" => add_data_i <= counter_6_i; + when "0101" => add_data_i <= counter_5_i; + when "0110" => add_data_i <= counter_4_i; + when "0111" => add_data_i <= counter_3_i; + when "1000" => add_data_i <= counter_2_i; + when "1001" => add_data_i <= counter_1_i; + when "1010" => add_data_i <= counter_0_i; + when others => add_data_i <= x"deadface"; + end case; + end if; + end if; + end process CHOOSE_DATA; + add_data_pulse <= '1' when SAVE_ADD_DATA_3 = LVL1_START_fsm_nextstate else '0'; + ADD_DATA_COUNTER_CONTROL : process (CLK,RESET,lvl1_tdc_trigg_i,add_data_pulse) + begin + if rising_edge(CLK) then + if RESET = '1' or START_READOUT = '1' then + add_data_counter <= x"1" & HOW_MANY_ADD_DATA(3 downto 0) - 1; + elsif add_data_pulse = '1' then + add_data_counter <= add_data_counter - 1; + end if; + end if; + end process ADD_DATA_COUNTER_CONTROL; + COUNT_WORDS_IN_EVENT : process (CLK, RESET,START_READOUT) + begin + if rising_edge(CLK) then + if RESET = '1' or START_READOUT = '1' then + words_in_event <= x"0003" + HOW_MANY_ADD_DATA; + else + words_in_event <= words_in_event; + end if; + end if; + end process COUNT_WORDS_IN_EVENT; + + first_header <= x"0" & counter_0_i(3 downto 0) & counter_1_i(7 downto 0) & words_in_event(15 downto 0); + second_header <= x"030000" & HOW_MANY_ADD_DATA; + + ----------------------------------------------------------------------------- + ---------------------------------------------------------------------------- + -- LVL2 logic (only CLK domain) + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + LVL2_START : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + LVL2_START_fsm_currentstate <= IDLE; + lvl1_fifo_rd_en <= '0'; + tdc_data_valid_i <= '0'; + else + lvl1_fifo_rd_en <= lvl1_fifo_rd_en_fsm; + tdc_data_valid_i <= tdc_data_valid_i_fsm; + LVL2_START_fsm_currentstate <= LVL2_START_fsm_nextstate; + end if; + end if; + end process LVL2_START; + START_LVL2_FSM: process (LVL2_START_fsm_currentstate, LVL1_START_fsm_currentstate, how_many_words_in_event, lvl1_fifo_out, etrax_is_ready_to_read) + begin + lvl2_debug (2 downto 0) <= "000"; + lvl1_fifo_rd_en_fsm <= '0'; + tdc_data_valid_i_fsm <= '0'; + LVL2_START_fsm_nextstate <= IDLE; + case (LVL2_START_fsm_currentstate) is + when IDLE => + lvl2_debug (2 downto 0) <= "001"; + lvl1_fifo_rd_en_fsm <= '0'; + tdc_data_valid_i_fsm <= '0'; + if LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG then + LVL2_START_fsm_nextstate <= READOUT_WORD1; + else + LVL2_START_fsm_nextstate <= IDLE; + end if; + when READOUT_WORD1 => + lvl2_debug (2 downto 0) <= "010"; + lvl1_fifo_rd_en_fsm <= '1'; + tdc_data_valid_i_fsm <= '0'; + LVL2_START_fsm_nextstate <= READOUT_WORD2; + when READOUT_WORD2 => + lvl2_debug (2 downto 0) <= "011"; + lvl1_fifo_rd_en_fsm <= '0'; + tdc_data_valid_i_fsm <= '0'; + LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE; + when SAVE_EVENT_SIZE => + lvl2_debug (2 downto 0) <= "100"; + lvl1_fifo_rd_en_fsm <= '0'; + tdc_data_valid_i_fsm <= '0'; + LVL2_START_fsm_nextstate <= SEND_DATA1; + when SEND_DATA1 => + lvl2_debug (2 downto 0) <= "101"; + lvl1_fifo_rd_en_fsm <= ETRAX_IS_READY_TO_READ; + tdc_data_valid_i_fsm <= '1'; + if how_many_words_in_event(15 downto 0) = x"0000" then + LVL2_START_fsm_nextstate <= IDLE; + else + LVL2_START_fsm_nextstate <= SEND_DATA1; + end if; + end case; + end process START_LVL2_FSM; + COUNT_DOWN_READOUT: process (CLK, RESET,how_many_words_in_event) + begin + if rising_edge(CLK) then + if RESET = '1' then + how_many_words_in_event <= (others => '0'); + elsif LVL2_START_fsm_currentstate = SAVE_EVENT_SIZE then + how_many_words_in_event <= '1' & lvl1_fifo_out(15 downto 0); + elsif how_many_words_in_event > x"0ffff" and ETRAX_IS_READY_TO_READ = '1' then -- or READ_ADRESS_END_UP='1')then + how_many_words_in_event <= how_many_words_in_event - 1; + end if; + end if; + end process COUNT_DOWN_READOUT; + SYNCH_DATA_VALID: process (CLK, RESET) + begin + if rising_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?) + if RESET = '1' then + DATA_VALID <= '0'; + else + DATA_VALID <= tdc_data_valid_i; + end if; + end if; + end process SYNCH_DATA_VALID; + + not_tdc_data_valid_i <= not tdc_data_valid_i; + LVL2_BUSY_END_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => not_tdc_data_valid_i, + pulse => lvl2_busy_end_pulse); + LVL2_BUSY_SET: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or lvl2_busy_end_pulse = '1'then + lvl2_busy_i <= '0'; + elsif LVL2_START_fsm_currentstate /= IDLE then + lvl2_busy_i <= '1'; + end if; + end if; + end process LVL2_BUSY_SET; + LVL2_BUSY_START_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => lvl2_busy_i, + pulse => lvl2_busy_start_pulse); + lvl1_memory_busy_i <= '1' when lvl1_fifo_counter > "00001111111111" else '0'; + --set + --to + --max + --value + --!!!!!!! and cut data funktion should + --be implemented - with busy or max + --size or last event ? or both + LVL1_OR_LVL2_BUSY: process (CLK, RESET, lvl1_busy_i, lvl2_busy_end_pulse) + begin + if rising_edge(CLK) then + if RESET = '1' then + lvl1_or_lvl2_is_busy <= '0'; + elsif lvl1_busy_i = '1' then + lvl1_or_lvl2_is_busy <= '1'; + elsif lvl2_busy_end_pulse = '1' then + lvl1_or_lvl2_is_busy <= '0'; + end if; + end if; + end process LVL1_OR_LVL2_BUSY; + + ----------------------------------------------------------------------------- + -- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal + ----------------------------------------------------------------------------- +-- TEST_COUNTER_a : up_counter_8bit +-- port map ( +-- CLK => CLK, +-- UP => tdc_start_i, +-- CLR => RESET, +-- QOUT => test_counter_0 +-- ); +-- TEST_COUNTER_b : up_counter_8bit +-- port map ( +-- CLK => CLK, +-- UP => RECEIVED_TDC_TOKEN, +-- CLR => RESET, +-- QOUT => test_counter_1 +-- ); +-- TEST_COUNTER_c : up_counter_8bit +-- port map ( +-- CLK => CLK, +-- UP => lvl2_busy_start_pulse,--lvl2_trigger_pulse, +-- CLR => RESET, +-- QOUT => test_counter_2 +-- ); +-- TEST_COUNTER_d : up_counter_8bit +-- port map ( +-- CLK => CLK, +-- UP => lvl2_busy_end_pulse, +-- CLR => RESET, +-- QOUT => test_counter_3 +-- ); + REGITERING_SIGNALS: process (CLK, RESET) + begin + if rising_edge(CLK) then -- rising clock edge + if RESET = '1' then + LVL1_BUSY <= '0'; + else + LVL1_BUSY <= lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i; --here + end if; + end if; + end process REGITERING_SIGNALS; +end fpga_to_etrax_data_flow; + + + diff --git a/trb_cts/cts_syn.prj b/trb_cts/cts_syn.prj new file mode 100644 index 0000000..fa3f9e5 --- /dev/null +++ b/trb_cts/cts_syn.prj @@ -0,0 +1,86 @@ +#-- Synplicity, Inc. +#-- Version Synplify Pro 8.2.1 + + +#add_file options +add_file -vhdl -lib work "etrax_interface.vhd" +add_file -vhdl -lib work "f_divider.vhd" +add_file -vhdl -lib work "cts.vhd" +add_file -vhdl -lib work "vulom_interface.vhd" +add_file -vhdl -lib work "from_64_bit_to_optical_link.vhd" +add_file -vhdl -lib work "optical_link_to_64_bit.vhd" +add_file -vhdl -lib work "up_down_counter_10bit.vhd" +add_file -vhdl -lib work "simpleupcounter_10bit.vhd" +add_file -vhdl -lib work "link_converter.vhd" +add_file -vhdl -lib work "cts_etrax_interface.vhd" +add_file -vhdl -lib work "trbv2_tlk_api_fifo.vhd" +add_file -vhdl -lib work "trbv2_tlk_api.vhd" + + +add_file -vhdl -lib work "api/trbnet/xilinx/trb_net_fifo_arch.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_fifo.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_iobuf.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_active_api.vhd" +add_file -vhdl -lib work "api/trbnet/xilinx/shift_lut_x16.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_ibuf.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_io_multiplexer.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_obuf.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_term_ibuf.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_term.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_active_apimbuf.vhd" +add_file -vhdl -lib work "api/trbnet/trb_net_base_api.vhd" +#add_file -constraint "cts_syn.sdc" + + +#implementation: "workdir" +impl -add workdir + +#device options +set_option -technology VIRTEX4 +set_option -part xc4vlx40 +set_option -package ff1148 +set_option -speed_grade -10 + +#compilation/mapping options +set_option -default_enum_encoding gray +set_option -symbolic_fsm_compiler 0 +set_option -resource_sharing 1 +set_option -use_fsm_explorer 0 +set_option -top_module "cts" + +#map options +set_option -frequency 120.000 +set_option -run_prop_extract 0 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -pipe 1 +set_option -update_models_cp 0 +set_option -verification_mode 0 +set_option -fixgatedclocks 0 +set_option -no_sequential_opt 0 +set_option -retiming 0 + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#VIF options +set_option -write_vif 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "workdir/cts.edf" + +# +#implementation attributes + +set_option -synthesis_onoff_pragma 0 +impl -active "workdir" diff --git a/trb_cts/cts_tb.vhd b/trb_cts/cts_tb.vhd new file mode 100644 index 0000000..d2e33df --- /dev/null +++ b/trb_cts/cts_tb.vhd @@ -0,0 +1,408 @@ +library IEEE; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.all; +library ieee; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.all; + + +entity cts_tb is + + port ( + VIRT_CLK : in std_logic; + VIRT_CLKB : in std_logic; + RESET_VIRT : in std_logic; + DBAD : out std_logic; + DGOOD : out std_logic; + DINT : out std_logic; + DWAIT : out std_logic; + FS_PB : out std_logic_vector (17 downto 0); + FS_PC : inout std_logic_vector (17 downto 0); + ETRAX_IRQ : out std_logic; + DSPADDR : out std_logic_vector (31 downto 0); + DSPDAT : inout std_logic_vector (31 downto 0); + DSP_ACK : in std_logic; + DSP_BM : inout std_logic; + DSP_BMS : out std_logic; + DSP_BOFF : out std_logic; + DSP_BRST : inout std_logic; + DSP_HBG : in std_logic; + DSP_HBR : out std_logic; + DSP_IRQ : out std_logic_vector (3 downto 0); + DSP_RD : out std_logic; + DSP_RESET : out std_logic; + DSP_RESET_OUT : in std_logic; + DSP_WRH : out std_logic; + DSP_WRL : out std_logic; + VSD_A : out std_logic_vector (12 downto 0); + VSD_BA : out std_logic_vector (1 downto 0); + VSD_CAS : out std_logic; + VSD_CKE : out std_logic; + VSD_CLOCK : out std_logic; + VSD_CSEH : out std_logic; + VSD_CSEL : out std_logic; + VSD_D : inout std_logic_vector (31 downto 0); + VSD_DQML : out std_logic_vector (3 downto 0); + VSD_RAS : out std_logic; + VSD_WE : out std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector (15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector (15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + SFP_LOS : in std_logic; + SFP_TX_DIS : out std_logic; + SFP_TX_FAULT : in std_logic; + ADO_LV : in std_logic_vector(51 downto 0); + ADO_TTL : inout std_logic_vector(46 downto 2); + ADO_CLK1 : in std_logic; + ADO_CLK2 : in std_logic); + +end cts_tb; +architecture cts_tb of cts_tb is + + +component cts + port ( + VIRT_CLK : in std_logic; + VIRT_CLKB : in std_logic; + RESET_VIRT : in std_logic; + DBAD : out std_logic; + DGOOD : out std_logic; + DINT : out std_logic; + DWAIT : out std_logic; + FS_PB : out std_logic_vector (17 downto 0); + FS_PC : inout std_logic_vector (17 downto 0); + ETRAX_IRQ : out std_logic; + DSPADDR : out std_logic_vector (31 downto 0); + DSPDAT : inout std_logic_vector (31 downto 0); + DSP_ACK : in std_logic; + DSP_BM : inout std_logic; + DSP_BMS : out std_logic; + DSP_BOFF : out std_logic; + DSP_BRST : inout std_logic; + DSP_HBG : in std_logic; + DSP_HBR : out std_logic; + DSP_IRQ : out std_logic_vector (3 downto 0); + DSP_RD : out std_logic; + DSP_RESET : out std_logic; + DSP_RESET_OUT : in std_logic; + DSP_WRH : out std_logic; + DSP_WRL : out std_logic; + VSD_A : out std_logic_vector (12 downto 0); + VSD_BA : out std_logic_vector (1 downto 0); + VSD_CAS : out std_logic; + VSD_CKE : out std_logic; + VSD_CLOCK : out std_logic; + VSD_CSEH : out std_logic; + VSD_CSEL : out std_logic; + VSD_D : inout std_logic_vector (31 downto 0); + VSD_DQML : out std_logic_vector (3 downto 0); + VSD_RAS : out std_logic; + VSD_WE : out std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector (15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector (15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + SFP_LOS : in std_logic; + SFP_TX_DIS : out std_logic; + SFP_TX_FAULT : in std_logic; + ADO_LV : in std_logic_vector(51 downto 0); + ADO_TTL : inout std_logic_vector(46 downto 2); + ADO_CLK1 : in std_logic; + ADO_CLK2 : in std_logic + ); +end component; + +signal VIRT_CLK_i : std_logic; +signal VIRT_CLKB_i : std_logic; +signal RESET_VIRT_i : std_logic; +signal DBAD_i : std_logic; +signal DGOOD_i : std_logic; +signal DINT_i : std_logic; +signal DWAIT_i : std_logic; +signal FS_PB_i : std_logic_vector (17 downto 0); +signal FS_PC_i : std_logic_vector (17 downto 0); +signal ETRAX_IRQ_i : std_logic; +signal DSPADDR_i : std_logic_vector (31 downto 0); +signal DSPDAT_i : std_logic_vector (31 downto 0); +signal DSP_ACK_i : std_logic; +signal DSP_BM_i : std_logic; +signal DSP_BMS_i : std_logic; +signal DSP_BOFF_i : std_logic; +signal DSP_BRST_i : std_logic; +signal DSP_HBG_i : std_logic; +signal DSP_HBR_i : std_logic; +signal DSP_IRQ_i : std_logic_vector (3 downto 0); +signal DSP_RD_i : std_logic; +signal DSP_RESET_i : std_logic; +signal DSP_RESET_OUT_i : std_logic; +signal DSP_WRH_i : std_logic; +signal DSP_WRL_i : std_logic; +signal VSD_A_i : std_logic_vector (12 downto 0); +signal VSD_BA_i : std_logic_vector (1 downto 0); +signal VSD_CAS_i : std_logic; +signal VSD_CKE_i : std_logic; +signal VSD_CLOCK_i : std_logic; +signal VSD_CSEH_i : std_logic; +signal VSD_CSEL_i : std_logic; +signal VSD_D_i : std_logic_vector (31 downto 0); +signal VSD_DQML_i : std_logic_vector (3 downto 0); +signal VSD_RAS_i : std_logic; +signal VSD_WE_i : std_logic; +signal TLK_CLK_i : std_logic; +signal TLK_ENABLE_i : std_logic; +signal TLK_LCKREFN_i : std_logic; +signal TLK_LOOPEN_i : std_logic; +signal TLK_PRBSEN_i : std_logic; +signal TLK_RXD_i : std_logic_vector (15 downto 0); +signal TLK_RX_CLK_i : std_logic; +signal TLK_RX_DV_i : std_logic; +signal TLK_RX_ER_i : std_logic; +signal TLK_TXD_i : std_logic_vector (15 downto 0); +signal TLK_TX_EN_i : std_logic; +signal TLK_TX_ER_i : std_logic; +signal SFP_LOS_i : std_logic; +signal SFP_TX_DIS_i : std_logic; +signal SFP_TX_FAULT_i : std_logic; +signal ADO_LV_i : std_logic_vector(51 downto 0); +signal ADO_TTL_i : std_logic_vector(46 downto 2); +signal ADO_CLK1_i : std_logic; +signal ADO_CLK2_i : std_logic; +signal vulom_lvl1_tag : std_logic_vector(15 downto 0); + + +begin -- cts_tb + test: cts + port map ( + VIRT_CLK => VIRT_CLK_i, + VIRT_CLKB => VIRT_CLKB_i, + RESET_VIRT => RESET_VIRT_i, + DBAD => DBAD_i, + DGOOD => DGOOD_i, + DINT => DINT_i, + DWAIT => DWAIT_i, + FS_PB => FS_PB_i, + FS_PC => FS_PC_i, + ETRAX_IRQ => ETRAX_IRQ_i, + DSPADDR => DSPADDR_i, + DSPDAT => DSPDAT_i, + DSP_ACK => DSP_ACK_i, + DSP_BM => DSP_BM_i, + DSP_BMS => DSP_BMS_i, + DSP_BOFF => DSP_BOFF_i, + DSP_BRST => DSP_BRST_i, + DSP_HBG => DSP_HBG_i, + DSP_HBR => DSP_HBR_i, + DSP_IRQ => DSP_IRQ_i, + DSP_RD => DSP_RD_i, + DSP_RESET => DSP_RESET_i, + DSP_RESET_OUT => DSP_RESET_OUT_i, + DSP_WRH => DSP_WRH_i, + DSP_WRL => DSP_WRL_i, + VSD_A => VSD_A_i, + VSD_BA => VSD_BA_i, + VSD_CAS => VSD_CAS_i, + VSD_CKE => VSD_CKE_i, + VSD_CLOCK => VSD_CLOCK_i, + VSD_CSEH => VSD_CSEH_i, + VSD_CSEL => VSD_CSEL_i, + VSD_D => VSD_D_i, + VSD_DQML => VSD_DQML_i, + VSD_RAS => VSD_RAS_i, + VSD_WE => VSD_WE_i, + TLK_CLK => TLK_CLK_i, + TLK_ENABLE => TLK_ENABLE_i, + TLK_LCKREFN => TLK_LCKREFN_i, + TLK_LOOPEN => TLK_LOOPEN_i, + TLK_PRBSEN => TLK_PRBSEN_i, + TLK_RXD => TLK_RXD_i, + TLK_RX_CLK => TLK_RX_CLK_i, + TLK_RX_DV => TLK_RX_DV_i, + TLK_RX_ER => TLK_RX_ER_i, + TLK_TXD => TLK_TXD_i, + TLK_TX_EN => TLK_TX_EN_i, + TLK_TX_ER => TLK_TX_ER_i, + SFP_LOS => SFP_LOS_i, + SFP_TX_DIS => SFP_TX_DIS_i, + SFP_TX_FAULT => SFP_TX_FAULT_i, + ADO_LV => ADO_LV_i, + ADO_TTL => ADO_TTL_i, + ADO_CLK1 => ADO_CLK1_i, + ADO_CLK2 => ADO_CLK2_i); + clock_gclk : process + begin + VIRT_CLK_i <= '0'; + VIRT_CLKB_i <= '1'; + wait for 5 ns; + VIRT_CLKB_i <= '0'; + VIRT_CLK_i <= '1'; + wait for 5 ns; + end process; + clock_tlk_clk : process + begin + TLK_CLK_i <= '0'; + wait for 5 ns; + TLK_CLK_i <= '1'; + wait for 5 ns; + end process; + clock_tlk_rx_clk : process + begin + TLK_RX_CLK_i <= '0'; + wait for 5 ns; + TLK_RX_CLK_i <= '1'; + wait for 5 ns; + end process; + ------------------------------------------------------------------------------- +-- etrax_int_test +------------------------------------------------------------------------------- + etrax_intf : PROCESS + BEGIN + + --reading DSP(dev number 1) + wait for 10 ns; + RESET_VIRT_i <= '0'; + + wait for 10 ns; + FS_PC_i(16) <= '1'; + FS_PC_i(17) <= '1'; + RESET_VIRT_i <= '1'; + wait for 10 ns; + + wait for 30 ns; + FS_PC_i(15 downto 0) <= x"0000"; + FS_PC_i(16) <= '0'; + FS_PC_i(17) <= '0'; + wait on VIRT_CLK_i until FS_PB_i(16) = '0'; + wait for 20 ns; + FS_PC_i(16) <= '1'; + wait for 20 ns; + FS_PC_i(15) <= '1'; --read mode(1) + FS_PC_i(14 downto 8) <= (others => '0'); + FS_PC_i(7 downto 0) <= x"00"; --device + FS_PC_i(16) <= '0'; + FS_PC_i(17) <= '0'; + wait for 20 ns; + FS_PC_i(15 downto 0) <= x"0000"; --address upper part + FS_PC_i(16) <= '1'; + FS_PC_i(17) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '1'; + FS_PC_i(15 downto 0) <= x"0025"; --adrees lower part + FS_PC_i(16) <= '1'; + FS_PC_i(17) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + wait on VIRT_CLK_i until FS_PB_i(16)= '1'; + FS_PC_i(16) <= '1'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + wait on VIRT_CLK_i until FS_PB_i(16) = '0'; + FS_PC_i(16) <= '1'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + wait on VIRT_CLK_i until FS_PB_i(16)= '1'; + FS_PC_i(16) <= '1'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + --writing DSP + wait for 20 ns; + FS_PC_i(16) <= '1'; + wait for 20 ns; + FS_PC_i(15) <= '0'; --write mode + FS_PC_i(14 downto 8) <= (others => '0'); + FS_PC_i(7 downto 0) <= x"00"; --device + FS_PC_i(16) <= '0'; + FS_PC_i(17) <= '0'; + wait for 20 ns; + FS_PC_i(15 downto 0) <= x"0000"; --address upper part + FS_PC_i(16) <= '1'; + FS_PC_i(17) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '1'; + FS_PC_i(15 downto 0) <= x"0000"; --adrees lower part + FS_PC_i(16) <= '1'; + FS_PC_i(17) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + wait for 20 ns; + FS_PC_i(15 downto 0) <= x"0000"; --data upper part + FS_PC_i(16) <= '1'; + FS_PC_i(17) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + wait for 20 ns; + FS_PC_i(15 downto 0) <= x"0080"; --data lower part - 1 switch on + --internal generation of trigger + FS_PC_i(16) <= '1'; + FS_PC_i(17) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '0'; + wait for 20 ns; + FS_PC_i(16) <= '1'; + wait for 20 ns; + FS_PC_i(16) <= '0'; +-- wait on VIRT_CLK_i until FS_PB_i(16)= '1'; + loop + wait on VIRT_CLK_i until FS_PB_i(16) = '1'; + FS_PC_i(17) <= '1'; + wait for 100 ns; + FS_PC_i(17) <= '0'; + wait for 100 ns; + end loop; + + wait; -- will wait forever + end process; + ----------------------------------------------------------------------------- + -- VULOM + ----------------------------------------------------------------------------- + ADO_TTL_i(4) <= 'Z'; + + VULOM_SENDS_TRIGGER: process + variable i,y : integer; + begin + vulom_lvl1_tag <= (others => '0'); + wait for 310 ns; + + loop + y := 0; + ADO_TTL_i(3 downto 2) <= "01"; + ADO_CLK2_i <= '1'; + wait for 10 ns; + ADO_CLK2_i <= '0'; + wait for 10 ns; + for i in 0 to 159 loop + ADO_TTL_i(3 downto 2) <= vulom_lvl1_tag (((y mod 15)+1) downto (y mod 15)); + ADO_CLK2_i <= '1'; + wait for 10 ns; + ADO_CLK2_i <= '0'; + wait for 10 ns; + y := y + 2; + end loop; -- 40ns; + wait on VIRT_CLK_i until ADO_TTL_i(4) = '0'; + vulom_lvl1_tag <= vulom_lvl1_tag + 1; + end loop; + end process VULOM_SENDS_TRIGGER; +end cts_tb; diff --git a/trb_cts/etrax_interface.vhd b/trb_cts/etrax_interface.vhd new file mode 100755 index 0000000..5354c78 --- /dev/null +++ b/trb_cts/etrax_interface.vhd @@ -0,0 +1,488 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. + + +entity etrax_interface is + port ( + CLK : in std_logic; + RESET : in std_logic; + DATA_BUS : in std_logic_vector(31 downto 0); + ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0); + ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0); + DATA_VALID : in std_logic; + ETRAX_BUS_BUSY : out std_logic; + ETRAX_IS_READY_TO_READ : out std_logic; + TDC_TCK : out std_logic; + TDC_TDI : out std_logic; + TDC_TMS : out std_logic; + TDC_TRST : out std_logic; + TDC_TDO : in std_logic; + TDC_RESET : out std_logic; + EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0); + EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0); + EXTERNAL_ACK : out std_logic; + EXTERNAL_VALID : in std_logic; + EXTERNAL_MODE : out std_logic_vector(15 downto 0); + FPGA_REGISTER_00 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_01 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_02 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_03 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_04 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_05 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_06 : out std_logic_vector(31 downto 0); + FPGA_REGISTER_07 : out std_logic_vector(31 downto 0); + FPGA_REGISTER_08 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_09 : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0A : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); +-- FPGA_REGISTER_14 : in std_logic_vector(31 downto 0); +-- FPGA_REGISTER_15 : in std_logic_vector(31 downto 0); +-- FPGA_REGISTER_16 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_17 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_18 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_19 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_20 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_21 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_22 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_23 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_24 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_25 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_26 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_27 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_28 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_29 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_30 : out std_logic_vector(31 downto 0); +-- FPGA_REGISTER_31 : out std_logic_vector(31 downto 0); + EXTERNAL_RESET : out std_logic; + LVL2_VALID : in std_logic + -- DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0) + ); +end etrax_interface; +architecture etrax_interface of etrax_interface is + component edge_to_pulse + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; + component up_counter_17bit + port ( + QOUT : out std_logic_vector(16 downto 0); + UP : in std_logic; + CLK : in std_logic; + CLR : in std_logic); + end component; + type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_ADDRESS_1, SAVE_ADDRESS_2, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_ZERO, SEND_DATA_2, WAIT_FOR_DATA, SAVING_EXTERNAL_DATA, SEND_VALID, SEND_EXTERNAL_TRIGGER ); + signal ETRAX_RW_STATE_currentstate,ETRAX_RW_STATE_nextstate : ETRAX_RW_STATE_MACHINE; + + signal etrax_trigger_pulse : std_logic; + signal rw_operation_finished_pulse : std_logic; + signal saved_rw_mode : std_logic_vector(17 downto 0); + signal saved_address : std_logic_vector (31 downto 0); + signal saved_data : std_logic_vector(31 downto 0); + signal saved_data_fpga : std_logic_vector(31 downto 0); + + signal data_to_etrax_valid : std_logic; + signal fpga_register_00_i : std_logic_vector(31 downto 0); + signal fpga_register_01_i : std_logic_vector(31 downto 0); + signal fpga_register_02_i : std_logic_vector(31 downto 0); + signal fpga_register_03_i : std_logic_vector(31 downto 0); + signal fpga_register_04_i : std_logic_vector(31 downto 0); + signal fpga_register_05_i : std_logic_vector(31 downto 0); + signal fpga_register_06_i : std_logic_vector(31 downto 0); + signal fpga_register_07_i : std_logic_vector(31 downto 0); + signal fpga_register_08_i : std_logic_vector(31 downto 0); + signal fpga_register_09_i : std_logic_vector(31 downto 0); + signal fpga_register_0A_i : std_logic_vector(31 downto 0); + signal fpga_register_0B_i : std_logic_vector(31 downto 0); + signal fpga_register_0C_i : std_logic_vector(31 downto 0); + signal fpga_register_0D_i : std_logic_vector(31 downto 0); +-- signal fpga_register_14_i : std_logic_vector(31 downto 0); +-- signal fpga_register_15_i : std_logic_vector(31 downto 0); +-- signal fpga_register_16_i : std_logic_vector(31 downto 0); +-- signal fpga_register_17_i : std_logic_vector(31 downto 0); +-- signal fpga_register_18_i : std_logic_vector(31 downto 0); +-- signal fpga_register_19_i : std_logic_vector(31 downto 0); +-- signal fpga_register_20_i : std_logic_vector(31 downto 0); +-- signal fpga_register_21_i : std_logic_vector(31 downto 0); +-- signal fpga_register_22_i : std_logic_vector(31 downto 0); +-- signal fpga_register_23_i : std_logic_vector(31 downto 0); +-- signal fpga_register_24_i : std_logic_vector(31 downto 0); +-- signal fpga_register_25_i : std_logic_vector(31 downto 0):=x"00000000"; +-- signal fpga_register_26_i : std_logic_vector(31 downto 0):=x"00000000"; +-- signal fpga_register_27_i : std_logic_vector(31 downto 0); +-- signal fpga_register_28_i : std_logic_vector(31 downto 0); +-- signal fpga_register_29_i : std_logic_vector(31 downto 0); +-- signal fpga_register_30_i : std_logic_vector(31 downto 0); +-- signal fpga_register_31_i : std_logic_vector(31 downto 0); + signal counter_for_test : std_logic_vector(16 downto 0); + signal saved_external_data : std_logic_vector(31 downto 0); + signal debug_reg_00 : std_logic_vector(3 downto 0); + signal debug_reg_01 : std_logic_vector(3 downto 0); + signal debug_reg_02 : std_logic_vector(3 downto 0); + signal debug_reg_03 : std_logic_vector(3 downto 0); + signal etrax_data_pulse_0 : std_logic; + signal etrax_data_pulse_1 : std_logic; + signal etrax_data_pulse_2 : std_logic; + signal etrax_data_pulse_3: std_logic; + signal debug_reg_04 : std_logic_vector(15 downto 0); + signal etrax_is_ready_to_read_i : std_logic; + signal pulse_clock : std_logic; + signal lvl2_not_valid_pulse : std_logic; + signal counter_for_pulses : std_logic_vector(2 downto 0); + signal internal_reset_i : std_logic; + +begin + MAKE_RESET: process (CLK, RESET) + begin + if rising_edge(CLK) then + if (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + internal_reset_i <= '1'; + elsif ETRAX_DATA_BUS_C(16)='0' and ETRAX_DATA_BUS_C(17)='0' then + internal_reset_i <= '0'; + else + internal_reset_i <= '0';--internal_reset_i; + end if; + end if; + end process MAKE_RESET; + +-- internal_reset_i <= ETRAX_DATA_BUS_C(16) and ETRAX_DATA_BUS_C(17); + ETRAX_TRIGG_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => ETRAX_DATA_BUS_C(16), + pulse => etrax_trigger_pulse); + ETRAX_READY_PULSE : edge_to_pulse + port map ( + clock => CLK, + en_clk => DATA_VALID,--'1', + signal_in => ETRAX_DATA_BUS_C(17), + pulse => etrax_is_ready_to_read_i); + MAKE_PULSES: process (CLK, RESET) + begin + if rising_edge(CLK) then + if internal_reset_i = '1' then --;(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + counter_for_pulses <= "000"; + -- pulse_clock <= '0'; + else +-- pulse_clock <= not pulse_clock; + counter_for_pulses <= counter_for_pulses + 1; + end if; + end if; + end process make_pulses; + LVL2_NOT_VALID_READY_PULSE : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', +-- signal_in => pulse_clock, + signal_in => counter_for_pulses(2), + pulse => lvl2_not_valid_pulse); +-- ETRAX_READY_CLOCKED : process (CLK, RESET,ETRAX_DATA_BUS_C(16),ETRAX_DATA_BUS_C(17)) +-- begin +-- if rising_edge(CLK) then +-- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then +-- ETRAX_RW_STATE_currentstate <= IDLE; +-- else +-- ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate; +-- end if; +-- end if; +-- end process ETRAX_FPGA_COMUNICATION_CLOCK; + + ETRAX_IS_READY_TO_READ <= etrax_is_ready_to_read_i or (DATA_VALID and lvl2_not_valid_pulse and LVL2_VALID); + RW_FINISHED_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => EXTERNAL_VALID, + pulse => rw_operation_finished_pulse); + DELAY_COUNTER : up_counter_17bit + port map ( + CLK => CLK, + UP => etrax_trigger_pulse, + CLR => RESET, + QOUT => counter_for_test + ); + TDC_TRST <= not fpga_register_06_i(2);--etrax_trigger_pulse and ETRAX_DATA_BUS_C(17); + TDC_RESET <= fpga_register_06_i(1); + EXTERNAL_RESET <= internal_reset_i;--ETRAX_DATA_BUS_C(16) and ETRAX_DATA_BUS_C(17); + ETRAX_BUS_BUSY <= '0' when ETRAX_RW_STATE_currentstate = IDLE else '1'; + REGISTERS: process (CLK) + begin + if rising_edge(CLK) then +-- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + fpga_register_02_i <= FPGA_REGISTER_02; + fpga_register_03_i <= FPGA_REGISTER_03; + fpga_register_04_i <= FPGA_REGISTER_04; + fpga_register_05_i <= FPGA_REGISTER_05; + FPGA_REGISTER_06 <= fpga_register_06_i; --this used for TDCjtag enable(0) + FPGA_REGISTER_07 <= fpga_register_07_i; + fpga_register_08_i <= FPGA_REGISTER_08; + fpga_register_09_i <= FPGA_REGISTER_09; + fpga_register_0A_i <= FPGA_REGISTER_0A; + fpga_register_0B_i <= FPGA_REGISTER_0B; + fpga_register_0c_i <= FPGA_REGISTER_0C; + fpga_register_0d_i <= FPGA_REGISTER_0D; + end if; + end process REGISTERS; + -- DEBUG_REGISTER_OO(7 downto 0) <= fpga_register_00_i(7 downto 0); + -- FPGA_REGISTER_23(7 downto 0) <= fpga_register_00_i(7 downto 0); + ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK, RESET,ETRAX_DATA_BUS_C(16),ETRAX_DATA_BUS_C(17)) + begin + if rising_edge(CLK) then + if internal_reset_i = '1' then --(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + ETRAX_RW_STATE_currentstate <= IDLE; + else + ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate; + end if; + end if; + end process ETRAX_FPGA_COMUNICATION_CLOCK; + ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,etrax_trigger_pulse,saved_rw_mode(15),rw_operation_finished_pulse) + begin + fpga_register_00_i <= x"00000001"; + case ETRAX_RW_STATE_currentstate is + when IDLE => + fpga_register_00_i <= x"00000001"; + if etrax_trigger_pulse = '1' and DATA_VALID ='0' then + ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1; + else + ETRAX_RW_STATE_nextstate <= IDLE; + end if; + when SAVE_ADDRESS_1 => + fpga_register_00_i <= x"00000002"; + if etrax_trigger_pulse = '1' then + ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2; + else + ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1; + end if; + when SAVE_ADDRESS_2 => + fpga_register_00_i <= x"00000003"; + if etrax_trigger_pulse = '1' then + if saved_rw_mode(15) = '1' then + ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER; + else + ETRAX_RW_STATE_nextstate <= SAVE_DATA_1; + end if; + else + ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2; + end if; + when SAVE_DATA_1 => + fpga_register_00_i <= x"00000004"; + if etrax_trigger_pulse = '1' then + ETRAX_RW_STATE_nextstate <= SAVE_DATA_2; + else + ETRAX_RW_STATE_nextstate <= SAVE_DATA_1; + end if; + when SAVE_DATA_2 => + fpga_register_00_i <= x"00000005"; + if etrax_trigger_pulse = '1' then + ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER; + else + ETRAX_RW_STATE_nextstate <= SAVE_DATA_2; + end if; + when SEND_EXTERNAL_TRIGGER => + ETRAX_RW_STATE_nextstate <= WAIT_FOR_DATA; + when WAIT_FOR_DATA => + fpga_register_00_i <= x"00000006"; + if saved_rw_mode(15) = '0' then + ETRAX_RW_STATE_nextstate <= SEND_VALID; + elsif rw_operation_finished_pulse = '1' or saved_rw_mode(7 downto 0) = x"00" then + ETRAX_RW_STATE_nextstate <= SAVING_EXTERNAL_DATA; + else + ETRAX_RW_STATE_nextstate <= WAIT_FOR_DATA; + end if; + when SEND_VALID => + fpga_register_00_i <= x"00000007"; + if etrax_trigger_pulse = '1' then + ETRAX_RW_STATE_nextstate <= IDLE; + else + ETRAX_RW_STATE_nextstate <= SEND_VALID; + end if; + when SAVING_EXTERNAL_DATA => + ETRAX_RW_STATE_nextstate <= SEND_DATA_1; + when SEND_DATA_1 => + fpga_register_00_i <= x"00000008"; + if etrax_trigger_pulse = '1' then + ETRAX_RW_STATE_nextstate <= SEND_ZERO; + else + ETRAX_RW_STATE_nextstate <= SEND_DATA_1; + end if; + when SEND_ZERO => + fpga_register_00_i <= x"0000000a"; + if etrax_trigger_pulse = '1' then + ETRAX_RW_STATE_nextstate <= SEND_DATA_2; + else + ETRAX_RW_STATE_nextstate <= SEND_ZERO; + end if; + + when SEND_DATA_2 => + fpga_register_00_i <= x"00000009"; + if etrax_trigger_pulse = '1' then + ETRAX_RW_STATE_nextstate <= IDLE; + else + ETRAX_RW_STATE_nextstate <= SEND_DATA_2; + end if; + when others => + ETRAX_RW_STATE_nextstate <= IDLE; + end case; + end process ETRAX_FPGA_COMUNICATION; + + REGISTER_ETRAX_BUS: process (CLK, RESET,ETRAX_RW_STATE_currentstate) + begin + if rising_edge(CLK) then + if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + saved_rw_mode <= (others => '0'); + saved_address <= (others => '0'); + saved_data <= (others => '0'); + elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then + saved_rw_mode <= ETRAX_DATA_BUS_C; + elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_1 and etrax_trigger_pulse = '1' then + saved_address(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0); + elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_2 and etrax_trigger_pulse = '1' then + saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0); + elsif ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA and rw_operation_finished_pulse = '1' then + saved_external_data <= EXTERNAL_DATA_IN; + elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1 and etrax_trigger_pulse = '1' then + saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0); + elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2 and etrax_trigger_pulse = '1' then + saved_data(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0); + else + saved_rw_mode <= saved_rw_mode; + saved_address <= saved_address; + saved_data <= saved_data; + end if; + end if; + end process REGISTER_ETRAX_BUS; + EXTERNAL_ADDRESS <= saved_address; + EXTERNAL_MODE <= saved_rw_mode(15 downto 0); + EXTERNAL_DATA_OUT <= saved_data; + EXTERNAL_DATA_LOGIC: process (CLK, RESET) + begin + if rising_edge(CLK) then + if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + EXTERNAL_ACK <= '0'; + elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '1' then + EXTERNAL_ACK <= '1'; + elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '0' then + EXTERNAL_ACK <= '1'; + else + EXTERNAL_ACK <= '0'; + end if; + end if; + end process EXTERNAL_DATA_LOGIC; + ETRAX_DATA_BUS_CHOOSE : process (CLK, RESET,ETRAX_RW_STATE_currentstate, DATA_VALID) + begin + if rising_edge(CLK) then + if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";--(others => 'Z'); + elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then + ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16);--fpga_register_07_i(15 downto 0);-- + ETRAX_DATA_BUS_B(16) <= '1'; + -- ETRAX_DATA_BUS_B(17) <= '0'; + elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 or ETRAX_RW_STATE_currentstate = SEND_VALID then + ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(15 downto 0);--fpga_register_07_i(15 downto 0);-- + ETRAX_DATA_BUS_B(16) <= '1'; + -- ETRAX_DATA_BUS_B(17) <= '0'; + elsif DATA_VALID = '1' then + ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0); + -- ETRAX_DATA_BUS_B(17) <= CLK; + ETRAX_DATA_BUS_B(16) <= '1' and not(LVL2_VALID); + else + ETRAX_DATA_BUS_B(15 downto 0) <= fpga_register_06_i(15 downto 0); +-- ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0);--fpga_register_07_i(15 downto 0); + ETRAX_DATA_BUS_B(16) <= '0'; + end if; + end if; + end process ETRAX_DATA_BUS_CHOOSE; + +ETRAX_DATA_BUS_B(17) <= CLK when DATA_VALID = '1' else '0'; +-- ETRAX_DATA_BUS_B(17) <= 'Z'; + TDC_JAM_SIGNALS : process (CLK, RESET, DATA_VALID, fpga_register_06_i(0)) + begin + if rising_edge(CLK) then + if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then + TDC_TMS <= '1'; + TDC_TCK <= '1'; + TDC_TDI <= '1'; + ETRAX_DATA_BUS_C <= (others => 'Z'); + elsif fpga_register_06_i(0) = '1' then +-- ETRAX_DATA_BUS_C <= (others => 'Z'); + TDC_TMS <= ETRAX_DATA_BUS_C(1); + TDC_TCK <= ETRAX_DATA_BUS_C(2); + TDC_TDI <= ETRAX_DATA_BUS_C(3); + ETRAX_DATA_BUS_C(0) <= TDC_TDO; + ETRAX_DATA_BUS_C(17 downto 1) <= (others => 'Z'); +-- ETRAX_DATA_BUS_C(13 downto 0) <= (others => 'Z'); + elsif DATA_VALID = '1' then + ETRAX_DATA_BUS_C(15 downto 0) <= DATA_BUS(31 downto 16); + ETRAX_DATA_BUS_C(16) <= 'Z'; + ETRAX_DATA_BUS_C(17) <= 'Z'; + TDC_TMS <= '1'; + TDC_TCK <= '1'; + TDC_TDI <= '1'; + else + TDC_TMS <= '1'; + TDC_TCK <= '1'; + TDC_TDI <= '1'; + ETRAX_DATA_BUS_C <= (others => 'Z'); + end if; + end if; + end process TDC_JAM_SIGNALS; + DATA_SOURCE_SELECT : process (CLK,RESET,saved_rw_mode,saved_address) + begin + if rising_edge(CLK) then + if internal_reset_i = '1' then--(ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then + fpga_register_06_i <= x"00000000"; + else + case saved_rw_mode(7 downto 0) is + when "00000000" => + if saved_rw_mode(15) = '1' then + case saved_address(31 downto 0) is + when x"00000000" => saved_data_fpga <= fpga_register_00_i; + when x"00000001" => saved_data_fpga <= fpga_register_01_i; + when x"00000002" => saved_data_fpga <= fpga_register_02_i; + when x"00000003" => saved_data_fpga <= fpga_register_03_i; + when x"00000004" => saved_data_fpga <= fpga_register_04_i; + when x"00000005" => saved_data_fpga <= fpga_register_05_i; + when x"00000006" => saved_data_fpga <= fpga_register_06_i; + when x"00000007" => saved_data_fpga <= fpga_register_07_i; + when x"00000008" => saved_data_fpga <= fpga_register_08_i; + when x"00000009" => saved_data_fpga <= fpga_register_09_i; + when x"0000000A" => saved_data_fpga <= fpga_register_0A_i; + when x"0000000B" => saved_data_fpga <= fpga_register_0B_i; + when x"0000000C" => saved_data_fpga <= fpga_register_0C_i; + when x"0000000D" => saved_data_fpga <= fpga_register_0D_i; + when others => saved_data_fpga <= x"deadface"; + end case; + elsif saved_rw_mode(15) = '0' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then + case saved_address(31 downto 0) is + when x"00000006" => fpga_register_06_i <= saved_data; + when x"00000007" => fpga_register_07_i <= saved_data; + when others => null; + end case; + end if; + when "00000001" => --DSP write read + saved_data_fpga <= saved_external_data; + when x"02" => + saved_data_fpga <= saved_external_data; + when x"03" => + saved_data_fpga <= saved_external_data; + when others => --ADDON board write read + saved_data_fpga <= x"deadface"; + end case; + end if; + end if; + end process DATA_SOURCE_SELECT; +end etrax_interface; diff --git a/trb_cts/f_divider.vhd b/trb_cts/f_divider.vhd new file mode 100644 index 0000000..7366e7e --- /dev/null +++ b/trb_cts/f_divider.vhd @@ -0,0 +1,173 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_arith.all; +use IEEE.STD_LOGIC_unsigned.all; + + +entity f_divider is + + generic( + cnt : integer := 4000 -- Der Teiler teilt durch "cnt" , wenn Test = 0 ist. -- + ); + + port ( + clk : in std_logic; + ena_cnt : in std_logic; + f_div : out std_logic + ); + +end f_divider; + + + +architecture arch_f_divider of f_divider is + + function How_many_Bits (int : integer) return integer is + variable i, tmp : integer; + begin + tmp := int; + i := 0; + while tmp > 0 loop + tmp := tmp / 2; + i := i + 1; + end loop; + return i; + end How_many_bits; + + + --+ + --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können? | + --+ + constant c_counter_width : integer := How_many_Bits(cnt - 2); + + --+ ---------------------------------------------------------------------------------------------+ + --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt" | + --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne | + --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung. | + --+ ---------------------------------------------------------------------------------------------+ + signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1); + + --+ ---------------------------------------------------------------------------------------------+ + --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem | + --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt. | + --+ ---------------------------------------------------------------------------------------------+ + constant c_ld_value : integer := cnt - 2; + +begin + p_f_divider : process (clk) + begin + if clk'event and clk = '1' then + if s_counter(s_counter'high) = '1' then -- Bei underflow wird neu geladen -- + s_counter <= conv_std_logic_vector(c_ld_value, s_counter'length); + elsif ena_cnt = '1' then + if s_counter(s_counter'high) = '0' then -- Kein underflow erreicht weiter -- + s_counter <= s_counter - 1; -- subtrahieren. -- + end if; + end if; + end if; + end process p_f_divider; + + f_div <= s_counter(s_counter'high); + +end arch_f_divider; + + + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +--library synplify; +--use synplify.attributes.all; + + +entity edge_to_pulse is + + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + +end edge_to_pulse; + +architecture arch_edge_to_pulse of edge_to_pulse is + signal signal_sync : std_logic; + signal old_sync : std_logic; + type state is (idle, high, wait_for_low); -- state + signal current_state, next_state : state; + +begin -- arch_edge_to_pulse + + fsm : process (clock) + begin -- process fsm + if rising_edge(clock) then -- rising clock edge + if en_clk = '1' then + current_state <= next_state; + signal_sync <= signal_in; + end if; + end if; + end process fsm; + + + fsm_comb : process (current_state, signal_sync) + begin -- process fsm_comb + case current_state is + when idle => + pulse <= '0'; + if signal_sync = '1' then + next_state <= high; + else + next_state <= idle; + end if; + when high => + pulse <= '1'; + next_state <= wait_for_low; +-- when wait_for_low_1 => +-- pulse <= '1'; +-- next_state <= wait_for_low; + when wait_for_low => + pulse <= '0'; + if signal_sync = '0' then + next_state <= idle; + else + next_state <= wait_for_low; + end if; + when others => + next_state <= idle; + end case; + end process fsm_comb; + + +end arch_edge_to_pulse; + + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +package support is + + component f_divider + generic ( + cnt : integer); + port ( + clk : in std_logic; + ena_cnt : in std_logic; + f_div : out std_logic); + end component; + + component edge_to_pulse + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; + + +end support; + diff --git a/trb_cts/fpga_to_etrax_data_flow.vhd b/trb_cts/fpga_to_etrax_data_flow.vhd new file mode 100644 index 0000000..f7206df --- /dev/null +++ b/trb_cts/fpga_to_etrax_data_flow.vhd @@ -0,0 +1,520 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VComponents.all; +entity fpga_to_etrax_data_flow is + port ( + CLK : in std_logic; + RESET : in std_logic; + START_READOUT : in std_logic; + HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0); + COUNTER_0 : in std_logic_vector(31 downto 0); + COUNTER_1 : in std_logic_vector(31 downto 0); + COUNTER_2 : in std_logic_vector(31 downto 0); + COUNTER_3 : in std_logic_vector(31 downto 0); + COUNTER_4 : in std_logic_vector(31 downto 0); + COUNTER_5 : in std_logic_vector(31 downto 0); + COUNTER_6 : in std_logic_vector(31 downto 0); + COUNTER_7 : in std_logic_vector(31 downto 0); + COUNTER_8 : in std_logic_vector(31 downto 0); + COUNTER_9 : in std_logic_vector(31 downto 0); + COUNTER_a : in std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector (31 downto 0); --data to ETRAX (LVL2) + DATA_VALID : out std_logic; -- The DATA_OUT can be written + ETRAX_IS_READY_TO_READ : in std_logic; + LVL1_BUSY : out std_logic; + CTS_ETRAX_REGISTER_00 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_01 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_02 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_03 : out std_logic_vector(31 downto 0); + CTS_ETRAX_REGISTER_04 : out std_logic_vector(31 downto 0) + ); +end fpga_to_etrax_data_flow; +architecture fpga_to_etrax_data_flow of fpga_to_etrax_data_flow is + component edge_to_pulse + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; + component up_down_counter_16_bit + port ( + QOUT : out std_logic_vector(15 downto 0); + UP : in std_logic; + DOWN : in std_logic; + CLK : in std_logic; + CLR : in std_logic + ); + end component; + component BUFG + port( + O: out std_ulogic; + I: in std_ulogic + ); + end component; + component up_counter_8bit + port ( + QOUT : out std_logic_vector(7 downto 0); + UP : in std_logic; + CLK : in std_logic; + CLR : in std_logic); + end component; + component lvl1_fifo + port ( + clk : IN std_logic; + din : IN std_logic_VECTOR(31 downto 0); + rd_en : IN std_logic; + rst : IN std_logic; + wr_en : IN std_logic; + data_count : OUT std_logic_VECTOR(13 downto 0); + dout : OUT std_logic_VECTOR(31 downto 0); + empty : OUT std_logic; + full : OUT std_logic); + end component; + signal tdc_ready : std_logic; + signal counter_0_i : std_logic_vector(31 downto 0); + signal counter_1_i : std_logic_vector(31 downto 0); + signal counter_2_i : std_logic_vector(31 downto 0); + signal counter_3_i : std_logic_vector(31 downto 0); + signal counter_4_i : std_logic_vector(31 downto 0); + signal counter_5_i : std_logic_vector(31 downto 0); + signal counter_6_i : std_logic_vector(31 downto 0); + signal counter_7_i : std_logic_vector(31 downto 0); + signal counter_8_i : std_logic_vector(31 downto 0); + signal counter_9_i : std_logic_vector(31 downto 0); + signal counter_a_i : std_logic_vector(31 downto 0); + signal add_data_counter : std_logic_vector(7 downto 0):=(others => '0'); + signal add_data_pulse : std_logic; + signal first_header : std_logic_vector(31 downto 0):=(others => '0'); + signal second_header : std_logic_vector(31 downto 0):=(others => '0'); + signal words_in_event : std_logic_vector(15 downto 0):=(others => '0'); + signal tdc_data_valid_i : std_logic; + signal how_many_words_in_event : std_logic_vector(16 downto 0); + signal delay_up : std_logic; + signal delay_clr : std_logic; + signal delay_qout : std_logic_vector(7 downto 0); + signal lvl1_trigger_pulse_start : std_logic; + signal lvl1_trigger_pulse_delay : std_logic; + type DELAY_FSM_TRIGG is + (IDLE ,DELAY_1,DELAY_2); + signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG; + type LVL1_START_FSM is + (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_TOKEN, SAVE_ADD_DATA_1, SAVE_ADD_DATA_2, SAVE_ADD_DATA_3, SAVE_ADD_DATA_4, SEND_LVL2_TRIGG); + signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM; + type LVL2_START_FSM is + (IDLE, READOUT_WORD1, READOUT_WORD2 ,SAVE_EVENT_SIZE ,SEND_DATA1); + signal LVL2_START_fsm_currentstate, LVL2_START_fsm_nextstate : LVL2_START_FSM; + signal lvl1_busy_i : std_logic; + signal lvl1_busy_ff : std_logic; + signal lvl1_memory_busy_i : std_logic; + signal lvl2_busy_i : std_logic; + signal lvl1_trigger_pulse : std_logic; + signal lvl1_tdc_trigg_i : std_logic; + signal lvl1_tdc_trigg_ff : std_logic; + + signal trigger_register_00_i : std_logic_vector(5 downto 0); + signal lvl2_busy_end_pulse : std_logic; + signal not_tdc_data_valid_i : std_logic; + + signal not_tdc_clk : std_logic; + signal test_counter_0 : std_logic_vector(7 downto 0); + signal test_counter_1 : std_logic_vector(7 downto 0); + signal test_counter_2 : std_logic_vector(7 downto 0); + signal test_counter_3 : std_logic_vector(7 downto 0); + signal add_data_i : std_logic_vector(31 downto 0); + signal lvl1_fifo_out : std_logic_vector(31 downto 0); + signal lvl1_fifo_in : std_logic_vector(31 downto 0); + signal lvl1_fifo_counter : std_logic_vector(13 downto 0); + signal lvl1_fifo_empty : std_logic; + signal lvl1_fifo_full : std_logic; + signal lvl1_fifo_wr_en : std_logic; + signal lvl1_fifo_rd_en : std_logic; + signal lvl1_or_lvl2_is_busy : std_logic; + signal trigger_with_gen_pulse : std_logic; + signal lvl1_tag_minus1 : std_logic_vector(15 downto 0); + signal lvl2_debug : std_logic_vector(2 downto 0); + signal tdc_start_i : std_logic; + signal lvl2_busy_start_pulse : std_logic; + + signal lvl1_tdc_trigg_i_fsm : std_logic; + signal lvl1_fifo_wr_en_fsm : std_logic; + signal lvl1_fifo_in_fsm : std_logic_vector(31 downto 0); + signal lvl1_buffer_rd_en_fsm : std_logic; + signal lvl1_busy_i_fsm : std_logic; + signal lvl1_fifo_rd_en_fsm : std_logic; + signal tdc_data_valid_i_fsm : std_logic; +begin + + + CTS_ETRAX_REGISTER : process (CLK, RESET) + begin + if rising_edge(CLK) then + CTS_ETRAX_REGISTER_00(0) <= '0'; + CTS_ETRAX_REGISTER_00(1) <= '0'; + CTS_ETRAX_REGISTER_00(2) <= '0'; + CTS_ETRAX_REGISTER_00(3) <= '0'; + CTS_ETRAX_REGISTER_00(13 downto 4) <= (others => '0'); + CTS_ETRAX_REGISTER_00(14) <= lvl1_busy_i; + CTS_ETRAX_REGISTER_00(15) <= lvl1_or_lvl2_is_busy;--lvl1_memory_busy_i; + CTS_ETRAX_REGISTER_00(30) <= lvl1_fifo_wr_en; + CTS_ETRAX_REGISTER_00(31) <= lvl2_busy_i; + CTS_ETRAX_REGISTER_00(29 downto 16) <= lvl1_fifo_counter; + CTS_ETRAX_REGISTER_01(26 downto 0) <= lvl2_debug & trigger_register_00_i(5 downto 2) & "00" & trigger_register_00_i(1 downto 0)& how_many_words_in_event(15 downto 0); + CTS_ETRAX_REGISTER_01(31 downto 27) <= (others => '0'); + CTS_ETRAX_REGISTER_02(31 downto 0) <= (others => '0'); + CTS_ETRAX_REGISTER_03(31 downto 0) <= lvl1_fifo_out; + CTS_ETRAX_REGISTER_04(31 downto 0) <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0; + end if; + end process CTS_ETRAX_REGISTER; + LVL1_FIFO_LVL2: lvl1_fifo + port map ( + clk => CLK, + din => lvl1_fifo_in, + rd_en => lvl1_fifo_rd_en, + rst => RESET, + wr_en => lvl1_fifo_wr_en, + data_count => lvl1_fifo_counter, + dout => lvl1_fifo_out, + empty => lvl1_fifo_empty, + full => lvl1_fifo_full); + DATA_OUT <= lvl1_fifo_out; + LVL1_START : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + LVL1_START_fsm_currentstate <= IDLE; + lvl1_tdc_trigg_i <= '0'; + lvl1_fifo_wr_en <= '0'; + lvl1_busy_i <= '0'; + lvl1_tdc_trigg_i <= '0'; + else + LVL1_START_fsm_currentstate <= LVL1_START_fsm_nextstate; + lvl1_tdc_trigg_i <= lvl1_tdc_trigg_i_fsm; + lvl1_fifo_wr_en <= lvl1_fifo_wr_en_fsm; + lvl1_fifo_in <= lvl1_fifo_in_fsm ; + lvl1_busy_i <= lvl1_busy_i_fsm; + lvl1_tdc_trigg_i <= lvl1_tdc_trigg_i_fsm; + end if; + end if; + end process LVL1_START; + + + LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate, START_READOUT, add_data_counter, lvl1_or_lvl2_is_busy, how_many_add_data, add_data_i, second_header, first_header) + begin + lvl1_tdc_trigg_i_fsm <= '0'; + lvl1_fifo_wr_en_fsm <= '0'; + lvl1_busy_i_fsm <= '0'; + LVL1_START_fsm_nextstate <= IDLE; + lvl1_fifo_in_fsm <= first_header; + case (LVL1_START_fsm_currentstate) is + when IDLE => + trigger_register_00_i(5 downto 2) <= x"1"; + lvl1_fifo_wr_en_fsm <= '0'; + lvl1_fifo_in_fsm <= first_header; + lvl1_busy_i_fsm <= '0'; + if START_READOUT = '1' then + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_1; + else + LVL1_START_fsm_nextstate <= IDLE; + end if; + when SAVE_ADD_DATA_1 => + trigger_register_00_i(5 downto 2) <= x"7"; + lvl1_fifo_in_fsm <= first_header; + lvl1_fifo_wr_en_fsm <= '1'; + lvl1_busy_i_fsm <= '1'; + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_2; + when SAVE_ADD_DATA_2 => + trigger_register_00_i(5 downto 2) <= x"8"; + lvl1_fifo_in_fsm <= second_header; + lvl1_fifo_wr_en_fsm <= '1'; + lvl1_busy_i_fsm <= '1'; + if HOW_MANY_ADD_DATA = x"00" then + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_4; + else + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_3; + end if; + when SAVE_ADD_DATA_3 => + trigger_register_00_i(5 downto 2) <= x"9"; + lvl1_fifo_in_fsm <= add_data_i; + lvl1_fifo_wr_en_fsm <= '1'; + lvl1_busy_i_fsm <= '1'; + if add_data_counter = x"0f" then + LVL1_START_fsm_nextstate <= SEND_LVL2_TRIGG; + else + LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_3; + end if; + when SEND_LVL2_TRIGG => + trigger_register_00_i(5 downto 2) <= x"c"; + lvl1_fifo_in_fsm <= first_header; + lvl1_fifo_wr_en_fsm <= '0'; + lvl1_busy_i_fsm <= '1'; + lvl1_tdc_trigg_i_fsm <= '0'; + LVL1_START_fsm_nextstate <= IDLE; + when others => + trigger_register_00_i(5 downto 2) <= x"d"; + lvl1_fifo_in_fsm <= first_header; + lvl1_fifo_wr_en_fsm <= '0'; + lvl1_busy_i_fsm <= '1'; + lvl1_tdc_trigg_i_fsm <= '0'; + LVL1_START_fsm_nextstate <= IDLE; + end case; + end process LVL1_START_FSM_PROC; +-- not_tdc_clk <= TDC_CLK; + + SAVE_DATA : process (CLK, RESET,lvl1_tdc_trigg_i) + begin + if rising_edge(CLK) then + if RESET = '1' then + counter_a_i <= (others => '0'); + counter_9_i <= (others => '0'); + counter_8_i <= (others => '0'); + counter_7_i <= (others => '0'); + counter_6_i <= (others => '0'); + counter_5_i <= (others => '0'); + counter_4_i <= (others => '0'); + counter_3_i <= (others => '0'); + counter_2_i <= (others => '0'); + counter_1_i <= (others => '0'); + counter_0_i <= (others => '0'); + + + elsif START_READOUT = '1' then + counter_a_i <= COUNTER_a; + counter_9_i <= COUNTER_9; + counter_8_i <= COUNTER_8; + counter_7_i <= COUNTER_7; + counter_6_i <= COUNTER_6; + counter_5_i <= COUNTER_5; + counter_4_i <= COUNTER_4; + counter_3_i <= COUNTER_3; + counter_2_i <= COUNTER_2; + counter_1_i <= COUNTER_1; + counter_0_i <= COUNTER_0; + end if; + end if; + end process SAVE_DATA; + CHOOSE_DATA : process (CLK, RESET, add_data_counter) + begin + if rising_edge(CLK) then + if RESET = '1' then + add_data_i <= x"00000000"; + else + case add_data_counter(3 downto 0) is + when "0000" => add_data_i <= counter_a_i; + when "0001" => add_data_i <= counter_9_i; + when "0010" => add_data_i <= counter_8_i; + when "0011" => add_data_i <= counter_7_i; + when "0100" => add_data_i <= counter_6_i; + when "0101" => add_data_i <= counter_5_i; + when "0110" => add_data_i <= counter_4_i; + when "0111" => add_data_i <= counter_3_i; + when "1000" => add_data_i <= counter_2_i; + when "1001" => add_data_i <= counter_1_i; + when "1010" => add_data_i <= counter_0_i; + when others => add_data_i <= x"deadface"; + end case; + end if; + end if; + end process CHOOSE_DATA; + add_data_pulse <= '1' when SAVE_ADD_DATA_3 = LVL1_START_fsm_nextstate else '0'; + ADD_DATA_COUNTER_CONTROL : process (CLK,RESET,lvl1_tdc_trigg_i,add_data_pulse) + begin + if rising_edge(CLK) then + if RESET = '1' or START_READOUT = '1' then + add_data_counter <= x"1" & HOW_MANY_ADD_DATA(3 downto 0) - 1; + elsif add_data_pulse = '1' then + add_data_counter <= add_data_counter - 1; + end if; + end if; + end process ADD_DATA_COUNTER_CONTROL; + COUNT_WORDS_IN_EVENT : process (CLK, RESET,START_READOUT) + begin + if rising_edge(CLK) then + if RESET = '1' or START_READOUT = '1' then + words_in_event <= x"0003" + HOW_MANY_ADD_DATA; + else + words_in_event <= words_in_event; + end if; + end if; + end process COUNT_WORDS_IN_EVENT; + + first_header <= x"0" & counter_0_i(3 downto 0) & counter_1_i(7 downto 0) & words_in_event(15 downto 0); + second_header <= x"030000" & HOW_MANY_ADD_DATA; + + ----------------------------------------------------------------------------- + ---------------------------------------------------------------------------- + -- LVL2 logic (only CLK domain) + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + LVL2_START : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + LVL2_START_fsm_currentstate <= IDLE; + lvl1_fifo_rd_en <= '0'; + tdc_data_valid_i <= '0'; + else + lvl1_fifo_rd_en <= lvl1_fifo_rd_en_fsm; + tdc_data_valid_i <= tdc_data_valid_i_fsm; + LVL2_START_fsm_currentstate <= LVL2_START_fsm_nextstate; + end if; + end if; + end process LVL2_START; + START_LVL2_FSM: process (LVL2_START_fsm_currentstate, LVL1_START_fsm_currentstate, how_many_words_in_event, lvl1_fifo_out, etrax_is_ready_to_read) + begin + lvl2_debug (2 downto 0) <= "000"; + lvl1_fifo_rd_en_fsm <= '0'; + tdc_data_valid_i_fsm <= '0'; + LVL2_START_fsm_nextstate <= IDLE; + case (LVL2_START_fsm_currentstate) is + when IDLE => + lvl2_debug (2 downto 0) <= "001"; + lvl1_fifo_rd_en_fsm <= '0'; + tdc_data_valid_i_fsm <= '0'; + if LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG then + LVL2_START_fsm_nextstate <= READOUT_WORD1; + else + LVL2_START_fsm_nextstate <= IDLE; + end if; + when READOUT_WORD1 => + lvl2_debug (2 downto 0) <= "010"; + lvl1_fifo_rd_en_fsm <= '1'; + tdc_data_valid_i_fsm <= '0'; + LVL2_START_fsm_nextstate <= READOUT_WORD2; + when READOUT_WORD2 => + lvl2_debug (2 downto 0) <= "011"; + lvl1_fifo_rd_en_fsm <= '0'; + tdc_data_valid_i_fsm <= '0'; + LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE; + when SAVE_EVENT_SIZE => + lvl2_debug (2 downto 0) <= "100"; + lvl1_fifo_rd_en_fsm <= '0'; + tdc_data_valid_i_fsm <= '0'; + LVL2_START_fsm_nextstate <= SEND_DATA1; + when SEND_DATA1 => + lvl2_debug (2 downto 0) <= "101"; + lvl1_fifo_rd_en_fsm <= ETRAX_IS_READY_TO_READ; + tdc_data_valid_i_fsm <= '1'; + if how_many_words_in_event(15 downto 0) = x"0000" then + LVL2_START_fsm_nextstate <= IDLE; + else + LVL2_START_fsm_nextstate <= SEND_DATA1; + end if; + end case; + end process START_LVL2_FSM; + COUNT_DOWN_READOUT: process (CLK, RESET,how_many_words_in_event) + begin + if rising_edge(CLK) then + if RESET = '1' then + how_many_words_in_event <= (others => '0'); + elsif LVL2_START_fsm_currentstate = SAVE_EVENT_SIZE then + how_many_words_in_event <= '1' & lvl1_fifo_out(15 downto 0); + elsif how_many_words_in_event > x"0ffff" and ETRAX_IS_READY_TO_READ = '1' then -- or READ_ADRESS_END_UP='1')then + how_many_words_in_event <= how_many_words_in_event - 1; + end if; + end if; + end process COUNT_DOWN_READOUT; + SYNCH_DATA_VALID: process (CLK, RESET) + begin + if rising_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?) + if RESET = '1' then + DATA_VALID <= '0'; + else + DATA_VALID <= tdc_data_valid_i; + end if; + end if; + end process SYNCH_DATA_VALID; + + not_tdc_data_valid_i <= not tdc_data_valid_i; + LVL2_BUSY_END_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => not_tdc_data_valid_i, + pulse => lvl2_busy_end_pulse); + LVL2_BUSY_SET: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or lvl2_busy_end_pulse = '1'then + lvl2_busy_i <= '0'; + elsif LVL2_START_fsm_currentstate /= IDLE then + lvl2_busy_i <= '1'; + end if; + end if; + end process LVL2_BUSY_SET; + LVL2_BUSY_START_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => lvl2_busy_i, + pulse => lvl2_busy_start_pulse); + lvl1_memory_busy_i <= '1' when lvl1_fifo_counter > "00001111111111" else '0'; + --set + --to + --max + --value + --!!!!!!! and cut data funktion should + --be implemented - with busy or max + --size or last event ? or both + LVL1_OR_LVL2_BUSY: process (CLK, RESET, lvl1_busy_i, lvl2_busy_end_pulse) + begin + if rising_edge(CLK) then + if RESET = '1' then + lvl1_or_lvl2_is_busy <= '0'; + elsif lvl1_busy_i = '1' then + lvl1_or_lvl2_is_busy <= '1'; + elsif lvl2_busy_end_pulse = '1' then + lvl1_or_lvl2_is_busy <= '0'; + end if; + end if; + end process LVL1_OR_LVL2_BUSY; + + ----------------------------------------------------------------------------- + -- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal + ----------------------------------------------------------------------------- +-- TEST_COUNTER_a : up_counter_8bit +-- port map ( +-- CLK => CLK, +-- UP => tdc_start_i, +-- CLR => RESET, +-- QOUT => test_counter_0 +-- ); +-- TEST_COUNTER_b : up_counter_8bit +-- port map ( +-- CLK => CLK, +-- UP => RECEIVED_TDC_TOKEN, +-- CLR => RESET, +-- QOUT => test_counter_1 +-- ); +-- TEST_COUNTER_c : up_counter_8bit +-- port map ( +-- CLK => CLK, +-- UP => lvl2_busy_start_pulse,--lvl2_trigger_pulse, +-- CLR => RESET, +-- QOUT => test_counter_2 +-- ); +-- TEST_COUNTER_d : up_counter_8bit +-- port map ( +-- CLK => CLK, +-- UP => lvl2_busy_end_pulse, +-- CLR => RESET, +-- QOUT => test_counter_3 +-- ); + REGITERING_SIGNALS: process (CLK, RESET) + begin + if rising_edge(CLK) then -- rising clock edge + if RESET = '1' then + LVL1_BUSY <= '0'; + else + LVL1_BUSY <= lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i; --here + end if; + end if; + end process REGITERING_SIGNALS; +end fpga_to_etrax_data_flow; + + + diff --git a/trb_cts/impact_batch_cts.txt b/trb_cts/impact_batch_cts.txt new file mode 100644 index 0000000..b5ac4c4 --- /dev/null +++ b/trb_cts/impact_batch_cts.txt @@ -0,0 +1,6 @@ +setMode -bs +setMode -bs +setCable -port stapl -file "../cts.stapl" +addDevice -p 1 -file "cts.bit" +Program -p 1 -defaultVersion 0 +quit \ No newline at end of file diff --git a/trb_cts/lvl1_fifo.ngc b/trb_cts/lvl1_fifo.ngc new file mode 100644 index 0000000..df353eb --- /dev/null +++ b/trb_cts/lvl1_fifo.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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'1', + ERROR_COUNTER => link_error_counter, --open + TLK_RECEIVED_CLK => VIRTEX_CLK, + TLK_TRANSMIT_CLK => VIRTEX_CLK, + DATA_FROM_TLK => tx_data_64(15 downto 0), + DATA_TO_TLK => data_to_tlk, + TLK_RX_ER => '0', + TLK_RX_DV => tx_ready, + TLK_TX_EN => tlk_rx_dv, + TLK_TX_ER => open, + CLK => VIRTEX_CLK, + RESET => INTERNAL_RESET, + TEST_REGISTER => test_register, + TEST_REGISTER_01 => TLK_REGISTER_01, + STOP_SENDING => link_error(3), + STOP_CHECKING => tx_ready); + +-- SFP_STATUS: sfp_status +-- port map ( +-- DATA_FROM_SFP => DATA_FROM_SFP_i, +-- READ_REQUEST => '1', +-- READ_ACK => open, +-- ADRESS_TO_SFP => x"01", +-- CLK => VIRTEX_CLK, +-- CLK_en => '1', +-- RESET => INTERNAL_RESET, +-- I2C_DATA_LINE => I2C_DATA_LINE_i, +-- I2C_CLK_LINE => I2C_CLK_LINE_i, +-- DEBUG_REG => DEBUG_REG_i, +-- SETTINGS_DONE => FS_PC(6), +-- DEBUG_REG_2 => DEBUG_REG_2_i +-- ); + rx_data_64 <= data_to_tlk & data_to_tlk & data_to_tlk & data_to_tlk; + link_converter_logic : link_converter + port map ( + CLK => VIRTEX_CLK, + RESET => INTERNAL_RESET, + SERDES_LOOPEN => open, + SERDES_LCKREFN => open, + SERDES_TX_EN => tx_en_i,--TX_EN,--open,--for_simulation_dv,--TX_EN,-- + SERDES_TX_ER => open, + SERDES_GTX_CLK => TLK_CLK, + SERDES_RXD => TLK_RXD,--for_simulation_trans,--TLK_RXD,-- + SERDES_RX_CLK => RX_CLK, + SERDES_RX_DV => RX_DV,--for_simulation_dv_b, --RX_DV,-- + SERDES_RX_ER => RX_ER, + SERDES_ENABLE => open, + SERDES_PRBSEN => open, + SERDES_TXD => TLK_TXD,--for_simulation_trans_b,--TLK_TXD,-- + RX_READY => tlk_rx_dv, + RX_DATA_64 => rx_data_64, + TX_READY => tx_ready, + TX_DATA_64 => tx_data_64, + TX_TAKE_DATA => tx_ready, + SFP_TXFAULT => '0', + SFP_TXDIS => open, + SFP_LOS => '0', + LINK_ERROR => link_error); + ENABLE <= '1'; + LOOPEN <= '0'; + PRBSEN <= '0'; + LCKREFN <= '1'; + TLK_REGISTER_00 <= TEST_REGISTER(3) & link_error(3) & INTERNAL_RESET & tx_en_i & RX_ER & error_count(10 downto 0) & TLK_RXD;-- + --link_error_counter; + + +------------------------------------------------------------------------------- +-- ---------------------------------------------------------------------------- +-- ---------------------------------------------------------------------------- +-- ---------------------------------------------------------------------------- +-- correct synchronization - check if there is optical signal on sfp - and others => +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + + RESET_VIRTEX : process (VIRTEX_CLK) + begin + if rising_edge(VIRTEX_CLK) then + if (RX_ER = '1' and RESET_COUNTER = x"00FFFFFF")or SFP_LOS = '1' then + RESET_COUNTER <= x"00000000"; + elsif RESET_COUNTER < x"00FFFFFF" then + RESET_COUNTER <= RESET_COUNTER + 1; + else + RESET_COUNTER <= RESET_COUNTER; + end if; + end if; + end process RESET_VIRTEX; + INTERNAL_RESET <= '1' when RESET_COUNTER < x"00FFFFFE" else '0'; + + ERROR_COUNTER: process (RX_CLK, RESET_VIRT,RX_ER, RX_DV) + begin + if rising_edge(RX_CLK) then + if RX_ER = '1' then + error_count <= error_count + 1; + else + error_count <= error_count; + end if; + end if; + end process ERROR_COUNTER; + + VIRTEX_CLK <= VIRT_CLK; + TX_EN <= tx_en_i when RESET_COUNTER > x"00FFFFFE" else '0';-- when INTERNAL_RESET = '0' else '0'; + TX_ER <= '0';-- when RESET_COUNTER < x"4f" else '0'; + + + + +end tlk_interface; diff --git a/trb_cts/trbv2_tlk_api.vhd b/trb_cts/trbv2_tlk_api.vhd new file mode 100644 index 0000000..ce33510 --- /dev/null +++ b/trb_cts/trbv2_tlk_api.vhd @@ -0,0 +1,143 @@ +library IEEE; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.all; +library ieee; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.all; + +entity trbv2_tlk_api is + + port ( + RESET : in std_logic; + CLK : in std_logic; + TLK_CLK : in std_logic; + TLK_ENABLE : out std_logic; + TLK_LCKREFN : out std_logic; + TLK_LOOPEN : out std_logic; + TLK_PRBSEN : out std_logic; + TLK_RXD : in std_logic_vector(15 downto 0); + TLK_RX_CLK : in std_logic; + TLK_RX_DV : in std_logic; + TLK_RX_ER : in std_logic; + TLK_TXD : out std_logic_vector(15 downto 0); + TLK_TX_EN : out std_logic; + TLK_TX_ER : out std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_VALID_OUT : out std_logic; + TLK_API_REGISTER_00 : out std_logic_vector(31 downto 0) + ); +end trbv2_tlk_api; +architecture trbv2_tlk_api of trbv2_tlk_api is + component trbv2_tlk_api_fifo + port ( + din : IN std_logic_VECTOR(17 downto 0); + rd_clk : IN std_logic; + rd_en : IN std_logic; + rst : IN std_logic; + wr_clk : IN std_logic; + wr_en : IN std_logic; + dout : OUT std_logic_VECTOR(17 downto 0); + empty : OUT std_logic; + full : OUT std_logic; + rd_data_count : OUT std_logic_VECTOR(9 downto 0); + wr_data_count : OUT std_logic_VECTOR(9 downto 0)); + end component; + signal fifo_din_a : std_logic_vector(17 downto 0); + signal fifo_dout_a : std_logic_vector(17 downto 0); + signal fifo_rst_a : std_logic; + signal fifo_rd_en_a : std_logic; + signal fifo_rd_data_count_a : std_logic_vector(9 downto 0); + signal fifo_wr_data_count_a : std_logic_vector(9 downto 0); + signal fifo_empty_a : std_logic; + signal fifo_full_a : std_logic; + signal fifo_din_m : std_logic_vector(17 downto 0); + signal fifo_dout_m : std_logic_vector(17 downto 0); + signal fifo_rst_m : std_logic; + signal fifo_rd_en_m : std_logic; + signal fifo_rd_data_count_m : std_logic_vector(9 downto 0); + signal fifo_wr_data_count_m : std_logic_vector(9 downto 0); + signal fifo_empty_m : std_logic; + signal fifo_full_m : std_logic; + signal reset_fifo_counter : std_logic_vector(7 downto 0); +begin + ----------------------------------------------------------------------------- + -- api to media + ----------------------------------------------------------------------------- + fifo_din_a <= TLK_RX_ER & TLK_RX_DV & TLK_RXD; + + OPTICAL_TO_FIFO_TO_API: trbv2_tlk_api_fifo + port map ( + din => fifo_din_a, + rd_clk => CLK, + rd_en => fifo_rd_en_a, + rst => fifo_rst_a, + wr_clk => TLK_RX_CLK, + wr_en => '1', + dout => fifo_dout_a, + empty => fifo_empty_a, + full => fifo_full_a, + rd_data_count => fifo_rd_data_count_a, + wr_data_count => fifo_wr_data_count_a); + SYNCH_DATA_OUT: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + DATA_VALID_OUT <= '0'; + DATA_OUT <= x"0000"; + else + DATA_VALID_OUT <= not(fifo_dout_a(17)) and fifo_dout_a(16); + DATA_OUT <= fifo_dout_a(15 downto 0); + end if; + end if; + end process SYNCH_DATA_OUT; + + ----------------------------------------------------------------------------- + -- media to api + ----------------------------------------------------------------------------- + fifo_din_m <= '0' & DATA_VALID_IN & DATA_IN; + + API_TO_FIFO_TO_OPTICAL: trbv2_tlk_api_fifo + port map ( + din => fifo_din_m, + rd_clk => TLK_CLK, + rd_en => fifo_rd_en_m , + rst => fifo_rst_m , + wr_clk => CLK, + wr_en => '1', + dout => fifo_dout_m, + empty => fifo_empty_m, + full => fifo_full_m, + rd_data_count => fifo_rd_data_count_m, + wr_data_count => fifo_wr_data_count_m); + + TLK_TXD <= fifo_dout_m (15 downto 0); + TLK_TX_EN <= fifo_dout_m(16); + TLK_TX_ER <= '0'; + TLK_LOOPEN <= '0'; + TLK_LCKREFN <= '1'; + TLK_ENABLE <= '1'; + TLK_PRBSEN <= '0'; + + ----------------------------------------------------------------------------- + -- all + ----------------------------------------------------------------------------- + RESET_FIFO_COUNTER_PROC: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or fifo_dout_a(17) = '1'then + reset_fifo_counter <= x"00"; + elsif reset_fifo_counter < x"f0" then + reset_fifo_counter <= reset_fifo_counter + 1; + end if; + end if; + end process RESET_FIFO_COUNTER_PROC; + fifo_rst_m <= '1' when reset_fifo_counter < x"40" else '0'; + fifo_rst_a <= '1' when reset_fifo_counter < x"40" else '0'; + fifo_rd_en_m <= '1' when reset_fifo_counter > x"46" else '0'; + fifo_rd_en_a <= '1' when reset_fifo_counter > x"46" else '0'; +end trbv2_tlk_api; diff --git a/trb_cts/trbv2_tlk_api_fifo.ngc b/trb_cts/trbv2_tlk_api_fifo.ngc new file mode 100644 index 0000000..d0694d3 --- /dev/null +++ b/trb_cts/trbv2_tlk_api_fifo.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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\ No newline at end of file diff --git a/trb_cts/trbv2_tlk_api_fifo.vhd b/trb_cts/trbv2_tlk_api_fifo.vhd new file mode 100644 index 0000000..5faa056 --- /dev/null +++ b/trb_cts/trbv2_tlk_api_fifo.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file trbv2_tlk_api_fifo.vhd when simulating +-- the core, trbv2_tlk_api_fifo. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY trbv2_tlk_api_fifo IS + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(9 downto 0); + wr_data_count: OUT std_logic_VECTOR(9 downto 0)); +END trbv2_tlk_api_fifo; + +ARCHITECTURE trbv2_tlk_api_fifo_a OF trbv2_tlk_api_fifo IS +-- synthesis translate_off +component wrapped_trbv2_tlk_api_fifo + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(9 downto 0); + wr_data_count: OUT std_logic_VECTOR(9 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_trbv2_tlk_api_fifo use entity XilinxCoreLib.fifo_generator_v3_3(behavioral) + generic map( + c_rd_freq => 100, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 18, + c_has_wr_data_count => 1, + c_implementation_type => 2, + c_family => "virtex4", + c_has_wr_rst => 0, + c_wr_freq => 100, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 1024, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 10, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 10, + c_has_almost_empty => 0, + c_rd_data_count_width => 10, + c_enable_rlocs => 0, + c_wr_pntr_width => 10, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 10, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 1021, + c_wr_depth => 1024, + c_prog_empty_thresh_negate_val => 3, + c_prog_empty_thresh_assert_val => 2, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 1022, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "1kx18", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_trbv2_tlk_api_fifo + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END trbv2_tlk_api_fifo_a; + diff --git a/trb_cts/vulom_interface.vhd b/trb_cts/vulom_interface.vhd new file mode 100644 index 0000000..0b131ba --- /dev/null +++ b/trb_cts/vulom_interface.vhd @@ -0,0 +1,244 @@ +library IEEE; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.all; +library ieee; +library work; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.all; + +entity vulom_interface is + port ( + CLK : in std_logic; + DATA_CLK : in std_logic; + RESET : in std_logic; + DATA_IN : in std_logic_vector(1 downto 0); + BUSY : out std_logic; + API_DATA : out std_logic_vector(47 downto 0); + API_RUN_OUT : in std_logic; + API_SHORT_TRANSFER : out std_logic; + API_DTYPE : out std_logic_vector(3 downto 0); + API_SEND : out std_logic; + API_WRITE_IN : out std_logic; + API_TARGET_ADDRESS : out std_logic_vector(15 downto 0); + API_SEQNR_OUT : in std_logic_vector(7 downto 0); + VULOM_INT_REG : out std_logic_vector(31 downto 0); + INTERFACE_CONTROL : in std_logic_vector(3 downto 0); + EVENT_REGISTER_00 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_01 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_02 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_03 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_04 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_05 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_06 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_07 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_08 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_09 : out std_logic_vector(31 downto 0); + EVENT_REGISTER_0a : out std_logic_vector(31 downto 0); + EVENT_REGISTER_0b : out std_logic_vector(31 downto 0); + EVENT_REGISTER_0c : out std_logic_vector(31 downto 0); + START_READOUT : out std_logic; + LVL1_TRANSFER_BUSY : in std_logic + ); +end vulom_interface; + +architecture vulom_interface of vulom_interface is + component edge_to_pulse + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic + ); + end component; + type VULOM_TO_API is (IDLE, SEND_TRIGGER_a,SEND_TRIGGER_b,SEND_TRIGGER_c, + WAIT_FOR_END_BUSY,TRIGGER_MISSMATCH); + signal VULOM_TO_API_current,VULOM_TO_API_next : VULOM_TO_API; + signal trigger_code : std_logic_vector(3 downto 0); + signal trigger_tag : std_logic_vector(15 downto 0); + signal api_ready_pulse : std_logic; + signal vulom_interface_debug : std_logic_vector(3 downto 0); + signal trigger_pulse : std_logic; + signal trigger_error : std_logic; + signal trigger_counter : std_logic_vector(15 downto 0); + signal not_api_run_out : std_logic; + signal data_trigg : std_logic; + signal fast_trigg : std_logic; + signal data_trigg_pulse : std_logic; + type vulom_data is array (160 downto 0) of std_logic_vector(1 downto 0); + signal v_data : vulom_data; + signal busy_i : std_logic; + signal data_clock_counter : std_logic_vector(7 downto 0):=x"00"; + signal not_transfer_busy : std_logic; + signal not_transfer_busy_pulse : std_logic; +begin + trigger_code <= "00" & v_data(0); + trigger_tag <= v_data(8) & v_data(7) & v_data(6) & v_data(5) & v_data(4) & v_data(3) & v_data(2) & v_data(1); + API_WRITE_IN <= '0'; + API_DATA <= (others => '0'); + API_DTYPE <= trigger_code; + API_TARGET_ADDRESS <= x"FFFF"; + API_SHORT_TRANSFER <= '1'; + not_api_run_out <= not API_RUN_OUT; + SAVE_VULOM_DATA: process (DATA_CLK) + variable vulom_data_array_counter : integer:=1; + begin + if rising_edge (DATA_CLK) then + + if vulom_data_array_counter = 161 then + vulom_data_array_counter := 1; + data_clock_counter <= (others => '0'); + else + vulom_data_array_counter := vulom_data_array_counter + 1; + v_data(vulom_data_array_counter-1) <= DATA_IN(1 downto 0); + data_clock_counter <= data_clock_counter + 1; + end if; + end if; + end process SAVE_VULOM_DATA; + EVENT_REGISTER_00 <= x"0123456" & "00" & v_data(0); + EVENT_REGISTER_01 <= v_data(16) & v_data(15) & v_data(14) & v_data(13) & v_data(12) & v_data(11) & v_data(10) & v_data(9) + & v_data(8) & v_data(7) & v_data(6) & v_data(5) & v_data(4) & v_data(3) & v_data(2) & v_data(1); + EVENT_REGISTER_02 <= v_data(32) & v_data(31) & v_data(30) & v_data(29) & v_data(28) & v_data(27) & v_data(26) & v_data(25) + & v_data(24) & v_data(23) & v_data(22) & v_data(21) & v_data(20) & v_data(19) & v_data(18) & v_data(17); + EVENT_REGISTER_03 <= v_data(48) & v_data(47) & v_data(46) & v_data(45) & v_data(44) & v_data(43) & v_data(42) & v_data(41) + & v_data(40) & v_data(39) & v_data(38) & v_data(37) & v_data(36) & v_data(35) & v_data(34) & v_data(33); + EVENT_REGISTER_04 <= v_data(64) & v_data(63) & v_data(62) & v_data(61) & v_data(60) & v_data(59) & v_data(58) & v_data(57) + & v_data(56) & v_data(55) & v_data(54) & v_data(53) & v_data(52) & v_data(51) & v_data(50) & v_data(49); + EVENT_REGISTER_05 <= v_data(80) & v_data(79) & v_data(78) & v_data(77) & v_data(76) & v_data(75) & v_data(74) & v_data(73) + & v_data(72) & v_data(71) & v_data(70) & v_data(69) & v_data(68) & v_data(67) & v_data(66) & v_data(65); + EVENT_REGISTER_06 <= v_data(96) & v_data(95) & v_data(94) & v_data(93) & v_data(92) & v_data(91) & v_data(90) & v_data(89) + & v_data(88) & v_data(87) & v_data(86) & v_data(85) & v_data(84) & v_data(83) & v_data(82) & v_data(81); + EVENT_REGISTER_07 <= v_data(112) & v_data(111) & v_data(110) & v_data(109) & v_data(108) & v_data(107) & v_data(106) & v_data(105) + & v_data(104) & v_data(103) & v_data(102) & v_data(101) & v_data(100) & v_data(99) & v_data(98) & v_data(97); + EVENT_REGISTER_08 <= v_data(128) & v_data(127) & v_data(126) & v_data(125) & v_data(124) & v_data(123) & v_data(122) & v_data(121) + & v_data(120) & v_data(119) & v_data(118) & v_data(117) & v_data(116) & v_data(115) & v_data(114) & v_data(113); + EVENT_REGISTER_09 <= v_data(144) & v_data(143) & v_data(142) & v_data(141) & v_data(140) & v_data(139) & v_data(138) & v_data(137) + & v_data(136) & v_data(135) & v_data(134) & v_data(133) & v_data(132) & v_data(131) & v_data(130) & v_data(129); + EVENT_REGISTER_0a <= v_data(160) & v_data(159) & v_data(158) & v_data(157) & v_data(156) & v_data(155) & v_data(154) & v_data(153) + & v_data(152) & v_data(151) & v_data(150) & v_data(149) & v_data(148) & v_data(147) & v_data(146) & v_data(145); +-- EVENT_REGISTER_0b <= v_data(64) & v_data(63) & v_data(62) & v_data(61) & v_data(60) & v_data(59) & v_data(58) & v_data(57) +-- & v_data(56) & v_data(55) & v_data(54) & v_data(53) & v_data(52) & v_data(51) & v_data(50) & v_data(49) +-- EVENT_REGISTER_0c <= v_data(64) & v_data(63) & v_data(62) & v_data(61) & v_data(60) & v_data(59) & v_data(58) & v_data(57) +-- & v_data(56) & v_data(55) & v_data(54) & v_data(53) & v_data(52) & v_data(51) & v_data(50) & v_data(49) +-- EVENT_REGISTER_0d <= v_data(64) & v_data(63) & v_data(62) & v_data(61) & v_data(60) & v_data(59) & v_data(58) & v_data(57) +-- & v_data(56) & v_data(55) & v_data(54) & v_data(53) & v_data(52) & v_data(51) & v_data(50) & v_data(49) + API_READY_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => not_api_run_out, + pulse => api_ready_pulse); + FAST_TRIGG_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => data_trigg, + pulse => data_trigg_pulse); + data_trigg <= '1' when data_clock_counter = 160 else '0'; --160 + SYNCH_START: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + START_READOUT <= '0'; + else + START_READOUT <= data_trigg_pulse; + end if; + end if; + end process SYNCH_START; + fast_trigg <= '1' when data_clock_counter = 17 else '0'; + TRIGGER_TAG_COUNTER: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + trigger_counter <= (others => '0'); + elsif data_trigg_pulse ='1' then + trigger_counter <= trigger_counter + 1; + else + trigger_counter <= trigger_counter; + end if; + end if; + end process TRIGGER_TAG_COUNTER; + not_transfer_busy <= not LVL1_TRANSFER_BUSY; + TRANSFER_BUSY_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => not_transfer_busy, + pulse => not_transfer_busy_pulse); + VULOM_TO_API_CLK : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + VULOM_TO_API_current <= IDLE; + else + VULOM_TO_API_current <= VULOM_TO_API_next; + end if; + end if; + end process VULOM_TO_API_CLK; + VULOM_TO_API_FSM: process (CLK, fast_trigg ,trigger_pulse,trigger_counter,trigger_tag, api_ready_pulse) + begin + case (VULOM_TO_API_current) is + when IDLE => + vulom_interface_debug <= x"1"; + busy_i <= '0'; + API_SEND <= '0'; + if fast_trigg = '1' then + VULOM_TO_API_next <= SEND_TRIGGER_a; + else + VULOM_TO_API_next <= IDLE; + end if; +-- and INTERFACE_CONTROL(0) = '1' additional state for starting + when SEND_TRIGGER_a => + vulom_interface_debug <= x"2"; + busy_i <= '1'; + API_SEND <= '0'; + VULOM_TO_API_next <= SEND_TRIGGER_b; + when SEND_TRIGGER_b => + vulom_interface_debug <= x"3"; + busy_i <= '1'; + API_SEND <= '1'; +--api + -- if API_SEQNR_OUT /= trigger_tag then +--cts only +if trigger_counter /= trigger_tag then + VULOM_TO_API_next <= TRIGGER_MISSMATCH; + else + VULOM_TO_API_next <= WAIT_FOR_END_BUSY; + end if; + when WAIT_FOR_END_BUSY => + vulom_interface_debug <= x"6"; + busy_i <= '1'; + API_SEND <= '0'; +--api +if api_ready_pulse = '1' then +--just cts +-- if not_transfer_busy_pulse = '1' then + VULOM_TO_API_next <= IDLE; + else + VULOM_TO_API_next <= WAIT_FOR_END_BUSY; + end if; + +-- else +-- VULOM_TO_API_next <= WAIT_FOR_END_BUSY; +-- end if; + when TRIGGER_MISSMATCH => + vulom_interface_debug <= x"7"; + busy_i <= '1'; + API_SEND <= '0'; + VULOM_TO_API_next <= TRIGGER_MISSMATCH; + when others => + vulom_interface_debug <= x"8"; + busy_i <= '0'; + API_SEND <= '0'; + VULOM_TO_API_next <= IDLE; + end case; + end process VULOM_TO_API_FSM; + + BUSY <=(busy_i or LVL1_TRANSFER_BUSY); + VULOM_INT_REG(3 downto 0) <= vulom_interface_debug; + VULOM_INT_REG(7 downto 4) <= trigger_code; + VULOM_INT_REG(15 downto 8) <= trigger_tag(7 downto 0); + VULOM_INT_REG(23 downto 16) <= trigger_counter(7 downto 0); + VULOM_INT_REG(31 downto 24) <= data_clock_counter(7 downto 0); +end vulom_interface;