From: Cahit Date: Tue, 26 Jan 2016 08:28:02 +0000 (+0100) Subject: tidied up the code X-Git-Tag: v2.3~53 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8d4a4b41a35e1308eb13dca7de3c89adc560854e;p=tdc.git tidied up the code --- diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd index 77cc574..5542ca6 100644 --- a/releases/tdc_v2.3/Channel_200.vhd +++ b/releases/tdc_v2.3/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2015-12-10 +-- Last update: 2016-01-25 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -146,7 +146,6 @@ architecture Channel_200 of Channel_200 is signal trg_win_end_tdc_flag_fsm : std_logic; signal trg_win_end_tdc_flag : std_logic := '0'; signal trg_win_end_tdc : std_logic := '0'; - signal trg_win_end_tdc_rst : std_logic := '0'; signal fsm_wr_debug_fsm : std_logic_vector(3 downto 0); signal fsm_wr_debug : std_logic_vector(3 downto 0); @@ -181,17 +180,7 @@ begin -- Channel_200 trg_win_end_tdc <= TRG_WIN_END_TDC_IN when rising_edge(CLK_200); end generate GEN_TrgWinEndTdcDist_Sim; - --TrgWinEndTdcDist: process (CLK_200) is - --begin - -- if rising_edge(CLK_200) then -- rising clock edge - -- if TRG_WIN_END_TDC_IN = '0' then - -- trg_win_end_tdc <= '0'; - -- elsif TRG_WIN_END_TDC_IN = '1' then - -- trg_win_end_tdc <= '1'; - -- end if; - -- end if; - --end process TrgWinEndTdcDist; - + SimAdderYes : if SIMULATION = c_YES generate --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition FC : Adder_304 @@ -202,7 +191,7 @@ begin -- Channel_200 DataB => data_b, ClkEn => ff_array_en, Result => result); - data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000FFFFFFF"&x"7FFFFFF"; + data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0001FF"&x"7FFFFFF"; data_b <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN); end generate SimAdderYes; SimAdderNo : if SIMULATION = c_NO generate diff --git a/releases/tdc_v2.3/Encoder_288_Bit.vhd b/releases/tdc_v2.3/Encoder_288_Bit.vhd index 0d917be..f98a5dd 100644 --- a/releases/tdc_v2.3/Encoder_288_Bit.vhd +++ b/releases/tdc_v2.3/Encoder_288_Bit.vhd @@ -4,7 +4,7 @@ -- File : Encoder_288_Bit.vhd -- Author : Cahit Ugur -- Created : 2011-11-28 --- Last update: 2015-08-24 +-- Last update: 2016-01-26 ------------------------------------------------------------------------------- -- Description: Encoder for 288 bits ------------------------------------------------------------------------------- @@ -68,6 +68,7 @@ architecture behavioral of Encoder_288_Bit is signal binary_code_r : std_logic_vector(8 downto 0); signal start_reg : std_logic; signal start_2reg : std_logic; + signal start_3reg : std_logic; signal address : std_logic_vector(9 downto 0); signal q_reg : std_logic_vector(7 downto 0); signal info : std_logic_vector(1 downto 0); @@ -91,6 +92,7 @@ begin thermocode(0) <= '1'; start_reg <= START_IN when rising_edge(CLK); start_2reg <= start_reg when rising_edge(CLK); + start_3reg <= start_2reg when rising_edge(CLK); mux_control_reg <= mux_control when rising_edge(CLK); mux_control_2reg <= mux_control_reg when rising_edge(CLK); mux_control_3reg <= mux_control_2reg when rising_edge(CLK); @@ -164,6 +166,8 @@ begin end if; end process Interval_Selection; + address <= start_2reg & interval_reg; + The_ROM : entity work.ROM_encoder_3 port map ( Address => address, @@ -172,7 +176,6 @@ begin Reset => RESET, Q => q_reg); - address <= start_2reg & interval_reg; interval_binary <= q_reg(2 downto 0) when rising_edge(CLK); info <= q_reg(7 downto 6) when rising_edge(CLK); info_reg <= info when rising_edge(CLK); @@ -221,8 +224,8 @@ begin -- if RESET = '1' then -- BINARY_CODE_OUT <= (others => '0'); -- FINISHED_OUT <= '0'; - -- elsif proc_finished_1 = '1' then - -- BINARY_CODE_OUT <= address; --'0' & interval_reg; + -- elsif start_2reg = '1' or start_3reg = '1' then + -- BINARY_CODE_OUT <= address; -- FINISHED_OUT <= '1'; -- else -- BINARY_CODE_OUT <= (others => '0'); diff --git a/releases/tdc_v2.3/TDC_record.vhd b/releases/tdc_v2.3/TDC_record.vhd index 5f6f23f..8b7f5bc 100644 --- a/releases/tdc_v2.3/TDC_record.vhd +++ b/releases/tdc_v2.3/TDC_record.vhd @@ -174,7 +174,7 @@ begin generic map( PORT_NUMBER => 4, PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", 3 => x"0800", others => x"0000"), - PORT_ADDR_MASK => (0 => 7, 1 => 5, 2 => 7, 3 => 3, others => 0), + PORT_ADDR_MASK => (0 => 7, 1 => 5, 2 => 7, 3 => 3, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -326,20 +326,20 @@ begin '1' after 2.5 ns when rising_edge(hit_in_s(i)); edge_rising_r(i) <= edge_rising(i) when rising_edge(CLK_TDC); edge_rising_2r(i) <= edge_rising_r(i) when rising_edge(CLK_TDC); - edge_rising_3r(i) <= edge_rising_2r(i) when rising_edge(CLK_TDC); --edge_rising_r(i) and not edge_rising_2r(i) when rising_edge(CLK_TDC); + edge_rising_3r(i) <= edge_rising_2r(i) when rising_edge(CLK_TDC); edge_falling(i) <= '0' when edge_falling_3r(i) = '1' else --edge_falling(i) when hit_edge(i) = '0' else '1' after 2 ns when falling_edge(hit_in_s(i)); edge_falling_r(i) <= edge_falling(i) when rising_edge(CLK_TDC); edge_falling_2r(i) <= edge_falling_r(i) when rising_edge(CLK_TDC); - edge_falling_3r(i) <= edge_falling_2r(i) when rising_edge(CLK_TDC); --edge_falling_r(i) and not edge_falling_2r(i) when rising_edge(CLK_TDC); + edge_falling_3r(i) <= edge_falling_2r(i) when rising_edge(CLK_TDC); hit_latch(i) <= edge_rising(i) or edge_falling_d(i); edge_falling_d_r(i) <= edge_falling_d(i) when rising_edge(CLK_TDC); edge_falling_d_2r(i) <= edge_falling_d_r(i) when rising_edge(CLK_TDC); - edge_falling_d_3r(i) <= edge_falling_d_2r(i) when rising_edge(CLK_TDC); --edge_falling_d_r(i) and not edge_falling_d_2r(i) when rising_edge(CLK_TDC); + edge_falling_d_3r(i) <= edge_falling_d_2r(i) when rising_edge(CLK_TDC); hit_edge(i) <= '0' when edge_falling_d(i) = '1' or RESET = '1' else '1' when rising_edge(edge_rising(i)); @@ -353,7 +353,7 @@ begin '1' when rising_edge(hit_in_s(i)); edge_rising_r(i) <= edge_rising(i) when rising_edge(CLK_TDC); edge_rising_2r(i) <= edge_rising_r(i) when rising_edge(CLK_TDC); - edge_rising_3r(i) <= edge_rising_2r(i) when rising_edge(CLK_TDC); --edge_rising_r(i) and not edge_rising_2r(i) when rising_edge(CLK_TDC); + edge_rising_3r(i) <= edge_rising_2r(i) when rising_edge(CLK_TDC); hit_latch(i) <= edge_rising(i); hit_edge_2r(i) <= '1'; @@ -364,8 +364,8 @@ begin hit_mux_ch : hit_mux port map ( CH_EN_IN => ch_en(i), - CALIBRATION_EN_IN => '0', --calibration_on, - HIT_CALIBRATION_IN => '0', --hit_cal, + CALIBRATION_EN_IN => '0', + HIT_CALIBRATION_IN => '0', HIT_PHYSICAL_IN => hit_latch(i), HIT_OUT => hit_in_i(i)); end generate GEN_hit_mux; @@ -373,9 +373,9 @@ begin hit_mux_ref : hit_mux port map ( CH_EN_IN => '1', - CALIBRATION_EN_IN => '0', --calibration_on, - HIT_CALIBRATION_IN => '0', -- hit_cal, - HIT_PHYSICAL_IN => hit_in_s(0), --REFERENCE_TIME, + CALIBRATION_EN_IN => '0', + HIT_CALIBRATION_IN => '0', + HIT_PHYSICAL_IN => hit_in_s(0), HIT_OUT => hit_in_i(0)); CalibrationSwitch : process (CLK_READOUT) @@ -635,10 +635,6 @@ begin end process Hit_Detect_Counter; end generate GenHitCounter; - - - - ------------------------------------------------------------------------------- -- Slow Control Data Busses ------------------------------------------------------------------------------- @@ -709,10 +705,6 @@ begin status_registers_bus(17)(23 downto 0) <= readout_statistics(13); status_registers_bus(18)(23 downto 0) <= readout_statistics(14); - - - - -- Channel debug TheChannelDebugBus : entity work.BusHandler_record generic map ( @@ -722,7 +714,7 @@ begin CLK => CLK_READOUT, BUS_RX => buschdebug_rx, BUS_TX => buschdebug_tx, - DATA_IN => buschdebug_data_in, --ch_200_debug + DATA_IN => buschdebug_data_in, DATA_OUT => open); buschdebug_data_in(0) <= ch_200_debug(0);