From: Thomas Gessler Date: Thu, 8 Oct 2020 21:52:14 +0000 (+0200) Subject: hub_test: Fix and simplify ILA cores X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8d622e2998d74ed327507bd7c17d979c7ab88988;p=cri.git hub_test: Fix and simplify ILA cores --- diff --git a/hub_test/constrs/debug.xdc b/hub_test/constrs/debug.xdc index e835588..8752f0c 100644 --- a/hub_test/constrs/debug.xdc +++ b/hub_test/constrs/debug.xdc @@ -1,24 +1,10 @@ - - -set_property MARK_DEBUG true [get_nets reset] -set_property MARK_DEBUG true [get_nets reset_from_vio] -set_property MARK_DEBUG true [get_nets sysclk_locked] -set_property MARK_DEBUG true [get_nets trb_reset] -set_property MARK_DEBUG true [get_nets clear] -set_property MARK_DEBUG true [get_nets initial_clear_n] -set_property MARK_DEBUG true [get_nets send_reset_detect] -set_property MARK_DEBUG true [get_nets {med2int_i[9][stat_op][13]}] -set_property MARK_DEBUG true [get_nets {med2int_i[9][stat_op][15]}] - - - create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] -set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] -set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] -set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] -set_property C_INPUT_PIPE_STAGES 6 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] @@ -45,113 +31,103 @@ connect_debug_port u_ila_0/probe4 [get_nets [list {generate_parsers[0].trb_parse create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 1 [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {generate_parsers[0].trb_parser_i/M_AXIS_TVALID}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {generate_parsers[0].trb_parser_i/M_AXIS_TREADY}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 1 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {generate_parsers[0].trb_parser_i/M_AXIS_TVALID}]] create_debug_core u_ila_1 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1] -set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1] -set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1] set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1] -set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1] -set_property C_INPUT_PIPE_STAGES 6 [get_debug_cores u_ila_1] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1] set_property C_TRIGIN_EN false [get_debug_cores u_ila_1] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1] set_property port_width 1 [get_debug_ports u_ila_1/clk] -connect_debug_port u_ila_1/clk [get_nets [list THE_SYSCLK/inst/clk_out2]] +connect_debug_port u_ila_1/clk [get_nets [list mgtrefclk_uplink_bufg]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0] set_property port_width 8 [get_debug_ports u_ila_1/probe0] -connect_debug_port u_ila_1/probe0 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[0]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[1]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[2]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[3]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[4]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[5]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[6]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[7]}]] +connect_debug_port u_ila_1/probe0 [get_nets [list {THE_UPLINK/THE_SERDES/RXDATA[0]} {THE_UPLINK/THE_SERDES/RXDATA[1]} {THE_UPLINK/THE_SERDES/RXDATA[2]} {THE_UPLINK/THE_SERDES/RXDATA[3]} {THE_UPLINK/THE_SERDES/RXDATA[4]} {THE_UPLINK/THE_SERDES/RXDATA[5]} {THE_UPLINK/THE_SERDES/RXDATA[6]} {THE_UPLINK/THE_SERDES/RXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1] set_property port_width 8 [get_debug_ports u_ila_1/probe1] -connect_debug_port u_ila_1/probe1 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[0]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[1]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[2]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[3]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[4]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[5]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[6]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[7]}]] +connect_debug_port u_ila_1/probe1 [get_nets [list {THE_UPLINK/THE_SERDES/TXDATA[0]} {THE_UPLINK/THE_SERDES/TXDATA[1]} {THE_UPLINK/THE_SERDES/TXDATA[2]} {THE_UPLINK/THE_SERDES/TXDATA[3]} {THE_UPLINK/THE_SERDES/TXDATA[4]} {THE_UPLINK/THE_SERDES/TXDATA[5]} {THE_UPLINK/THE_SERDES/TXDATA[6]} {THE_UPLINK/THE_SERDES/TXDATA[7]}]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2] -set_property port_width 8 [get_debug_ports u_ila_1/probe2] -connect_debug_port u_ila_1/probe2 [get_nets [list {THE_UPLINK/THE_SERDES/RXDATA[0]} {THE_UPLINK/THE_SERDES/RXDATA[1]} {THE_UPLINK/THE_SERDES/RXDATA[2]} {THE_UPLINK/THE_SERDES/RXDATA[3]} {THE_UPLINK/THE_SERDES/RXDATA[4]} {THE_UPLINK/THE_SERDES/RXDATA[5]} {THE_UPLINK/THE_SERDES/RXDATA[6]} {THE_UPLINK/THE_SERDES/RXDATA[7]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe2] +connect_debug_port u_ila_1/probe2 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISCOMMA]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3] -set_property port_width 8 [get_debug_ports u_ila_1/probe3] -connect_debug_port u_ila_1/probe3 [get_nets [list {THE_UPLINK/THE_SERDES/TXDATA[0]} {THE_UPLINK/THE_SERDES/TXDATA[1]} {THE_UPLINK/THE_SERDES/TXDATA[2]} {THE_UPLINK/THE_SERDES/TXDATA[3]} {THE_UPLINK/THE_SERDES/TXDATA[4]} {THE_UPLINK/THE_SERDES/TXDATA[5]} {THE_UPLINK/THE_SERDES/TXDATA[6]} {THE_UPLINK/THE_SERDES/TXDATA[7]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe3] +connect_debug_port u_ila_1/probe3 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISK]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4] -set_property port_width 2 [get_debug_ports u_ila_1/probe4] -connect_debug_port u_ila_1/probe4 [get_nets [list {med2int_i[9][stat_op][13]} {med2int_i[9][stat_op][15]}]] +set_property port_width 1 [get_debug_ports u_ila_1/probe4] +connect_debug_port u_ila_1/probe4 [get_nets [list THE_UPLINK/THE_SERDES/RXDISPERR]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5] set_property port_width 1 [get_debug_ports u_ila_1/probe5] -connect_debug_port u_ila_1/probe5 [get_nets [list clear]] +connect_debug_port u_ila_1/probe5 [get_nets [list THE_UPLINK/THE_SERDES/RXNOTINTABLE]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6] set_property port_width 1 [get_debug_ports u_ila_1/probe6] -connect_debug_port u_ila_1/probe6 [get_nets [list initial_clear_n]] +connect_debug_port u_ila_1/probe6 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARDISPMODE]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7] set_property port_width 1 [get_debug_ports u_ila_1/probe7] -connect_debug_port u_ila_1/probe7 [get_nets [list reset]] +connect_debug_port u_ila_1/probe7 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARDISPVAL]] create_debug_port u_ila_1 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8] set_property port_width 1 [get_debug_ports u_ila_1/probe8] -connect_debug_port u_ila_1/probe8 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISCOMMA]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9] -set_property port_width 1 [get_debug_ports u_ila_1/probe9] -connect_debug_port u_ila_1/probe9 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXCHARISCOMMA}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10] -set_property port_width 1 [get_debug_ports u_ila_1/probe10] -connect_debug_port u_ila_1/probe10 [get_nets [list THE_UPLINK/THE_SERDES/RXCHARISK]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11] -set_property port_width 1 [get_debug_ports u_ila_1/probe11] -connect_debug_port u_ila_1/probe11 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXCHARISK}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12] -set_property port_width 1 [get_debug_ports u_ila_1/probe12] -connect_debug_port u_ila_1/probe12 [get_nets [list THE_UPLINK/THE_SERDES/RXDISPERR]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13] -set_property port_width 1 [get_debug_ports u_ila_1/probe13] -connect_debug_port u_ila_1/probe13 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDISPERR}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe14] -set_property port_width 1 [get_debug_ports u_ila_1/probe14] -connect_debug_port u_ila_1/probe14 [get_nets [list THE_UPLINK/THE_SERDES/RXNOTINTABLE]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe15] -set_property port_width 1 [get_debug_ports u_ila_1/probe15] -connect_debug_port u_ila_1/probe15 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXNOTINTABLE}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe16] -set_property port_width 1 [get_debug_ports u_ila_1/probe16] -connect_debug_port u_ila_1/probe16 [get_nets [list sysclk_locked]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe17] -set_property port_width 1 [get_debug_ports u_ila_1/probe17] -connect_debug_port u_ila_1/probe17 [get_nets [list trb_reset]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe18] -set_property port_width 1 [get_debug_ports u_ila_1/probe18] -connect_debug_port u_ila_1/probe18 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARDISPMODE]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe19] -set_property port_width 1 [get_debug_ports u_ila_1/probe19] -connect_debug_port u_ila_1/probe19 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARDISPMODE}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe20] -set_property port_width 1 [get_debug_ports u_ila_1/probe20] -connect_debug_port u_ila_1/probe20 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARDISPVAL}]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe21] -set_property port_width 1 [get_debug_ports u_ila_1/probe21] -connect_debug_port u_ila_1/probe21 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARDISPVAL]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe22] -set_property port_width 1 [get_debug_ports u_ila_1/probe22] -connect_debug_port u_ila_1/probe22 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARISK]] -create_debug_port u_ila_1 probe -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe23] -set_property port_width 1 [get_debug_ports u_ila_1/probe23] -connect_debug_port u_ila_1/probe23 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARISK}]] +connect_debug_port u_ila_1/probe8 [get_nets [list THE_UPLINK/THE_SERDES/TXCHARISK]] +create_debug_core u_ila_2 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_2] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2] +set_property port_width 1 [get_debug_ports u_ila_2/clk] +connect_debug_port u_ila_2/clk [get_nets [list THE_SYSCLK/inst/clk_out2]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0] +set_property port_width 8 [get_debug_ports u_ila_2/probe0] +connect_debug_port u_ila_2/probe0 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[0]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[1]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[2]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[3]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[4]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[5]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[6]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDATA[7]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1] +set_property port_width 8 [get_debug_ports u_ila_2/probe1] +connect_debug_port u_ila_2/probe1 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[0]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[1]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[2]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[3]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[4]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[5]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[6]} {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXDATA[7]}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2] +set_property port_width 1 [get_debug_ports u_ila_2/probe2] +connect_debug_port u_ila_2/probe2 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXCHARISCOMMA}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3] +set_property port_width 1 [get_debug_ports u_ila_2/probe3] +connect_debug_port u_ila_2/probe3 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXCHARISK}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4] +set_property port_width 1 [get_debug_ports u_ila_2/probe4] +connect_debug_port u_ila_2/probe4 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXDISPERR}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5] +set_property port_width 1 [get_debug_ports u_ila_2/probe5] +connect_debug_port u_ila_2/probe5 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/RXNOTINTABLE}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6] +set_property port_width 1 [get_debug_ports u_ila_2/probe6] +connect_debug_port u_ila_2/probe6 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARDISPMODE}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7] +set_property port_width 1 [get_debug_ports u_ila_2/probe7] +connect_debug_port u_ila_2/probe7 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARDISPVAL}]] +create_debug_port u_ila_2 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8] +set_property port_width 1 [get_debug_ports u_ila_2/probe8] +connect_debug_port u_ila_2/probe8 [get_nets [list {generate_downlinks[0].THE_DOWNLINK/THE_SERDES/TXCHARISK}]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]