From: Thomas Gessler Date: Thu, 25 Feb 2021 09:48:21 +0000 (+0100) Subject: Squashed 'hub_test/src/tx_phase_aligner/' content from commit e92a060 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8dd99c8843ba968c8b98a1de0dd3377a94603a9e;p=cri.git Squashed 'hub_test/src/tx_phase_aligner/' content from commit e92a060 git-subtree-dir: hub_test/src/tx_phase_aligner git-subtree-split: e92a060f338e99de064f09df812c65363268221b --- 8dd99c8843ba968c8b98a1de0dd3377a94603a9e diff --git a/.gitkeep b/.gitkeep new file mode 100644 index 0000000..e69de29 diff --git a/README.md b/README.md new file mode 100644 index 0000000..132498e --- /dev/null +++ b/README.md @@ -0,0 +1,3 @@ +Tx phase aligner core reference design + +It is recommended to read the reference note file: tx_phase_aligner_reference_note.pdf \ No newline at end of file diff --git a/license.txt b/license.txt new file mode 100644 index 0000000..e72bfdd --- /dev/null +++ b/license.txt @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. Therefore, you have +certain responsibilities if you distribute copies of the software, or if +you modify it: responsibilities to respect the freedom of others. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must pass on to the recipients the same +freedoms that you received. You must make sure that they, too, receive +or can get the source code. And you must show them these terms so they +know their rights. + + Developers that use the GNU GPL protect your rights with two steps: +(1) assert copyright on the software, and (2) offer you this License +giving you legal permission to copy, distribute and/or modify it. + + For the developers' and authors' protection, the GPL clearly explains +that there is no warranty for this free software. For both users' and +authors' sake, the GPL requires that modified versions be marked as +changed, so that their problems will not be attributed erroneously to +authors of previous versions. + + Some devices are designed to deny users access to install or run +modified versions of the software inside them, although the manufacturer +can do so. This is fundamentally incompatible with the aim of +protecting users' freedom to change the software. The systematic +pattern of such abuse occurs in the area of products for individuals to +use, which is precisely where it is most unacceptable. Therefore, we +have designed this version of the GPL to prohibit the practice for those +products. If such problems arise substantially in other domains, we +stand ready to extend this provision to those domains in future versions +of the GPL, as needed to protect the freedom of users. + + Finally, every program is threatened constantly by software patents. +States should not allow patents to restrict development and use of +software on general-purpose computers, but in those that do, we wish to +avoid the special danger that patents applied to a free program could +make it effectively proprietary. To prevent this, the GPL assures that +patents cannot be used to render the program non-free. + + The precise terms and conditions for copying, distribution and +modification follow. + + TERMS AND CONDITIONS + + 0. Definitions. + + "This License" refers to version 3 of the GNU General Public License. + + "Copyright" also means copyright-like laws that apply to other kinds of +works, such as semiconductor masks. + + "The Program" refers to any copyrightable work licensed under this +License. Each licensee is addressed as "you". "Licensees" and +"recipients" may be individuals or organizations. + + To "modify" a work means to copy from or adapt all or part of the work +in a fashion requiring copyright permission, other than the making of an +exact copy. The resulting work is called a "modified version" of the +earlier work or a work "based on" the earlier work. + + A "covered work" means either the unmodified Program or a work based +on the Program. + + To "propagate" a work means to do anything with it that, without +permission, would make you directly or secondarily liable for +infringement under applicable copyright law, except executing it on a +computer or modifying a private copy. Propagation includes copying, +distribution (with or without modification), making available to the +public, and in some countries other activities as well. + + To "convey" a work means any kind of propagation that enables other +parties to make or receive copies. Mere interaction with a user through +a computer network, with no transfer of a copy, is not conveying. + + An interactive user interface displays "Appropriate Legal Notices" +to the extent that it includes a convenient and prominently visible +feature that (1) displays an appropriate copyright notice, and (2) +tells the user that there is no warranty for the work (except to the +extent that warranties are provided), that licensees may convey the +work under this License, and how to view a copy of this License. If +the interface presents a list of user commands or options, such as a +menu, a prominent item in the list meets this criterion. + + 1. Source Code. + + The "source code" for a work means the preferred form of the work +for making modifications to it. "Object code" means any non-source +form of a work. + + A "Standard Interface" means an interface that either is an official +standard defined by a recognized standards body, or, in the case of +interfaces specified for a particular programming language, one that +is widely used among developers working in that language. + + The "System Libraries" of an executable work include anything, other +than the work as a whole, that (a) is included in the normal form of +packaging a Major Component, but which is not part of that Major +Component, and (b) serves only to enable use of the work with that +Major Component, or to implement a Standard Interface for which an +implementation is available to the public in source code form. A +"Major Component", in this context, means a major essential component +(kernel, window system, and so on) of the specific operating system +(if any) on which the executable work runs, or a compiler used to +produce the work, or an object code interpreter used to run it. + + The "Corresponding Source" for a work in object code form means all +the source code needed to generate, install, and (for an executable +work) run the object code and to modify the work, including scripts to +control those activities. However, it does not include the work's +System Libraries, or general-purpose tools or generally available free +programs which are used unmodified in performing those activities but +which are not part of the work. For example, Corresponding Source +includes interface definition files associated with source files for +the work, and the source code for shared libraries and dynamically +linked subprograms that the work is specifically designed to require, +such as by intimate data communication or control flow between those +subprograms and other parts of the work. + + The Corresponding Source need not include anything that users +can regenerate automatically from other parts of the Corresponding +Source. + + The Corresponding Source for a work in source code form is that +same work. + + 2. Basic Permissions. + + All rights granted under this License are granted for the term of +copyright on the Program, and are irrevocable provided the stated +conditions are met. This License explicitly affirms your unlimited +permission to run the unmodified Program. The output from running a +covered work is covered by this License only if the output, given its +content, constitutes a covered work. This License acknowledges your +rights of fair use or other equivalent, as provided by copyright law. + + You may make, run and propagate covered works that you do not +convey, without conditions so long as your license otherwise remains +in force. You may convey covered works to others for the sole purpose +of having them make modifications exclusively for you, or provide you +with facilities for running those works, provided that you comply with +the terms of this License in conveying all material for which you do +not control copyright. Those thus making or running the covered works +for you must do so exclusively on your behalf, under your direction +and control, on terms that prohibit them from making any copies of +your copyrighted material outside their relationship with you. + + Conveying under any other circumstances is permitted solely under +the conditions stated below. Sublicensing is not allowed; section 10 +makes it unnecessary. + + 3. Protecting Users' Legal Rights From Anti-Circumvention Law. + + No covered work shall be deemed part of an effective technological +measure under any applicable law fulfilling obligations under article +11 of the WIPO copyright treaty adopted on 20 December 1996, or +similar laws prohibiting or restricting circumvention of such +measures. + + When you convey a covered work, you waive any legal power to forbid +circumvention of technological measures to the extent such circumvention +is effected by exercising rights under this License with respect to +the covered work, and you disclaim any intention to limit operation or +modification of the work as a means of enforcing, against the work's +users, your or third parties' legal rights to forbid circumvention of +technological measures. + + 4. Conveying Verbatim Copies. + + You may convey verbatim copies of the Program's source code as you +receive it, in any medium, provided that you conspicuously and +appropriately publish on each copy an appropriate copyright notice; +keep intact all notices stating that this License and any +non-permissive terms added in accord with section 7 apply to the code; +keep intact all notices of the absence of any warranty; and give all +recipients a copy of this License along with the Program. + + You may charge any price or no price for each copy that you convey, +and you may offer support or warranty protection for a fee. + + 5. Conveying Modified Source Versions. + + You may convey a work based on the Program, or the modifications to +produce it from the Program, in the form of source code under the +terms of section 4, provided that you also meet all of these conditions: + + a) The work must carry prominent notices stating that you modified + it, and giving a relevant date. + + b) The work must carry prominent notices stating that it is + released under this License and any conditions added under section + 7. This requirement modifies the requirement in section 4 to + "keep intact all notices". + + c) You must license the entire work, as a whole, under this + License to anyone who comes into possession of a copy. This + License will therefore apply, along with any applicable section 7 + additional terms, to the whole of the work, and all its parts, + regardless of how they are packaged. This License gives no + permission to license the work in any other way, but it does not + invalidate such permission if you have separately received it. + + d) If the work has interactive user interfaces, each must display + Appropriate Legal Notices; however, if the Program has interactive + interfaces that do not display Appropriate Legal Notices, your + work need not make them do so. + + A compilation of a covered work with other separate and independent +works, which are not by their nature extensions of the covered work, +and which are not combined with it such as to form a larger program, +in or on a volume of a storage or distribution medium, is called an +"aggregate" if the compilation and its resulting copyright are not +used to limit the access or legal rights of the compilation's users +beyond what the individual works permit. Inclusion of a covered work +in an aggregate does not cause this License to apply to the other +parts of the aggregate. + + 6. Conveying Non-Source Forms. + + You may convey a covered work in object code form under the terms +of sections 4 and 5, provided that you also convey the +machine-readable Corresponding Source under the terms of this License, +in one of these ways: + + a) Convey the object code in, or embodied in, a physical product + (including a physical distribution medium), accompanied by the + Corresponding Source fixed on a durable physical medium + customarily used for software interchange. + + b) Convey the object code in, or embodied in, a physical product + (including a physical distribution medium), accompanied by a + written offer, valid for at least three years and valid for as + long as you offer spare parts or customer support for that product + model, to give anyone who possesses the object code either (1) a + copy of the Corresponding Source for all the software in the + product that is covered by this License, on a durable physical + medium customarily used for software interchange, for a price no + more than your reasonable cost of physically performing this + conveying of source, or (2) access to copy the + Corresponding Source from a network server at no charge. + + c) Convey individual copies of the object code with a copy of the + written offer to provide the Corresponding Source. This + alternative is allowed only occasionally and noncommercially, and + only if you received the object code with such an offer, in accord + with subsection 6b. + + d) Convey the object code by offering access from a designated + place (gratis or for a charge), and offer equivalent access to the + Corresponding Source in the same way through the same place at no + further charge. You need not require recipients to copy the + Corresponding Source along with the object code. If the place to + copy the object code is a network server, the Corresponding Source + may be on a different server (operated by you or a third party) + that supports equivalent copying facilities, provided you maintain + clear directions next to the object code saying where to find the + Corresponding Source. Regardless of what server hosts the + Corresponding Source, you remain obligated to ensure that it is + available for as long as needed to satisfy these requirements. + + e) Convey the object code using peer-to-peer transmission, provided + you inform other peers where the object code and Corresponding + Source of the work are being offered to the general public at no + charge under subsection 6d. + + A separable portion of the object code, whose source code is excluded +from the Corresponding Source as a System Library, need not be +included in conveying the object code work. + + A "User Product" is either (1) a "consumer product", which means any +tangible personal property which is normally used for personal, family, +or household purposes, or (2) anything designed or sold for incorporation +into a dwelling. In determining whether a product is a consumer product, +doubtful cases shall be resolved in favor of coverage. For a particular +product received by a particular user, "normally used" refers to a +typical or common use of that class of product, regardless of the status +of the particular user or of the way in which the particular user +actually uses, or expects or is expected to use, the product. A product +is a consumer product regardless of whether the product has substantial +commercial, industrial or non-consumer uses, unless such uses represent +the only significant mode of use of the product. + + "Installation Information" for a User Product means any methods, +procedures, authorization keys, or other information required to install +and execute modified versions of a covered work in that User Product from +a modified version of its Corresponding Source. The information must +suffice to ensure that the continued functioning of the modified object +code is in no case prevented or interfered with solely because +modification has been made. + + If you convey an object code work under this section in, or with, or +specifically for use in, a User Product, and the conveying occurs as +part of a transaction in which the right of possession and use of the +User Product is transferred to the recipient in perpetuity or for a +fixed term (regardless of how the transaction is characterized), the +Corresponding Source conveyed under this section must be accompanied +by the Installation Information. But this requirement does not apply +if neither you nor any third party retains the ability to install +modified object code on the User Product (for example, the work has +been installed in ROM). + + The requirement to provide Installation Information does not include a +requirement to continue to provide support service, warranty, or updates +for a work that has been modified or installed by the recipient, or for +the User Product in which it has been modified or installed. Access to a +network may be denied when the modification itself materially and +adversely affects the operation of the network or violates the rules and +protocols for communication across the network. + + Corresponding Source conveyed, and Installation Information provided, +in accord with this section must be in a format that is publicly +documented (and with an implementation available to the public in +source code form), and must require no special password or key for +unpacking, reading or copying. + + 7. Additional Terms. + + "Additional permissions" are terms that supplement the terms of this +License by making exceptions from one or more of its conditions. +Additional permissions that are applicable to the entire Program shall +be treated as though they were included in this License, to the extent +that they are valid under applicable law. If additional permissions +apply only to part of the Program, that part may be used separately +under those permissions, but the entire Program remains governed by +this License without regard to the additional permissions. + + When you convey a copy of a covered work, you may at your option +remove any additional permissions from that copy, or from any part of +it. (Additional permissions may be written to require their own +removal in certain cases when you modify the work.) You may place +additional permissions on material, added by you to a covered work, +for which you have or can give appropriate copyright permission. + + Notwithstanding any other provision of this License, for material you +add to a covered work, you may (if authorized by the copyright holders of +that material) supplement the terms of this License with terms: + + a) Disclaiming warranty or limiting liability differently from the + terms of sections 15 and 16 of this License; or + + b) Requiring preservation of specified reasonable legal notices or + author attributions in that material or in the Appropriate Legal + Notices displayed by works containing it; or + + c) Prohibiting misrepresentation of the origin of that material, or + requiring that modified versions of such material be marked in + reasonable ways as different from the original version; or + + d) Limiting the use for publicity purposes of names of licensors or + authors of the material; or + + e) Declining to grant rights under trademark law for use of some + trade names, trademarks, or service marks; or + + f) Requiring indemnification of licensors and authors of that + material by anyone who conveys the material (or modified versions of + it) with contractual assumptions of liability to the recipient, for + any liability that these contractual assumptions directly impose on + those licensors and authors. + + All other non-permissive additional terms are considered "further +restrictions" within the meaning of section 10. If the Program as you +received it, or any part of it, contains a notice stating that it is +governed by this License along with a term that is a further +restriction, you may remove that term. If a license document contains +a further restriction but permits relicensing or conveying under this +License, you may add to a covered work material governed by the terms +of that license document, provided that the further restriction does +not survive such relicensing or conveying. + + If you add terms to a covered work in accord with this section, you +must place, in the relevant source files, a statement of the +additional terms that apply to those files, or a notice indicating +where to find the applicable terms. + + Additional terms, permissive or non-permissive, may be stated in the +form of a separately written license, or stated as exceptions; +the above requirements apply either way. + + 8. Termination. + + You may not propagate or modify a covered work except as expressly +provided under this License. Any attempt otherwise to propagate or +modify it is void, and will automatically terminate your rights under +this License (including any patent licenses granted under the third +paragraph of section 11). + + However, if you cease all violation of this License, then your +license from a particular copyright holder is reinstated (a) +provisionally, unless and until the copyright holder explicitly and +finally terminates your license, and (b) permanently, if the copyright +holder fails to notify you of the violation by some reasonable means +prior to 60 days after the cessation. + + Moreover, your license from a particular copyright holder is +reinstated permanently if the copyright holder notifies you of the +violation by some reasonable means, this is the first time you have +received notice of violation of this License (for any work) from that +copyright holder, and you cure the violation prior to 30 days after +your receipt of the notice. + + Termination of your rights under this section does not terminate the +licenses of parties who have received copies or rights from you under +this License. If your rights have been terminated and not permanently +reinstated, you do not qualify to receive new licenses for the same +material under section 10. + + 9. Acceptance Not Required for Having Copies. + + You are not required to accept this License in order to receive or +run a copy of the Program. Ancillary propagation of a covered work +occurring solely as a consequence of using peer-to-peer transmission +to receive a copy likewise does not require acceptance. However, +nothing other than this License grants you permission to propagate or +modify any covered work. These actions infringe copyright if you do +not accept this License. Therefore, by modifying or propagating a +covered work, you indicate your acceptance of this License to do so. + + 10. Automatic Licensing of Downstream Recipients. + + Each time you convey a covered work, the recipient automatically +receives a license from the original licensors, to run, modify and +propagate that work, subject to this License. You are not responsible +for enforcing compliance by third parties with this License. + + An "entity transaction" is a transaction transferring control of an +organization, or substantially all assets of one, or subdividing an +organization, or merging organizations. If propagation of a covered +work results from an entity transaction, each party to that +transaction who receives a copy of the work also receives whatever +licenses to the work the party's predecessor in interest had or could +give under the previous paragraph, plus a right to possession of the +Corresponding Source of the work from the predecessor in interest, if +the predecessor has it or can get it with reasonable efforts. + + You may not impose any further restrictions on the exercise of the +rights granted or affirmed under this License. For example, you may +not impose a license fee, royalty, or other charge for exercise of +rights granted under this License, and you may not initiate litigation +(including a cross-claim or counterclaim in a lawsuit) alleging that +any patent claim is infringed by making, using, selling, offering for +sale, or importing the Program or any portion of it. + + 11. Patents. + + A "contributor" is a copyright holder who authorizes use under this +License of the Program or a work on which the Program is based. The +work thus licensed is called the contributor's "contributor version". + + A contributor's "essential patent claims" are all patent claims +owned or controlled by the contributor, whether already acquired or +hereafter acquired, that would be infringed by some manner, permitted +by this License, of making, using, or selling its contributor version, +but do not include claims that would be infringed only as a +consequence of further modification of the contributor version. For +purposes of this definition, "control" includes the right to grant +patent sublicenses in a manner consistent with the requirements of +this License. + + Each contributor grants you a non-exclusive, worldwide, royalty-free +patent license under the contributor's essential patent claims, to +make, use, sell, offer for sale, import and otherwise run, modify and +propagate the contents of its contributor version. + + In the following three paragraphs, a "patent license" is any express +agreement or commitment, however denominated, not to enforce a patent +(such as an express permission to practice a patent or covenant not to +sue for patent infringement). To "grant" such a patent license to a +party means to make such an agreement or commitment not to enforce a +patent against the party. + + If you convey a covered work, knowingly relying on a patent license, +and the Corresponding Source of the work is not available for anyone +to copy, free of charge and under the terms of this License, through a +publicly available network server or other readily accessible means, +then you must either (1) cause the Corresponding Source to be so +available, or (2) arrange to deprive yourself of the benefit of the +patent license for this particular work, or (3) arrange, in a manner +consistent with the requirements of this License, to extend the patent +license to downstream recipients. "Knowingly relying" means you have +actual knowledge that, but for the patent license, your conveying the +covered work in a country, or your recipient's use of the covered work +in a country, would infringe one or more identifiable patents in that +country that you have reason to believe are valid. + + If, pursuant to or in connection with a single transaction or +arrangement, you convey, or propagate by procuring conveyance of, a +covered work, and grant a patent license to some of the parties +receiving the covered work authorizing them to use, propagate, modify +or convey a specific copy of the covered work, then the patent license +you grant is automatically extended to all recipients of the covered +work and works based on it. + + A patent license is "discriminatory" if it does not include within +the scope of its coverage, prohibits the exercise of, or is +conditioned on the non-exercise of one or more of the rights that are +specifically granted under this License. You may not convey a covered +work if you are a party to an arrangement with a third party that is +in the business of distributing software, under which you make payment +to the third party based on the extent of your activity of conveying +the work, and under which the third party grants, to any of the +parties who would receive the covered work from you, a discriminatory +patent license (a) in connection with copies of the covered work +conveyed by you (or copies made from those copies), or (b) primarily +for and in connection with specific products or compilations that +contain the covered work, unless you entered into that arrangement, +or that patent license was granted, prior to 28 March 2007. + + Nothing in this License shall be construed as excluding or limiting +any implied license or other defenses to infringement that may +otherwise be available to you under applicable patent law. + + 12. No Surrender of Others' Freedom. + + If conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot convey a +covered work so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you may +not convey it at all. For example, if you agree to terms that obligate you +to collect a royalty for further conveying from those to whom you convey +the Program, the only way you could satisfy both those terms and this +License would be to refrain entirely from conveying the Program. + + 13. Use with the GNU Affero General Public License. + + Notwithstanding any other provision of this License, you have +permission to link or combine any covered work with a work licensed +under version 3 of the GNU Affero General Public License into a single +combined work, and to convey the resulting work. The terms of this +License will continue to apply to the part which is the covered work, +but the special requirements of the GNU Affero General Public License, +section 13, concerning interaction through a network will apply to the +combination as such. + + 14. Revised Versions of this License. + + The Free Software Foundation may publish revised and/or new versions of +the GNU General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + + Each version is given a distinguishing version number. If the +Program specifies that a certain numbered version of the GNU General +Public License "or any later version" applies to it, you have the +option of following the terms and conditions either of that numbered +version or of any later version published by the Free Software +Foundation. If the Program does not specify a version number of the +GNU General Public License, you may choose any version ever published +by the Free Software Foundation. + + If the Program specifies that a proxy can decide which future +versions of the GNU General Public License can be used, that proxy's +public statement of acceptance of a version permanently authorizes you +to choose that version for the Program. + + Later license versions may give you additional or different +permissions. However, no additional obligations are imposed on any +author or copyright holder as a result of your choosing to follow a +later version. + + 15. Disclaimer of Warranty. + + THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY +APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT +HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY +OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM +IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF +ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + + 16. Limitation of Liability. + + IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS +THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY +GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE +USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF +DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD +PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), +EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF +SUCH DAMAGES. + + 17. Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. \ No newline at end of file diff --git a/run_script_tcl.bat b/run_script_tcl.bat new file mode 100644 index 0000000..3091023 --- /dev/null +++ b/run_script_tcl.bat @@ -0,0 +1,12 @@ +REM ################################################################################ +REM # Vivado 2019.1 batch file to create the HPTD Tx phase aligner +REM # This batch file uses the default Xilinx installation path. +REM ################################################################################ + +REM #call C:\EDA\Xilinx\v2016_2\Vivado\2016.2\bin\vivado.bat -mode gui -source tx_aligner_proj.tcl +call C:\EDA\Xilinx\\Vivado\\2019.1\\.\\bin\\vivado.bat -mode gui -source tx_aligner_proj.tcl + +del *.jou +del *.log + +REM pause \ No newline at end of file diff --git a/scripts/sim/tx_phase_aligner_simu.tcl b/scripts/sim/tx_phase_aligner_simu.tcl new file mode 100644 index 0000000..b9ab671 --- /dev/null +++ b/scripts/sim/tx_phase_aligner_simu.tcl @@ -0,0 +1,69 @@ +restart + +# Close if any window is opened +#close_wave_config + +# Init simulation with waves to be observed +#open_wave_config {./../tx_phase_aligner_simu.wcfg} + +# Force Initial VIO values for simulation +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/hb_gtwiz_reset_all_vio_int 0 0; # VIO_0 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/hb0_gtwiz_reset_tx_pll_and_datapath_int 0 0; # VIO_1 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/hb0_gtwiz_reset_tx_datapath_int 0 0; # VIO_2 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/hb_gtwiz_reset_rx_pll_and_datapath_vio_int 0 0; # VIO_3 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/hb_gtwiz_reset_rx_datapath_vio_int 0 0; # VIO_4 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/link_down_latched_reset_vio_int 0 0; # VIO_5 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/rxcdrreset_int 0 0; # VIO_6 +add_force -radix bin gtwizard_ultrascale_0_example_top_sim/example_top_inst/loopback_int 000 0; # VIO_7 +add_force -radix bin gtwizard_ultrascale_0_example_top_sim/example_top_inst/txprbssel_vio_async 0000 0; # VIO_8 +add_force -radix bin gtwizard_ultrascale_0_example_top_sim/example_top_inst/rxprbssel_vio_async 0000 0; # VIO_9 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/txprbsforceerr_vio_async 0 0; # VIO_10 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/rxprbscntreset_vio_async 0 0; # VIO_11 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_ui_align_calib 0 0; # VIO_12 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_fine_realign 0 0; # VIO_13 +add_force -radix bin gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_pi_phase_calib 0000000 0; # VIO_14 +add_force -radix hex gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_fifo_fill_pd_max 00000400 0 ; # VIO_15 +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_data_sel_vio_async 0 0; # VIO_16 + +# --------------------------------- Fine alignment --------------------------------- +puts "==> Running iteration 0 (fine alignment)" + +# Wait for Tx to be aligned +run 1000 ns +set tx_aligned [get_value -radix bin /gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_phase_aligner_inst/tx_aligned_o] +while {!$tx_aligned} { + run 1000 ns + set tx_aligned [get_value -radix bin /gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_phase_aligner_inst/tx_aligned_o] +} +puts ">> Tx aligned (fine alignment)" + +# Wait for some time +run 10000 ns + +# Get Tx PI phase in case and run a UI align +set tx_pi_phase_calib [get_value -radix bin /gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_phase_aligner_inst/tx_pi_phase_o] + +# Run a bit longer just to make it easier to identify simulation +run 10000 ns + +# ---------------------- UI alignment config (with enabled reset) ---------------------- +add_force gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_ui_align_calib 1 0; # VIO_12 +add_force -radix bin gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_pi_phase_calib $tx_pi_phase_calib 0; # VIO_14 + +# Force a reset +add_force hb_gtwiz_reset_all 1 0 +run 1000 ns +add_force hb_gtwiz_reset_all 0 0 +run 1000 ns + +# Wait for Tx to be aligned +run 1000 ns +set tx_aligned [get_value -radix bin /gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_phase_aligner_inst/tx_aligned_o] +while {!$tx_aligned} { + run 1000 ns + set tx_aligned [get_value -radix bin /gtwizard_ultrascale_0_example_top_sim/example_top_inst/tx_phase_aligner_inst/tx_aligned_o] +} +puts ">> Tx aligned (UI alignment)" + +# Run a bit longer just to make it easier to identify simulation +run 10000 ns diff --git a/scripts/sim/tx_phase_aligner_simu.wcfg b/scripts/sim/tx_phase_aligner_simu.wcfg new file mode 100644 index 0000000..807a3ea --- /dev/null +++ b/scripts/sim/tx_phase_aligner_simu.wcfg @@ -0,0 +1,189 @@ + + + + + + + + + + + + + + + + + + + + ch0_gthxn + ch0_gthxn + + + ch0_gthxp + ch0_gthxp + + + mgtrefclk1_x0y2 + mgtrefclk1_x0y2 + + + mgtrefclk0_x0y3 + mgtrefclk0_x0y3 + + + hb_gtwiz_reset_clk_freerun + hb_gtwiz_reset_clk_freerun + + + hb_gtwiz_reset_all + hb_gtwiz_reset_all + #A0A0A4 + true + + + link_down_latched_reset + link_down_latched_reset + + + link_status + link_status + + + link_down_latched + link_down_latched + + + simulation_timeout_check + simulation_timeout_check + + + link_up_ctr[10:0] + link_up_ctr[10:0] + + + link_stable + link_stable + + + gtwiz_userclk_rx_usrclk2_int + gtwiz_userclk_rx_usrclk2_int + + + clk_sys_i + clk_sys_i + + + reset_i + reset_i + + + rx_locked_out + rx_locked_out + + + tx_aligned_o + tx_aligned_o + #FF00FF + true + + + tx_pi_phase_calib_i[6:0] + tx_pi_phase_calib_i[6:0] + #00FFFF + true + + + tx_ui_align_calib_i + tx_ui_align_calib_i + #00FFFF + true + + + tx_enable_reset_i + tx_enable_reset_i + #00FFFF + true + + + tx_fifo_fill_pd_max_i[31:0] + tx_fifo_fill_pd_max_i[31:0] + #00FFFF + true + + + tx_fine_realign_i + tx_fine_realign_i + #00FFFF + true + + + tx_pi_phase_o[6:0] + tx_pi_phase_o[6:0] + #FAAFBE + true + + + tx_fifo_fill_pd_o[31:0] + tx_fifo_fill_pd_o[31:0] + #FAAFBE + true + + + clk_txusr_i + clk_txusr_i + + + tx_fifo_fill_level_i + tx_fifo_fill_level_i + + + txpippmen_o + txpippmen_o + + + txpippmovrden_o + txpippmovrden_o + + + txpippmsel_o + txpippmsel_o + + + txpippmpd_o + txpippmpd_o + + + txpippmstepsize_o[4:0] + txpippmstepsize_o[4:0] + + + drpaddr_o[8:0] + drpaddr_o[8:0] + + + drpen_o + drpen_o + + + drpdi_o[15:0] + drpdi_o[15:0] + + + drprdy_i + drprdy_i + + + drpdo_i[15:0] + drpdo_i[15:0] + + + drpwe_o + drpwe_o + + + tx_reset_o + tx_reset_o + + diff --git a/source/constrs/imports/example_design/gtwizard_ultrascale_0_example_top.xdc b/source/constrs/imports/example_design/gtwizard_ultrascale_0_example_top.xdc new file mode 100644 index 0000000..49022dc --- /dev/null +++ b/source/constrs/imports/example_design/gtwizard_ultrascale_0_example_top.xdc @@ -0,0 +1,153 @@ +#------------------------------------------------------------------------------ +# (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#------------------------------------------------------------------------------ + + +# UltraScale FPGAs Transceivers Wizard IP example design-level XDC file +# ---------------------------------------------------------------------------------------------------------------------- + +# ---------------------------------------------------------------------------------------------------------------------- +# ************************************************ PHYSICAL CONSTRAINTS ************************************************ +# ---------------------------------------------------------------------------------------------------------------------- +# Location constraints for differential reference clock buffers +# Note: the IP core-level XDC constrains the transceiver channel data pin locations +# ---------------------------------------------------------------------------------------------------------------------- +# MGT_SI570_CLOCK - on-board oscillator used for Rx reference clock +# Tipically, Tx and Rx share the same reference clock, in this design two +# separate clocks are used for a full proof-of-concept but this shall not be +# seen as a requirement/recommendation +set_property package_pin P5 [get_ports mgtrefclk0_x0y3_n] +set_property package_pin P6 [get_ports mgtrefclk0_x0y3_p] + +#FMC_LPC_GBTCLK0 - connect an FMC and an external generator for Tx reference clock +# example of FMC which can be used: TTC-PON FMC +set_property package_pin T5 [get_ports mgtrefclk1_x0y2_n] +set_property package_pin T6 [get_ports mgtrefclk1_x0y2_p] + +# Location and default clock constraints for differential recovered clock output buffers - direct from transceiver +# ---------------------------------------------------------------------------------------------------------------------- +# SMA_MGT_REF_CLK - ac-coupled on-board +set_property package_pin V6 [get_ports rxrecclkout_chx0y11_p] +set_property package_pin V5 [get_ports rxrecclkout_chx0y11_n] + +# Location and default clock constraints for recovered clock output buffers - going through fabric +# ---------------------------------------------------------------------------------------------------------------------- +set_property package_pin h27 [get_ports rxusrclk] +set_property iostandard lvcmos18 [get_ports rxusrclk] +set_property slew fast [get_ports rxusrclk] + +# Location constraints for other example design top-level ports +# Note: uncomment the following set_property constraints and replace "<>" with appropriate pin locations for your board +# ---------------------------------------------------------------------------------------------------------------------- +set_property package_pin G10 [get_ports hb_gtwiz_reset_clk_freerun_in_p] +set_property iostandard LVDS [get_ports hb_gtwiz_reset_clk_freerun_in_p] +set_property package_pin F10 [get_ports hb_gtwiz_reset_clk_freerun_in_n] +set_property iostandard LVDS [get_ports hb_gtwiz_reset_clk_freerun_in_n] + +#GPIO_SW_C +set_property package_pin AE10 [get_ports hb_gtwiz_reset_all_in] +set_property iostandard LVCMOS18 [get_ports hb_gtwiz_reset_all_in] + +#GPIO_SW_E +set_property package_pin AE8 [get_ports link_down_latched_reset_in] +set_property iostandard LVCMOS18 [get_ports link_down_latched_reset_in] + +#GPIO_LED_0 +set_property package_pin AP8 [get_ports link_status_out] +set_property iostandard LVCMOS18 [get_ports link_status_out] + +#GPIO_LED_1 +set_property package_pin H23 [get_ports link_down_latched_out] +set_property iostandard LVCMOS18 [get_ports link_down_latched_out] + +#GPIO_LED_2 +set_property package_pin P20 [get_ports rx_locked_out] +set_property iostandard LVCMOS18 [get_ports rx_locked_out] + +#GPIO_LED_3 +set_property package_pin P21 [get_ports tx_aligned_out] +set_property iostandard LVCMOS18 [get_ports tx_aligned_out] + +# ---------------------------------------------------------------------------------------------------------------------- +# MGT constraining of RXSLIDE to shift clock instead of data +# ---------------------------------------------------------------------------------------------------------------------- +set_property RXSLIDE_MODE PMA [get_cells -hier -filter {NAME=~*GTHE3_CHANNEL_PRIM_INST}] + +# ---------------------------------------------------------------------------------------------------------------------- +# ************************************************* TIMING CONSTRAINTS ************************************************* +# ---------------------------------------------------------------------------------------------------------------------- +# ---------------------------------------------------------------------------------------------------------------------- +# Clock constraints for clocks provided as inputs to the core +# Note: the IP core-level XDC constrains clocks produced by the core, which drive user clocks via helper blocks +# ---------------------------------------------------------------------------------------------------------------------- +create_clock -name clk_freerun -period 8.0 [get_ports hb_gtwiz_reset_clk_freerun_in_p] +create_clock -name clk_mgtrefclk0_x0y3_p -period 3.125 [get_ports mgtrefclk0_x0y3_p] +create_clock -name clk_mgtrefclk1_x0y2_p -period 3.125 [get_ports mgtrefclk1_x0y2_p] + +# Constrain the input to the OBUFDS_GTE3 primitive(s) at the maximum frequency that can be generated by the programmable +# divider for the receiver line rate. This can be changed to the exact frequency if the divider will not be modified. +create_clock -name clk_rxrecclk_chX0Y11 -period 0.39 [get_pins -filter {NAME =~ OBUFDS_GTE3_CHX0Y11_INST/I}] + +# False path constraints +# ---------------------------------------------------------------------------------------------------------------------- +# Synchronizers from example design +set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}] +set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}] + +# Synchronizers internal to rx_word_aligner +set_false_path -to [get_pins -hier -filter {NAME =~ *rx_word_aligner_inst/*meta*/D}] + +# Synchronizers internal to tx_phase_aligner +set_false_path -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_inst/*meta*/D}] + +# Latched with a done signal +set_false_path -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_inst/cmp_fifo_fill_level_acc/phase_detector_o*/D}] + +# Reset fifo fill pd after changing value of phase_detector_max from FSM +set_false_path -from [get_pins -hier -filter {NAME =~ tx_phase_aligner_inst/cmp_tx_phase_aligner_fsm/*/C}] -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_inst/cmp_fifo_fill_level_acc/phase_detector_acc_reg*/CE}] +set_false_path -from [get_pins -hier -filter {NAME =~ tx_phase_aligner_inst/cmp_tx_phase_aligner_fsm/*/C}] -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_inst/cmp_fifo_fill_level_acc/hits_acc_reg*/CE}] +set_false_path -from [get_pins -hier -filter {NAME =~ tx_phase_aligner_inst/cmp_tx_phase_aligner_fsm/*/C}] -to [get_pins -hier -filter {NAME =~ *tx_phase_aligner_inst/cmp_fifo_fill_level_acc/done_reg/D}] diff --git a/source/sim/imports/example_design/gtwizard_ultrascale_0_example_top_sim.v b/source/sim/imports/example_design/gtwizard_ultrascale_0_example_top_sim.v new file mode 100644 index 0000000..f321856 --- /dev/null +++ b/source/sim/imports/example_design/gtwizard_ultrascale_0_example_top_sim.v @@ -0,0 +1,226 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design top simulation module instantiates the example design top module, provides basic stimulus to it +// while looping back transceiver data from transmit to receive, and utilizes the PRBS checker-based link status +// indicator to demonstrate simple data integrity checking of the design. This module is for use in simulation only. +// ===================================================================================================================== + +module gtwizard_ultrascale_0_example_top_sim (); + + + // ------------------------------------------------------------------------------------------------------------------- + // Signal declarations and basic example design stimulus + // ------------------------------------------------------------------------------------------------------------------- + + // Declare wires to loop back serial data ports for transceiver channel 0 + wire ch0_gthxn; + wire ch0_gthxp; + + // Declare register to drive reference clock at location MGTREFCLK1_X0Y2 + reg mgtrefclk1_x0y2 = 1'b0; + + // Drive that reference clock at the appropriate frequency + // NOTE: the following simulation reference clock period may be up to +/- 2ps from its nominal value, due to rounding + // within Verilog timescale granularity, especially when transmitter and receiver reference clock frequencies differ + initial begin + mgtrefclk1_x0y2 = 1'b0; + forever + //mgtrefclk1_x0y2 = #1563 ~mgtrefclk1_x0y2; + mgtrefclk1_x0y2 = #1500 ~mgtrefclk1_x0y2; + end + + // Declare register to drive reference clock at location MGTREFCLK0_X0Y3 + reg mgtrefclk0_x0y3 = 1'b0; + + // Drive that reference clock at the appropriate frequency + // NOTE: the following simulation reference clock period may be up to +/- 2ps from its nominal value, due to rounding + // within Verilog timescale granularity, especially when transmitter and receiver reference clock frequencies differ + initial begin + mgtrefclk0_x0y3 = 1'b0; + forever + //mgtrefclk0_x0y3 = #1563 ~mgtrefclk0_x0y3; + mgtrefclk0_x0y3 = #1500 ~mgtrefclk0_x0y3; + end + + // Declare registers to drive reset helper block(s) + reg hb_gtwiz_reset_clk_freerun = 1'b0; + reg hb_gtwiz_reset_all = 1'b1; + + // Drive the helper block free running clock + initial begin + hb_gtwiz_reset_clk_freerun = 1'b0; + forever + hb_gtwiz_reset_clk_freerun = #4000 ~hb_gtwiz_reset_clk_freerun; + end + + // Drive the helper block "reset all" input high, then low after some time + initial begin + hb_gtwiz_reset_all = 1'b1; + #5E6; + repeat (100) + @(hb_gtwiz_reset_clk_freerun); + hb_gtwiz_reset_all = 1'b0; + end + + // Declare registers and wires to interface to the PRBS-based link status ports + reg link_down_latched_reset = 1'b0; + wire link_status; + wire link_down_latched; + + // ------------------------------------------------------------------------------------------------------------------- + // Basic data integrity checking, making use of PRBS-based link status ports + // ------------------------------------------------------------------------------------------------------------------- + + // Create a basic timeout indicator which is used to abort the simulation of no link is achieved after 2ms + reg simulation_timeout_check = 1'b0; + initial begin + simulation_timeout_check = 1'b0; + #2E9; + simulation_timeout_check = 1'b1; + end + + // Create a basic stable link monitor which is set after 2048 consecutive cycles of link up and is reset after any + // link loss + reg [10:0] link_up_ctr = 11'd0; + reg link_stable = 1'b0; + always @(posedge hb_gtwiz_reset_clk_freerun) begin + if (link_status !== 1'b1) begin + link_up_ctr <= 11'd0; + link_stable <= 1'b0; + end + else begin + if (&link_up_ctr) + link_stable <= 1'b1; + else + link_up_ctr <= link_up_ctr + 11'd1; + end + end + +// Commented by EBSM - the simulation is driven in TCL +// Checking is done in the TCL script accompanying the simulation +// // Perform basic checking of the simulation outcome based on stable link monitor +// initial begin + +// // Await de-assertion of the master reset signal +// @(negedge hb_gtwiz_reset_all); + +// // Await assertion of initial link indication or simulation timeout indicator +// @(posedge link_stable, simulation_timeout_check); + +// // If the simulation timeout indicator was asserted, the simulation failed to achieve initial link up in a +// // reasonable time, so display an error message and quit +// if (simulation_timeout_check) begin +// $display("Time : %12d ps FAIL: simulation timeout. Link never achieved.", $time); +// $display("** Error: Test did not complete successfully"); +// $finish; +// end + +// // If the initial link was achieved, display this message and continue checks as follows +// else begin +// $display("Time : %12d ps Initial link achieved across all transceiver channels.", $time); + +// // Reset the latched link down indicator, which is always set prior to initially achieving link +// $display("Time : %12d ps Resetting latched link down indicator.", $time); +// link_down_latched_reset = 1'b1; +// repeat (5) +// @(hb_gtwiz_reset_clk_freerun); +// link_down_latched_reset = 1'b0; + +// // Continue to run the simulation for long enough to detect any subsequent errors causing link loss which may +// // occur within a reasonable simulation time +// $display("Time : %12d ps Continuing simulation for 50us to check for maintenance of link.", $time); +// #5E7; + +// // At simulation completion, if the link indicator is still high and no intermittent link loss was detected, +// // display a success message. Otherwise, display a failure message. Complete the simulation in either case. +// if ((link_status === 1'b1) && (link_down_latched === 1'b0)) begin +// $display("Time : %12d ps PASS: simulation completed with maintained link.", $time); +// $display("** Test completed successfully"); +// end +// else begin +// $display("Time : %12d ps FAIL: simulation completed with subsequent link loss after after initial link.", $time); +// $display("** Error: Test did not complete successfully"); +// end + +// $finish; +// end +// end + + // ------------------------------------------------------------------------------------------------------------------- + // Instantiate example design top module as the simulation DUT + // ------------------------------------------------------------------------------------------------------------------- + + gtwizard_ultrascale_0_example_top example_top_inst ( + .mgtrefclk0_x0y3_p (mgtrefclk0_x0y3), + .mgtrefclk0_x0y3_n (~mgtrefclk0_x0y3), + .mgtrefclk1_x0y2_p (mgtrefclk1_x0y2), + .mgtrefclk1_x0y2_n (~mgtrefclk1_x0y2), + .ch0_gthrxn_in (ch0_gthxn), + .ch0_gthrxp_in (ch0_gthxp), + .ch0_gthtxn_out (ch0_gthxn), + .ch0_gthtxp_out (ch0_gthxp), + .rxrecclkout_chx0y11_p (), + .rxrecclkout_chx0y11_n (), + .rxusrclk (), // Added by EBSM + .hb_gtwiz_reset_clk_freerun_in_p (hb_gtwiz_reset_clk_freerun), + .hb_gtwiz_reset_clk_freerun_in_n (~hb_gtwiz_reset_clk_freerun), + .hb_gtwiz_reset_all_in (hb_gtwiz_reset_all), + .link_down_latched_reset_in (link_down_latched_reset), + .link_status_out (link_status), + .link_down_latched_out (link_down_latched), + .rx_locked_out(), // Added by EBSM + .tx_aligned_out() // Added by EBSM + ); + + +endmodule diff --git a/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd b/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd new file mode 100644 index 0000000..3b197d9 --- /dev/null +++ b/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd @@ -0,0 +1,240 @@ +--============================================================================== +-- © Copyright CERN for the benefit of the HPTD interest group 2018. All rights not +-- expressly granted are reserved. +-- +-- This file is part of tx_phase_aligner. +-- +-- tx_phase_aligner is free VHDL code: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- tx_phase_aligner is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with tx_phase_aligner. If not, see . +--============================================================================== +--! @file fifo_fill_level_acc.vhd +--============================================================================== +--! Standard library +library ieee; +--! Standard packages +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--! Specific packages +------------------------------------------------------------------------------- +-- -- +-- CERN, EP-ESE-BE, HPTD +-- -- +------------------------------------------------------------------------------- +-- +-- unit name: Transmitter FIFO filling level phase detector (fifo_fill_level_acc) +-- +--! @brief Transmitter FIFO filling level phase detector based on the address difference of read and write pointers +--! This block accumulates the FIFO filling level flag in order to obtain a high precision phase detector +--! +--! @author Eduardo Brandao de Souza Mendes - eduardo.brandao.de.souza.mendes@cern.ch +--! @date 02\05\2018 +--! @version 1.0 +--! @details +--! +--! Dependencies:\n +--! +--! +--! References:\n +--! \n +--! +--! +--! Modified by:\n +--! Author: Eduardo Brandao de Souza Mendes +------------------------------------------------------------------------------- +--! \n\nLast changes:\n +--! 02\05\2018 - EBSM - Created\n +--! +------------------------------------------------------------------------------- +--! @todo - \n +--! \n +-- +------------------------------------------------------------------------------- + +--============================================================================== +--! Entity declaration for fifo_fill_level_acc +--============================================================================== +entity fifo_fill_level_acc is + port ( + -- User Interface + clk_sys_i : in std_logic; --! system clock input + reset_i : in std_logic; --! actived on rising edge sync. reset + done_o : out std_logic; --! latched to '1' to indicate accumulated value was reached, cleared only with clear/reset + phase_detector_o : out std_logic_vector(31 downto 0); --! phase detector accumulated output (increments for each pulse in which txfifofilllevel is 1) + phase_detector_max_i : in std_logic_vector(31 downto 0); --! phase detector accumulated max output, sets precision of phase detector + --! this is supposedly a static signal, this block shall be reset whenever this signal changes + --! the time for each phase detection after a clear is given by phase_detector_max_i * PERIOD_clk_txusr_i + -- MGT interface + -- Tx fifo fill level - see Xilinx transceiver User Guide for more information + clk_txusr_i : in std_logic; --! txusr2clk + tx_fifo_fill_level_i : in std_logic --! connect to txbufstatus[0] + ); +end fifo_fill_level_acc; + +--============================================================================== +-- architecture declaration +--============================================================================== + +architecture rtl of fifo_fill_level_acc is + + --! Attribute declaration + attribute async_reg : string; + + --! Constant declaration + + --! Signal declaration + -- clear synchronizer to txusr clk using closed loop technique with synchronizer + -- reset synchronizer using simple 2-FF + -- clk_sys + signal reset_r : std_logic; + signal reset_toggle : std_logic := '0'; + + -- clk_txusr + signal reset_toggle_txusr_meta : std_logic; + signal reset_toggle_txusr_r : std_logic; + signal reset_toggle_txusr_r2 : std_logic; + attribute async_reg of reset_toggle_txusr_meta, reset_toggle_txusr_r, reset_toggle_txusr_r2 : signal is "true"; + signal reset_txusr : std_logic; + + -- phase detector + signal phase_detector_acc : unsigned(phase_detector_o'range); + signal hits_acc : unsigned(phase_detector_max_i'range); + signal done : std_logic; + + -- sync for done + signal done_sys_meta : std_logic; + signal done_sys_r : std_logic; + signal done_sys_r2 : std_logic; + attribute async_reg of done_sys_meta, done_sys_r, done_sys_r2 : signal is "true"; + + +begin + + --============================================================================ + -- Process p_reset_toggle + --! Creates a toggle for the reset when rising edge is detected + --! read: reset_i\n + --! write: \n + --! r/w: reset_toggle\n + --============================================================================ + p_reset_toggle : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + reset_r <= reset_i; + if(reset_r = '0' and reset_i = '1') then + reset_toggle <= not reset_toggle; + end if; + end if; + end process p_reset_toggle; + + --============================================================================ + -- Process p_reset_toggle_txusrsync + --! Creates a toggle for the reset when rising edge is detected + --! read: reset_toggle\n + --! write: reset_txusr\n + --! r/w: reset_toggle_txusr_meta, reset_toggle_txusr_r, reset_toggle_txusr_r2\n + --============================================================================ + p_reset_toggle_txusrsync : process(clk_txusr_i) + begin + if(rising_edge(clk_txusr_i)) then + reset_toggle_txusr_meta <= reset_toggle; + reset_toggle_txusr_r <= reset_toggle_txusr_meta; + reset_toggle_txusr_r2 <= reset_toggle_txusr_r; + reset_txusr <= reset_toggle_txusr_r2 xor reset_toggle_txusr_r; + end if; + end process p_reset_toggle_txusrsync; + + --============================================================================ + -- Process p_phase_detector + --! Creates reset toggle register with rising edge of reset + --! read: reset_txusr\n + --! write: done\n + --! r/w: hits_acc, phase_detector_acc\n + --============================================================================ + p_phase_detector : process(clk_txusr_i) + begin + if(rising_edge(clk_txusr_i)) then + if (reset_txusr = '1') then + phase_detector_acc <= to_unsigned(0, phase_detector_acc'length); + hits_acc <= to_unsigned(0, hits_acc'length); + done <= '0'; + else + if(hits_acc < unsigned(phase_detector_max_i)) then + hits_acc <= hits_acc + to_unsigned(1, hits_acc'length); + if(tx_fifo_fill_level_i = '1') then + phase_detector_acc <= phase_detector_acc + to_unsigned(1, phase_detector_acc'length); + end if; + done <= '0'; + else + done <= '1'; + end if; + end if; + end if; + end process p_phase_detector; + + --============================================================================ + -- Process p_sys_sync + --! System clock output synchronizer + --! read: done\n + --! write: done_sys_r2\n + --! r/w: done_sys_meta, done_sys_r\n + --============================================================================ + p_sys_sync : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + done_sys_meta <= done; + done_sys_r <= done_sys_meta; + done_sys_r2 <= done_sys_r; + end if; + end process p_sys_sync; + + --============================================================================ + -- Process p_done_out + --! Output of done bit + --! read: done_sys_r2, done_sys_r\n + --! write: done_o\n + --! r/w: -\n + --============================================================================ + p_done_out : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(reset_i = '1') then + done_o <= '0'; + else + if(done_sys_r2 = '0' and done_sys_r = '1') then + done_o <= '1'; + end if; + end if; + end if; + end process p_done_out; + + --============================================================================ + -- Process p_pd_out + --! Output of phase detector + --! read: done_sys_r2, done_sys_r, phase_detector_acc\n + --! write: phase_detector_o\n + --! r/w: -\n + --============================================================================ + p_pd_out : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(done_sys_r2 = '0' and done_sys_r = '1') then + phase_detector_o <= std_logic_vector(phase_detector_acc); + end if; + end if; + end process p_pd_out; + +end architecture rtl; +--============================================================================== +-- architecture end +--============================================================================== diff --git a/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd b/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd new file mode 100644 index 0000000..085a43b --- /dev/null +++ b/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd @@ -0,0 +1,409 @@ +--============================================================================== +-- © Copyright CERN for the benefit of the HPTD interest group 2018. All rights not +-- expressly granted are reserved. +-- +-- This file is part of tx_phase_aligner. +-- +-- tx_phase_aligner is free VHDL code: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- tx_phase_aligner is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with tx_phase_aligner. If not, see . +--============================================================================== +--! @file tx_phase_aligner.vhd +--============================================================================== +--! Standard library +library ieee; +--! Standard packages +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--! Specific packages +------------------------------------------------------------------------------- +-- -- +-- CERN, EP-ESE-BE, HPTD +-- -- +------------------------------------------------------------------------------- +-- +-- unit name: Tx Phase Aligner for usage when elastic buffer is enabled (tx_phase_aligner) +-- +--! @brief Tx Phase Aligner for usage when elastic buffer is enabled +--! - Implements tx phase alignment procedure +--! - It is recommended to keep this block in a reset state ('reset_i' = 1) until the transceiver reset procedure is completed +--! - It is also recommended to keep the transmitter user logic in a reset state while the alignment procedure is not finished ('tx_aligned_o' = 0) +--! Different flavours are possible: +--! 1) At each reset, re-align transmitter with fine PI step: +--! - When is it recommended? +--! a) applications not requiring a perfect phase determinism (~5-10 ps variation) with resets +--! b) applications using this block only as a CDC strategy with minimal latency variation +--! - How to use design? +--! - Config ports: +--! Tie tx_pi_phase_calib_i to all '0' +--! Tie tx_ui_align_calib_i to '0' +--! +--! 2) At each reset, re-align the transmitter PI to a calibrated value +--! - When is it recommended? +--! a) applications requiring a perfect phase determinism (~1 ps variation) with resets +--! b) applications where the board FPGA is not subject to large temperature variations +--! - What does it cost? +--! a) Requires a initial calibration (automatically done by block) during first reset +--! b) Monitor the tx_fifo_fill_pd_o and perform re-calibration whenever it is all zeros or all ones +--! +--! - How to use design? +--! - Config ports: +--! +--! a) during first reset: +--! Tie tx_pi_phase_calib_i to all X (dont care) +--! Tie tx_ui_align_calib_i to '0' +--! +--! b) during other resets: +--! Tie tx_pi_phase_calib_i to the value of 'tx_pi_phase_o' after the first reset +--! Tie tx_ui_align_calib_i to '1' +--! +--! @author Eduardo Brandao de Souza Mendes - eduardo.brandao.de.souza.mendes@cern.ch +--! @date 03\05\2018 +--! @version 1.0 +--! @details +--! +--! Dependencies:\n +--! +--! +--! References:\n +--! \n +--! +--! +--! Modified by:\n +--! Author: Eduardo Brandao de Souza Mendes +------------------------------------------------------------------------------- +--! \n\nLast changes:\n +--! 03\05\2018 - EBSM - Created\n +--! 13\09\2018 - EBSM - Remove unused ports\n +--! +------------------------------------------------------------------------------- +--! @todo - \n +--! \n +-- +------------------------------------------------------------------------------- + +--============================================================================== +--! Entity declaration for tx_phase_aligner +--============================================================================== +entity tx_phase_aligner is + generic( + -- User choice of DRP control or port control + -- Recommended nowadays to use in DRP control as a strange behaviour was observed using the port in PI code stepping mode + g_DRP_NPORT_CTRL : boolean := true; --! Uses DRP control of port control for the transmitter PI + g_DRP_ADDR_TXPI_PPM_CFG : std_logic_vector(8 downto 0) := ("010011010") --! Check the transceiver user guide of your device for this address + ); + port ( + --============================================================================== + --! User control/monitor ports + --============================================================================== + -- Clock / reset + clk_sys_i : in std_logic; --! system clock input + reset_i : in std_logic; --! active high sync. reset (recommended to keep reset_i=1 while transceiver reset initialization is being performed) + + -- Top level interface + tx_aligned_o : out std_logic; --! Use it as a reset for the user transmitter logic + + -- Config (for different flavours) + tx_pi_phase_calib_i : in std_logic_vector(6 downto 0); --! previous calibrated tx pi phase (tx_pi_phase_o after first reset calibration) + tx_ui_align_calib_i : in std_logic; --! align with previous calibrated tx pi phase + tx_fifo_fill_pd_max_i : in std_logic_vector(31 downto 0); --! phase detector accumulated max output, sets precision of phase detector + --! this is supposedly a static signal, this block shall be reset whenever this signal changes + --! the time for each phase detection after a clear is given by tx_fifo_fill_pd_max_i * PERIOD_clk_txusr_i + tx_fine_realign_i : in std_logic; --! A rising edge will cause the Tx to perform a fine realignment to the half-response + + -- It is only valid to re-shift clock once aligned (tx_aligned_o = '1') + ps_strobe_i : in std_logic; --! pulse synchronous to clk_sys_i to activate a shift in the phase (only captured rising edge, so a signal larger than a pulse is also fine) + ps_inc_ndec_i : in std_logic; --! 1 increments phase by phase_step_i units, 0 decrements phase by phase_step_i units + ps_phase_step_i : in std_logic_vector(3 downto 0); --! number of units to shift the phase of the receiver clock (see Xilinx transceiver User Guide to convert units in time) + ps_done_o : out std_logic; --! pulse synchronous to clk_sys_i to indicate a phase shift was performed + + -- Tx PI phase value + tx_pi_phase_o : out std_logic_vector(6 downto 0); --! phase shift accumulated + + -- Tx fifo fill level phase detector + tx_fifo_fill_pd_o : out std_logic_vector(31 downto 0); --! phase detector output, when aligned this value should be close to (0x2_0000) + + --============================================================================== + --! MGT ports + --============================================================================== + clk_txusr_i : in std_logic; --! txusr2clk + -- Tx fifo fill level - see Xilinx transceiver User Guide for more information + tx_fifo_fill_level_i : in std_logic; --! connect to txbufstatus[0] + + -- Transmitter PI ports - see Xilinx transceiver User Guide for more information + -- obs1: all txpi ports shall be connected to the transceiver even when using this block in DRP-mode + txpippmen_o : out std_logic; --! enable tx phase interpolator controller + txpippmovrden_o : out std_logic; --! enable DRP control of tx phase interpolator + txpippmsel_o : out std_logic; --! set to 1 when using tx pi ppm controler + txpippmpd_o : out std_logic; --! power down transmitter phase interpolator + txpippmstepsize_o : out std_logic_vector(4 downto 0); --! sets step size and direction of phase shift with port control PI code stepping mode + + -- DRP interface - see Xilinx transceiver User Guide for more information + -- obs2: connect clk_sys_i to drpclk + -- obs3: if using this block in port-mode, DRP output can be left floating and input connected to '0' + drpaddr_o : out std_logic_vector(8 downto 0); --! For devices with a 10-bit DRP address interface, connect MSB to '0' + drpen_o : out std_logic; --! DRP enable transaction + drpdi_o : out std_logic_vector(15 downto 0); --! DRP data write + drprdy_i : in std_logic; --! DRP finished transaction + drpdo_i : in std_logic_vector(15 downto 0); --! DRP data read; not used nowadays, write only interface + drpwe_o : out std_logic --! DRP write enable + + ); +end tx_phase_aligner; + +--============================================================================== +-- architecture declaration +--============================================================================== + +architecture rtl of tx_phase_aligner is + + --! Function declaration + + --! Constant declaration + constant c_SPEED_PD_FACTOR : integer range 0 to 19 := 7; + constant c_PI_COARSE_STEP : integer range 0 to 15 := 8; + constant c_PI_FINE_STEP : integer range 0 to 15 := 1; + + --! Signal declaration + -- tx_pi_ctrl <-> tx_phase_aligner_fsm + signal tx_aligner_tx_pi_strobe : std_logic; + signal tx_aligner_tx_pi_inc_ndec : std_logic; + signal tx_aligner_tx_pi_phase_step : std_logic_vector(3 downto 0); + signal tx_aligner_tx_pi_done : std_logic; + + signal tx_pi_strobe : std_logic; + signal tx_pi_inc_ndec : std_logic; + signal tx_pi_phase_step : std_logic_vector(3 downto 0); + signal tx_pi_done : std_logic; + + signal tx_pi_phase : std_logic_vector(6 downto 0); + + -- tx_fifo_fill_level_acc <-> tx_phase_aligner_fsm + signal tx_fifo_fill_pd_clear : std_logic; + signal tx_fifo_fill_pd_done : std_logic; + signal tx_fifo_fill_pd : std_logic_vector(31 downto 0); + signal tx_fifo_fill_pd_max : std_logic_vector(31 downto 0); + + signal reset_fifo_fill_level_acc : std_logic; + + signal tx_aligned : std_logic; + + --! Component declaration + component tx_phase_aligner_fsm is + generic( + g_SPEED_PD_FACTOR : integer range 0 to 19 := 10; --! coarse alignment procedure takes g_TX_FIFO_FILL_PD_MAX/(2**g_SPEED_PD_FACTOR) + + g_PI_COARSE_STEP : integer range 0 to 15 := 8; --! coarse PI steps + + g_PI_FINE_STEP : integer range 0 to 15 := 1 --! fine PI steps + ); + port ( + -- Clock / reset + clk_sys_i : in std_logic; --! system clock input + reset_i : in std_logic; --! active high sync. reset + + -- Top level interface + tx_aligned_o : out std_logic; --! Use it as a reset for the user transmitter logic + + -- Config (for different flavours) + tx_pi_phase_calib_i : in std_logic_vector(6 downto 0); --! previous calibrated tx pi phase + tx_ui_align_calib_i : in std_logic; --! align with previous calibrated tx pi phase + tx_enable_reset_i : in std_logic; --! enable tx reset for perfect phase alignment (only relevant if tx_ui_align_calib_i is '1') + tx_fifo_fill_pd_max_i : in std_logic_vector(31 downto 0); --! phase detector accumulated max output, sets precision of phase detector + --! this is supposedly a static signal, this block shall be reset whenever this signal changes + --! the time for each phase detection after a clear is given by tx_fifo_fill_pd_max_i * PERIOD_clk_txusr_i + tx_fine_realign_i : in std_logic; --! A rising edge will cause the Tx to perform a fine realignment to the half-response + + -- Tx pi controller interface - see user interface tx_pi_ctrl.vhd for more information + tx_pi_strobe_o : out std_logic; --! see user interface tx_pi_ctrl.vhd for more information + tx_pi_inc_ndec_o : out std_logic; --! see user interface tx_pi_ctrl.vhd for more information + tx_pi_phase_step_o : out std_logic_vector(3 downto 0); --! see user interface tx_pi_ctrl.vhd for more information + tx_pi_done_i : in std_logic; --! see user interface tx_pi_ctrl.vhd for more information + tx_pi_phase_i : in std_logic_vector(6 downto 0); --! see user interface tx_pi_ctrl.vhd for more information + + -- Tx fifo fill level phase detector interface - see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_clear_o : out std_logic; --! see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_done_i : in std_logic; --! see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_i : in std_logic_vector(31 downto 0); --! see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_max_o : out std_logic_vector(31 downto 0); --! see user interface fifo_fill_level_acc.vhd for more information + + -- Tx MGT reset (only used when tx_enable_reset_i is activated) + tx_reset_o : out std_logic + ); + end component tx_phase_aligner_fsm; + + component tx_pi_ctrl is + generic( + -- User choice of DRP control or port control + -- Recommended nowadays to use in DRP control as a strange behaviour was observed using the port in PI code stepping mode + g_DRP_NPORT_CTRL : boolean := true; --! Uses DRP control of port control for the transmitter PI + g_DRP_ADDR_TXPI_PPM_CFG : std_logic_vector(8 downto 0) := ("010011010") --! Check the transceiver user guide of your device for this address + ); + port ( + -- User Interface + clk_sys_i : in std_logic; --! system clock input + reset_i : in std_logic; --! active high sync. reset + strobe_i : in std_logic; --! pulse synchronous to clk_sys_i to activate a shift in the transmitter phase (only captured rising edge, so a signal larger than a pulse is also fine) + inc_ndec_i : in std_logic; --! 1 increments tx phase by phase_step_i units, 0 decrements tx phase by phase_step_i units + phase_step_i : in std_logic_vector(3 downto 0); --! number of units to shift the phase of the transmitter (see Xilinx transceiver User Guide to convert units in time) + done_o : out std_logic; --! pulse synchronous to clk_sys_i to indicate a transmitter phase shift was performed + phase_o : out std_logic_vector(6 downto 0); --! phase shift accumulated + + -- MGT interface + -- Transmitter PI ports - see Xilinx transceiver User Guide for more information + -- obs1: all txpi ports shall be connected to the transceiver even when using this block in DRP-mode + clk_txusr_i : in std_logic; --! txusr2clk + txpippmen_o : out std_logic; --! enable tx phase interpolator controller + txpippmovrden_o : out std_logic; --! enable DRP control of tx phase interpolator + txpippmsel_o : out std_logic; --! set to 1 when using tx pi ppm controler + txpippmpd_o : out std_logic; --! power down transmitter phase interpolator + txpippmstepsize_o : out std_logic_vector(4 downto 0); --! sets step size and direction of phase shift with port control PI code stepping mode + + -- DRP interface - see Xilinx transceiver User Guide for more information + -- obs2: connect clk_sys_i to drpclk + -- obs3: if using this block in port-mode, DRP output can be left floating and input connected to '0' + drpaddr_o : out std_logic_vector(8 downto 0); --! For devices with a 10-bit DRP address interface, connect MSB to '0' + drpen_o : out std_logic; --! DRP enable transaction + drpdi_o : out std_logic_vector(15 downto 0); --! DRP data write + drprdy_i : in std_logic; --! DRP finished transaction + drpdo_i : in std_logic_vector(15 downto 0); --! DRP data read; not used nowadays, write only interface + drpwe_o : out std_logic --! DRP write enable + ); + end component tx_pi_ctrl; + + component fifo_fill_level_acc is + port ( + -- User Interface + clk_sys_i : in std_logic; --! system clock input + reset_i : in std_logic; --! actived on rising edge sync. reset + done_o : out std_logic; --! latched to '1' to indicate accumulated value was reached, cleared only with clear/reset + phase_detector_o : out std_logic_vector(31 downto 0); --! phase detector accumulated output (increments for each pulse in which txfifofilllevel is 1) + phase_detector_max_i : in std_logic_vector(31 downto 0); --! phase detector accumulated max output, sets precision of phase detector + --! this is supposedly a static signal, this block shall be reset whenever this signal changes + --! the time for each phase detection after a clear is given by phase_detector_max_i * PERIOD_clk_txusr_i + -- MGT interface + -- Tx fifo fill level - see Xilinx transceiver User Guide for more information + clk_txusr_i : in std_logic; --! txusr2clk + tx_fifo_fill_level_i : in std_logic --! connect to txbufstatus[0] + ); + end component fifo_fill_level_acc; + +begin + + cmp_tx_phase_aligner_fsm : tx_phase_aligner_fsm + generic map( + g_SPEED_PD_FACTOR => c_SPEED_PD_FACTOR , + g_PI_COARSE_STEP => c_PI_COARSE_STEP , + g_PI_FINE_STEP => c_PI_FINE_STEP + ) + port map( + -- Clock / reset + clk_sys_i => clk_sys_i, + reset_i => reset_i , + + -- Top level interface + tx_aligned_o => tx_aligned , + + -- Config (for different flavours) + tx_pi_phase_calib_i => tx_pi_phase_calib_i, + tx_ui_align_calib_i => tx_ui_align_calib_i, + tx_enable_reset_i => '0', -- this special mode is not being used to simplify user integration + tx_fifo_fill_pd_max_i => tx_fifo_fill_pd_max_i, + tx_fine_realign_i => tx_fine_realign_i, + + -- Tx pi controller interface - see user interface tx_pi_ctrl.vhd for more information + tx_pi_strobe_o => tx_aligner_tx_pi_strobe, + tx_pi_inc_ndec_o => tx_aligner_tx_pi_inc_ndec, + tx_pi_phase_step_o => tx_aligner_tx_pi_phase_step, + tx_pi_done_i => tx_aligner_tx_pi_done, + tx_pi_phase_i => tx_pi_phase, + + -- Tx fifo fill level phase detector interface - see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_clear_o => tx_fifo_fill_pd_clear, + tx_fifo_fill_pd_done_i => tx_fifo_fill_pd_done, + tx_fifo_fill_pd_i => tx_fifo_fill_pd, + tx_fifo_fill_pd_max_o => tx_fifo_fill_pd_max, + + -- Tx MGT reset (only used when tx_enable_reset_i is activated) + tx_reset_o => open -- this special mode is not being used to simplify user integration + ); + + cmp_tx_pi_ctrl : tx_pi_ctrl + generic map( + -- User choice of DRP control or port control + -- Recommended nowadays to use in DRP control as a strange behaviour was observed using the port in PI code stepping mode + g_DRP_NPORT_CTRL => g_DRP_NPORT_CTRL, + g_DRP_ADDR_TXPI_PPM_CFG => g_DRP_ADDR_TXPI_PPM_CFG + ) + port map( + -- User Interface + clk_sys_i => clk_sys_i, + reset_i => reset_i , + strobe_i => tx_pi_strobe, + inc_ndec_i => tx_pi_inc_ndec, + phase_step_i => tx_pi_phase_step, + done_o => tx_pi_done, + phase_o => tx_pi_phase, + + -- MGT interface + -- Transmitter PI ports - see Xilinx transceiver User Guide for more information + -- obs1: all txpi ports shall be connected to the transceiver even when using this block in DRP-mode + clk_txusr_i => clk_txusr_i, + txpippmen_o => txpippmen_o, + txpippmovrden_o => txpippmovrden_o, + txpippmsel_o => txpippmsel_o, + txpippmpd_o => txpippmpd_o, + txpippmstepsize_o => txpippmstepsize_o, + + -- DRP interface - see Xilinx transceiver User Guide for more information + -- obs2: connect clk_sys_i to drpclk + -- obs3: if using this block in port-mode, DRP output can be left floating and input connected to '0' + drpaddr_o => drpaddr_o, + drpen_o => drpen_o, + drpdi_o => drpdi_o, + drprdy_i => drprdy_i, + drpdo_i => drpdo_i, + drpwe_o => drpwe_o + ); + + tx_pi_phase_o <= tx_pi_phase; + + tx_aligned_o <= tx_aligned; + tx_pi_strobe <= ps_strobe_i when tx_aligned = '1' else tx_aligner_tx_pi_strobe; + tx_pi_inc_ndec <= ps_inc_ndec_i when tx_aligned = '1' else tx_aligner_tx_pi_inc_ndec; + tx_pi_phase_step <= ps_phase_step_i when tx_aligned = '1' else tx_aligner_tx_pi_phase_step; + ps_done_o <= tx_pi_done when tx_aligned = '1' else '0'; + tx_aligner_tx_pi_done <= tx_pi_done when tx_aligned = '0' else '0'; + + cmp_fifo_fill_level_acc : fifo_fill_level_acc + port map( + -- User Interface + clk_sys_i => clk_sys_i, + reset_i => reset_fifo_fill_level_acc, + done_o => tx_fifo_fill_pd_done, + phase_detector_o => tx_fifo_fill_pd, + phase_detector_max_i => tx_fifo_fill_pd_max, + + -- MGT interface + -- Tx fifo fill level - see Xilinx transceiver User Guide for more information + clk_txusr_i => clk_txusr_i, + tx_fifo_fill_level_i => tx_fifo_fill_level_i + ); + reset_fifo_fill_level_acc <= reset_i or tx_fifo_fill_pd_clear; + + tx_fifo_fill_pd_o <= tx_fifo_fill_pd; + +end architecture rtl; +--============================================================================== +-- architecture end +--============================================================================== diff --git a/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd b/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd new file mode 100644 index 0000000..6df86da --- /dev/null +++ b/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd @@ -0,0 +1,455 @@ +--============================================================================== +-- © Copyright CERN for the benefit of the HPTD interest group 2018. All rights not +-- expressly granted are reserved. +-- +-- This file is part of tx_phase_aligner. +-- +-- tx_phase_aligner is free VHDL code: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- tx_phase_aligner is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with tx_phase_aligner. If not, see . +--============================================================================== +--! @file tx_phase_aligner_fsm.vhd +--============================================================================== +--! Standard library +library ieee; +--! Standard packages +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--! Specific packages +------------------------------------------------------------------------------- +-- -- +-- CERN, EP-ESE-BE, HPTD +-- -- +------------------------------------------------------------------------------- +-- +-- unit name: Tx Phase Aligner FSM logic (tx_phase_aligner_fsm) +-- +--! @brief Tx Phase Aligner FSM logic +--! - Implements control algorithm for transmitter phase alignment acting on tx_pi_ctrl and fifo_fill_level_acc +--! - Many algorithm flavour and alignment strategies are possible and those are further explained in the reference note containing this design +--! +--! @author Eduardo Brandao de Souza Mendes - eduardo.brandao.de.souza.mendes@cern.ch +--! @date 02\05\2018 +--! @version 1.0 +--! @details +--! +--! Dependencies:\n +--! +--! +--! References:\n +--! \n +--! +--! +--! Modified by:\n +--! Author: Eduardo Brandao de Souza Mendes +------------------------------------------------------------------------------- +--! \n\nLast changes:\n +--! 02\05\2018 - EBSM - Created\n +--! 13\09\2018 - EBSM - register tx_aligned_o output\n +--! +------------------------------------------------------------------------------- +--! @todo - \n +--! \n +-- +------------------------------------------------------------------------------- + +--============================================================================== +--! Entity declaration for tx_phase_aligner_fsm +--============================================================================== +entity tx_phase_aligner_fsm is + generic( + g_SPEED_PD_FACTOR : integer range 0 to 19 := 10; --! coarse alignment procedure takes tx_fifo_fill_pd_max_i/(2**g_SPEED_PD_FACTOR) + + g_PI_COARSE_STEP : integer range 0 to 15 := 8; --! coarse PI steps + + g_PI_FINE_STEP : integer range 0 to 15 := 1 --! fine PI steps + ); + port ( + -- Clock / reset + clk_sys_i : in std_logic; --! system clock input + reset_i : in std_logic; --! active high sync. reset + + -- Top level interface + tx_aligned_o : out std_logic; --! Use it as a reset for the user transmitter logic + + -- Config (for different flavours) + tx_pi_phase_calib_i : in std_logic_vector(6 downto 0); --! previous calibrated tx pi phase + tx_ui_align_calib_i : in std_logic; --! align with previous calibrated tx pi phase + tx_enable_reset_i : in std_logic; --! enable tx reset for perfect phase alignment (only relevant if tx_ui_align_calib_i is '1') + tx_fifo_fill_pd_max_i : in std_logic_vector(31 downto 0); --! phase detector accumulated max output, sets precision of phase detector + --! this is supposedly a static signal, this block shall be reset whenever this signal changes + --! the time for each phase detection after a clear is given by tx_fifo_fill_pd_max_i * PERIOD_clk_txusr_i + tx_fine_realign_i : in std_logic; --! A rising edge will cause the Tx to perform a fine realignment to the half-response + + -- Tx pi controller interface - see user interface tx_pi_ctrl.vhd for more information + tx_pi_strobe_o : out std_logic; --! see user interface tx_pi_ctrl.vhd for more information + tx_pi_inc_ndec_o : out std_logic; --! see user interface tx_pi_ctrl.vhd for more information + tx_pi_phase_step_o : out std_logic_vector(3 downto 0); --! see user interface tx_pi_ctrl.vhd for more information + tx_pi_done_i : in std_logic; --! see user interface tx_pi_ctrl.vhd for more information + tx_pi_phase_i : in std_logic_vector(6 downto 0); --! see user interface tx_pi_ctrl.vhd for more information + + -- Tx fifo fill level phase detector interface - see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_clear_o : out std_logic; --! see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_done_i : in std_logic; --! see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_i : in std_logic_vector(31 downto 0); --! see user interface fifo_fill_level_acc.vhd for more information + tx_fifo_fill_pd_max_o : out std_logic_vector(31 downto 0); --! see user interface fifo_fill_level_acc.vhd for more information + + -- Tx MGT reset (only used when tx_enable_reset_i is activated) + tx_reset_o : out std_logic + ); +end tx_phase_aligner_fsm; + +--============================================================================== +-- architecture declaration +--============================================================================== + +architecture rtl of tx_phase_aligner_fsm is + + --! Function declaration + function fcn_reduce_or(arg : std_logic_vector) return std_logic is + variable result : std_logic; + begin + result := '0'; + for i in arg'range loop + result := result or arg(i); + end loop; + return result; + end; + + --! Constant declaration + + --! Signal declaration + -- FSM to control the phase alignment + -- The phase alignment is divided into four steps: + -- COARSE : Initial coarse and fast alignment to optimize time of routine, aligns to 1.0 as phase detector response + -- FINE : Fine alignment to find the ideal position where phase detector gives 0.5 as response + -- UI_ALIGN : Fine UI alignment to ensure PI position is always the same + -- ALIGNED : Keeps checking phase detector response + type t_PHASE_ALIGNER_FSM is (IDLE, -- | + -- | + COARSE_SET_CONFIG , -- | + -- v + COARSE_SHIFT_PI , -- | <--. + -- v | + COARSE_WAIT_PD , -- | | + -- |----. + -- v + FINE_SET_CONFIG , -- | <----------------------------------------------------------. + -- v | + FINE_CHECK_DIRECTION,-- | | + -- v | + FINE_SHIFT_PI , -- |<---. | + -- v | | + FINE_WAIT_PD , -- |----. | + -- v | + FINE_ALIGNED , -- | | + -- | ----------. | + -- v | | + UI_SET_OFFSET , -- | | | + -- v | | + UI_CHECK_SHIFT_PI , -- |-----------. | + -- v ^ | | | + UI_SHIFT_PI , -- ---| | | | + -- | | - IF NOT ENABLE UI ALIGNMENT | + UI_RESET_TX , -- <-----. | | + -- | | + -- | | + ALIGNED_CLEAR_PD , -- <------------. - ALIGNED | + -- | ^ ------------------------------------ + ALIGNED_WAIT_PD -- v------| - ALIGNED + ); + + signal phase_aligner_state : t_PHASE_ALIGNER_FSM; + + -- Identify rising edge of 'tx_fine_realign_i' and realign (only capture if already aligned) + signal tx_fine_realign_r : std_logic; + + -- Set configuration of PI and PD + signal tx_pi_inc_ndec : std_logic; + signal tx_pi_phase_step : std_logic_vector(tx_pi_phase_step_o'range); + signal tx_fifo_fill_pd_max : std_logic_vector(tx_fifo_fill_pd_max_o'range); + + -- half_response is used to indicate whether the + signal half_response : std_logic; + signal half_response_mem : std_logic; + + -- UI algorithm math + signal ref_dist_mod64 : unsigned(tx_pi_phase_i'left-1 downto 0); + signal ui_align_cntr : unsigned(tx_pi_phase_i'left-1 downto 0); + + -- Reset Tx pipeline + signal reset_tx_pipe : std_logic_vector(4 downto 0); + + -- Tx aligned combinatorial + signal tx_aligned : std_logic; +begin + + --============================================================================ + -- Main FSM algorithm + --============================================================================ + --============================================================================ + -- Process p_phase_aligner_fsm + --! Main FSM for the algorithm flow control + --! read: \n + --! write: -\n + --! r/w: drp_tx_pi_state\n + --============================================================================ + p_phase_aligner_fsm : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(reset_i = '1') then + phase_aligner_state <= IDLE; + else + case phase_aligner_state is + + when IDLE => + phase_aligner_state <= COARSE_SET_CONFIG; + + when COARSE_SET_CONFIG => + phase_aligner_state <= COARSE_SHIFT_PI; + + when COARSE_SHIFT_PI => + if(tx_pi_done_i = '1') then + phase_aligner_state <= COARSE_WAIT_PD; + end if; + + when COARSE_WAIT_PD => + if(tx_fifo_fill_pd_done_i = '1') then + if(tx_fifo_fill_pd_i(tx_fifo_fill_pd_i'left - g_SPEED_PD_FACTOR downto 0) = tx_fifo_fill_pd_max_i(tx_fifo_fill_pd_max_i'left downto g_SPEED_PD_FACTOR))then + phase_aligner_state <= FINE_SET_CONFIG; --reached full PD response (1.0) + else + phase_aligner_state <= COARSE_SHIFT_PI; + end if; + end if; + + when FINE_SET_CONFIG => + phase_aligner_state <= FINE_CHECK_DIRECTION; + + when FINE_CHECK_DIRECTION => + if(tx_fifo_fill_pd_done_i = '1') then + phase_aligner_state <= FINE_SHIFT_PI; + end if; + + when FINE_SHIFT_PI => + if(tx_pi_done_i = '1') then + phase_aligner_state <= FINE_WAIT_PD; + end if; + + when FINE_WAIT_PD => + if(tx_fifo_fill_pd_done_i = '1') then + if(half_response /= half_response_mem) then --reached half PD response 0.5 + phase_aligner_state <= FINE_ALIGNED; + else + phase_aligner_state <= FINE_SHIFT_PI; + end if; + end if; + + when FINE_ALIGNED => + if(tx_ui_align_calib_i = '1') then -- go to UI mod-shift if user wants this option + phase_aligner_state <= UI_SET_OFFSET; + else + phase_aligner_state <= ALIGNED_CLEAR_PD; + end if; + + when UI_SET_OFFSET => + phase_aligner_state <= UI_CHECK_SHIFT_PI; + + when UI_CHECK_SHIFT_PI => + if(to_integer(ui_align_cntr) /= 0) then + phase_aligner_state <= UI_SHIFT_PI; + else + if(tx_enable_reset_i = '1') then + if(tx_pi_phase_i(tx_pi_phase_i'left) = tx_pi_phase_calib_i(tx_pi_phase_calib_i'left)) then --perfect alignment (mod 128) + phase_aligner_state <= ALIGNED_WAIT_PD; + else -- reset the transmitter to try to achieve perfect alignment + phase_aligner_state <= UI_RESET_TX; + end if; + else + phase_aligner_state <= ALIGNED_CLEAR_PD; + end if; + end if; + + when UI_SHIFT_PI => + if(tx_pi_done_i = '1') then + phase_aligner_state <= UI_CHECK_SHIFT_PI; + end if; + + when UI_RESET_TX => + if (reset_tx_pipe(reset_tx_pipe'left) = '1') then + phase_aligner_state <= IDLE; + end if; + + when ALIGNED_CLEAR_PD => + if(tx_fine_realign_i = '1' and tx_fine_realign_r = '0') then + phase_aligner_state <= FINE_SET_CONFIG; + else + phase_aligner_state <= ALIGNED_WAIT_PD; + end if; + + when ALIGNED_WAIT_PD => + if(tx_fine_realign_i = '1' and tx_fine_realign_r = '0') then + phase_aligner_state <= FINE_SET_CONFIG; + elsif(tx_fifo_fill_pd_done_i = '1') then + phase_aligner_state <= ALIGNED_CLEAR_PD; + end if; + + when others => + phase_aligner_state <= IDLE; + + end case; + end if; + end if; + end process p_phase_aligner_fsm; + + -- register for rising edge identification + tx_fine_realign_r <= tx_fine_realign_i when rising_edge(clk_sys_i); + + --============================================================================ + -- PI and PD control + --============================================================================ + --============================================================================ + -- Process p_set_config + --! Sets config for Tx PI and phase detector depending on part of algorithm + --! read: phase_aligner_state, tx_fifo_fill_pd_max_i, ref_dist_mod64\n + --! write: \n + --! r/w: tx_pi_inc_ndec, tx_pi_phase_step, tx_fifo_fill_pd_max\n + --============================================================================ + p_set_config : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(reset_i = '1') then + tx_pi_inc_ndec <= '0'; + tx_pi_phase_step <= (others => '0'); + tx_fifo_fill_pd_max <= (others => '0'); + else + case phase_aligner_state is + when COARSE_SET_CONFIG => + tx_pi_inc_ndec <= '1'; + tx_pi_phase_step <= std_logic_vector(to_unsigned(g_PI_COARSE_STEP, tx_pi_phase_step'length)); + tx_fifo_fill_pd_max(tx_fifo_fill_pd_max_i'left-g_SPEED_PD_FACTOR downto 0) <= tx_fifo_fill_pd_max_i(tx_fifo_fill_pd_max_i'left downto g_SPEED_PD_FACTOR); + tx_fifo_fill_pd_max(tx_fifo_fill_pd_max_i'left downto tx_fifo_fill_pd_max_i'left-g_SPEED_PD_FACTOR+1) <= (others => '0'); + + when FINE_SET_CONFIG => + tx_pi_inc_ndec <= tx_pi_inc_ndec; + tx_pi_phase_step <= std_logic_vector(to_unsigned(g_PI_FINE_STEP, tx_pi_phase_step'length)); + tx_fifo_fill_pd_max <= tx_fifo_fill_pd_max_i; + + when FINE_CHECK_DIRECTION => + tx_pi_inc_ndec <= half_response; + tx_pi_phase_step <= tx_pi_phase_step; + tx_fifo_fill_pd_max <= tx_fifo_fill_pd_max; + + when UI_SET_OFFSET => + tx_pi_inc_ndec <= not ref_dist_mod64(ref_dist_mod64'left); --not bigger than half UI + tx_pi_phase_step <= tx_pi_phase_step; + tx_fifo_fill_pd_max <= tx_fifo_fill_pd_max; + + when others => + tx_pi_inc_ndec <= tx_pi_inc_ndec; + tx_pi_phase_step <= tx_pi_phase_step; + tx_fifo_fill_pd_max <= tx_fifo_fill_pd_max; + end case; + end if; + end if; + end process p_set_config; + + tx_pi_strobe_o <= '1' when (phase_aligner_state = COARSE_SHIFT_PI or phase_aligner_state = FINE_SHIFT_PI or phase_aligner_state = UI_SHIFT_PI) else '0'; + tx_pi_inc_ndec_o <= tx_pi_inc_ndec; + tx_pi_phase_step_o <= tx_pi_phase_step; + + tx_fifo_fill_pd_clear_o <= '1' when (tx_pi_done_i = '1' or phase_aligner_state = ALIGNED_CLEAR_PD or phase_aligner_state = FINE_SET_CONFIG) else '0'; + tx_fifo_fill_pd_max_o <= tx_fifo_fill_pd_max; + + --============================================================================ + -- Math + --============================================================================ + ref_dist_mod64 <= unsigned(tx_pi_phase_calib_i(tx_pi_phase_i'left-1 downto 0)) - unsigned(tx_pi_phase_i(tx_pi_phase_i'left-1 downto 0)); + + --============================================================================ + -- Process p_half_response_mem + --! Saves half response from PD + --! read: half_response\n + --! write: half_response_mem\n + --! r/w: \n + --============================================================================ + half_response <= '1' when (unsigned(tx_fifo_fill_pd_i) <= unsigned('0'&tx_fifo_fill_pd_max_i(tx_fifo_fill_pd_max_i'left downto 1))) else '0'; + p_half_response_mem : process(clk_sys_i) + begin + if (rising_edge(clk_sys_i)) then + if (tx_fifo_fill_pd_done_i = '1') then + half_response_mem <= half_response; + end if; + end if; + end process p_half_response_mem; + + --============================================================================ + -- Process p_ui_align_cntr + --! Sets config for Tx PI and phase detector depending on part of algorithm + --! read: phase_aligner_state, ref_dist_mod64, tx_pi_done_i\n + --! write: \n + --! r/w: ui_align_cntr\n + --============================================================================ + p_ui_align_cntr : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(reset_i = '1') then + ui_align_cntr <= (others => '0'); + else + case phase_aligner_state is + when UI_SET_OFFSET => + if(ref_dist_mod64(ref_dist_mod64'left) = '1') then -- bigger than half-UI + ui_align_cntr <= (not ref_dist_mod64) + to_unsigned(1, ref_dist_mod64'length); + else + ui_align_cntr <= ref_dist_mod64; + end if; + when UI_SHIFT_PI => + if(tx_pi_done_i = '1') then + ui_align_cntr <= ui_align_cntr - 1; + end if; + when others => + ui_align_cntr <= ui_align_cntr; + end case; + end if; + end if; + end process p_ui_align_cntr; + + --============================================================================ + -- Process p_reset_tx_pipe + --! Resets transmitter pipe + --! read: phase_aligner_state\n + --! write: tx_reset_o\n + --! r/w: reset_tx_pipe\n + --============================================================================ + p_reset_tx_pipe : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(phase_aligner_state = UI_RESET_TX) then + reset_tx_pipe(0) <= '1'; + else + reset_tx_pipe(0) <= '0'; + end if; + reset_tx_pipe(reset_tx_pipe'left downto 1) <= reset_tx_pipe(reset_tx_pipe'left-1 downto 0); + + tx_reset_o <= fcn_reduce_or(reset_tx_pipe); + end if; + end process p_reset_tx_pipe; + + --============================================================================ + -- Alignment condition + --============================================================================ + tx_aligned <= '1' when (phase_aligner_state = ALIGNED_CLEAR_PD or phase_aligner_state = ALIGNED_WAIT_PD) else '0'; + tx_aligned_o <= tx_aligned when rising_edge(clk_sys_i); +end architecture rtl; +--============================================================================== +-- architecture end +--============================================================================== diff --git a/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd b/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd new file mode 100644 index 0000000..556e55b --- /dev/null +++ b/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd @@ -0,0 +1,402 @@ +--============================================================================== +-- © Copyright CERN for the benefit of the HPTD interest group 2018. All rights not +-- expressly granted are reserved. +-- +-- This file is part of tx_phase_aligner. +-- +-- tx_phase_aligner is free VHDL code: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- tx_phase_aligner is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with tx_phase_aligner. If not, see . +--============================================================================== +--! @file tx_pi_ctrl.vhd +--============================================================================== +--! Standard library +library ieee; +--! Standard packages +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +--! Specific packages +------------------------------------------------------------------------------- +-- -- +-- CERN, EP-ESE-BE, HPTD +-- -- +------------------------------------------------------------------------------- +-- +-- unit name: Tx Phase Interpolator Controller (tx_pi_ctrl) +-- +--! @brief Transmitter phase interpolator controller for GTH/GTY (Ultrascale/Ultrascale plus - UG576 and UG578) and GTH (7-series - UG476) +--! - This block provides a simple interface for controlling the phase interpolator of Xilinx devices +--! - The control can be made via DRP or via PORT (selectable through attribute g_DRP_NPORT_CTRL) +--! g_DRP_NPORT_CONTROL = true uses DRP control +--! g_DRP_NPORT_CONTROL = false uses port control (a unexpected behaviour was observed in a GTH Ultrascale plus when using port control, this is the reason why the default is DRP control) +--! - The address of DRP control is different for Ultrascale/Ultrascale plus (0x009A) and 7-series devices (0x0095) +--! Default is the address of Ultrascale as this is what was tested +--! +--! @author Eduardo Brandao de Souza Mendes - eduardo.brandao.de.souza.mendes@cern.ch +--! @date 02\05\2018 +--! @version 1.0 +--! @details +--! +--! Dependencies:\n +--! +--! +--! References:\n +--! \n +--! +--! +--! Modified by:\n +--! Author: Eduardo Brandao de Souza Mendes +------------------------------------------------------------------------------- +--! \n\nLast changes:\n +--! 02\05\2018 - EBSM - Created\n +--! +------------------------------------------------------------------------------- +--! @todo - \n +--! \n +-- +------------------------------------------------------------------------------- + +--============================================================================== +--! Entity declaration for tx_pi_ctrl +--============================================================================== +entity tx_pi_ctrl is + generic( + -- User choice of DRP control or port control + -- Recommended nowadays to use in DRP control as a strange behaviour was observed using the port in PI code stepping mode + g_DRP_NPORT_CTRL : boolean := true; --! Uses DRP control of port control for the transmitter PI + g_DRP_ADDR_TXPI_PPM_CFG : std_logic_vector(8 downto 0) := ("010011010") --! Check the transceiver user guide of your device for this address + ); + port ( + -- User Interface + clk_sys_i : in std_logic; --! system clock input + reset_i : in std_logic; --! active high sync. reset + strobe_i : in std_logic; --! pulse synchronous to clk_sys_i to activate a shift in the transmitter phase (only captured rising edge, so a signal larger than a pulse is also fine) + inc_ndec_i : in std_logic; --! 1 increments tx phase by phase_step_i units, 0 decrements tx phase by phase_step_i units + phase_step_i : in std_logic_vector(3 downto 0); --! number of units to shift the phase of the transmitter (see Xilinx transceiver User Guide to convert units in time) + done_o : out std_logic; --! pulse synchronous to clk_sys_i to indicate a transmitter phase shift was performed + phase_o : out std_logic_vector(6 downto 0); --! phase shift accumulated + + -- MGT interface + -- Transmitter PI ports - see Xilinx transceiver User Guide for more information + -- obs1: all txpi ports shall be connected to the transceiver even when using this block in DRP-mode + clk_txusr_i : in std_logic; --! txusr2clk + txpippmen_o : out std_logic; --! enable tx phase interpolator controller + txpippmovrden_o : out std_logic; --! enable DRP control of tx phase interpolator + txpippmsel_o : out std_logic; --! set to 1 when using tx pi ppm controler + txpippmpd_o : out std_logic; --! power down transmitter phase interpolator + txpippmstepsize_o : out std_logic_vector(4 downto 0); --! sets step size and direction of phase shift with port control PI code stepping mode + + -- DRP interface - see Xilinx transceiver User Guide for more information + -- obs2: connect clk_sys_i to drpclk + -- obs3: if using this block in port-mode, DRP output can be left floating and input connected to '0' + drpaddr_o : out std_logic_vector(8 downto 0); --! For devices with a 10-bit DRP address interface, connect MSB to '0' + drpen_o : out std_logic; --! DRP enable transaction + drpdi_o : out std_logic_vector(15 downto 0); --! DRP data write + drprdy_i : in std_logic; --! DRP finished transaction + drpdo_i : in std_logic_vector(15 downto 0); --! DRP data read; not used nowadays, write only interface + drpwe_o : out std_logic --! DRP write enable + ); +end tx_pi_ctrl; + +--============================================================================== +-- architecture declaration +--============================================================================== + +architecture rtl of tx_pi_ctrl is + + --! Attribute declaration + attribute async_reg : string; + + --! Constant declaration + + --! Signal declaration + + -- ============================================================================== + -- ======================== Common: PORT/DRP interface ========================== + -- ============================================================================== + -- phase accumulator + signal phase_acc : unsigned(phase_o'range); + signal strobe_r : std_logic; --rising edge detector for strobe + + -- ============================================================================== + -- ======================== Interface 1: DRP interface ========================== + -- ============================================================================== + -- FSM to control Tx PI via DRP control + -- obs: Two write a new phase value for the transmitter PI via DRP: + -- The bits 6:0 of the corresponding DRP register have to be asserted + -- The bit 7 has to be asserted high (REGISTER_1PHASE_DRP) and then low (REGISTER_0PHASE_DRP) + type t_DRP_TX_PI_FSM is (IDLE, PHASE_ACCU, PRE_REGISTER_0PHASE_DRP, WAIT_PRE_REGISTER_0PHASE_DRP, REGISTER_1PHASE_DRP, WAIT_REGISTER_1PHASE_DRP, REGISTER_0PHASE_DRP, WAIT_REGISTER_0PHASE_DRP, DONE_DRP); + signal drp_tx_pi_state : t_DRP_TX_PI_FSM; + + -- ============================================================================== + -- ======================== Interface 2: PORT interface ========================= + -- ============================================================================== + -- Closed-loop strobe_toggle strategy + -- sync to clk_sys_i + signal strobe_toggle : std_logic := '0'; + + -- sync to clk_txusr_i + signal strobe_toggle_txusr_meta : std_logic; + signal strobe_toggle_txusr_r : std_logic; + signal strobe_toggle_txusr_r2 : std_logic; + attribute async_reg of strobe_toggle_txusr_meta, strobe_toggle_txusr_r, strobe_toggle_txusr_r2 : signal is "true"; + + signal strobe_txusr : std_logic; + signal strobe_txusr_r : std_logic; + signal strobe_txusr_extend : std_logic; + signal done_toggle : std_logic := '0'; + + -- sync to clk_sys_i + signal done_toggle_sys_meta : std_logic; + signal done_toggle_sys_r : std_logic; + signal done_toggle_sys_r2 : std_logic; + attribute async_reg of done_toggle_sys_meta, done_toggle_sys_r, done_toggle_sys_r2 : signal is "true"; + + signal done : std_logic; + +begin + + -- ============================================================================== + -- ======================== Interface 1: DRP interface ========================== + -- ============================================================================== + -- Only generated if user chooses to use port control + gen_drp_interface : if g_DRP_NPORT_CTRL generate + + -- Tie Tx PI port signals + txpippmen_o <= '0'; + txpippmovrden_o <= '1'; + txpippmsel_o <= '1'; + txpippmpd_o <= '0'; + txpippmstepsize_o(4 downto 0) <= (others => '0'); + + --============================================================================ + -- Process p_strobe_r + --! Delays strobe + --! read: strobe_i\n + --! write: strobe_r\n + --! r/w: \n + --============================================================================ + p_strobe_r : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + strobe_r <= strobe_i; + end if; + end process p_strobe_r; + + --============================================================================ + -- Process p_drp_tx_pi_fsm + --! FSM for Tx PI control via DRP + --! read: strobe_i, drprdy_i\n + --! write: -\n + --! r/w: drp_tx_pi_state\n + --============================================================================ + p_drp_tx_pi_fsm : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(reset_i = '1') then + drp_tx_pi_state <= IDLE; + else + case drp_tx_pi_state is + when IDLE => + if(strobe_i = '1' and strobe_r = '0') then + drp_tx_pi_state <= PHASE_ACCU; + end if; + when PHASE_ACCU => + drp_tx_pi_state <= PRE_REGISTER_0PHASE_DRP; + when PRE_REGISTER_0PHASE_DRP => + drp_tx_pi_state <= WAIT_PRE_REGISTER_0PHASE_DRP; + when WAIT_PRE_REGISTER_0PHASE_DRP => + if(drprdy_i = '1') then + drp_tx_pi_state <= REGISTER_1PHASE_DRP; + end if; + when REGISTER_1PHASE_DRP => + drp_tx_pi_state <= WAIT_REGISTER_1PHASE_DRP; + when WAIT_REGISTER_1PHASE_DRP => + if(drprdy_i = '1') then + drp_tx_pi_state <= REGISTER_0PHASE_DRP; + end if; + when REGISTER_0PHASE_DRP => + drp_tx_pi_state <= WAIT_REGISTER_0PHASE_DRP; + when WAIT_REGISTER_0PHASE_DRP => + if(drprdy_i = '1') then + drp_tx_pi_state <= DONE_DRP; + end if; + when DONE_DRP => + drp_tx_pi_state <= IDLE; + when others => drp_tx_pi_state <= IDLE; + end case; + end if; + end if; + end process p_drp_tx_pi_fsm; + + -- Tie static DRP signals + drpaddr_o <= g_DRP_ADDR_TXPI_PPM_CFG; + drpdi_o(15 downto 8) <= (others => '0'); + + -- DRP signals controlled via FSM + drpdi_o(7) <= '1' when drp_tx_pi_state = REGISTER_1PHASE_DRP else '0'; + drpdi_o(6 downto 0) <= std_logic_vector(phase_acc); + drpen_o <= '1' when (drp_tx_pi_state = REGISTER_1PHASE_DRP or drp_tx_pi_state = REGISTER_0PHASE_DRP or drp_tx_pi_state = PRE_REGISTER_0PHASE_DRP) else '0'; + drpwe_o <= '1' when (drp_tx_pi_state = REGISTER_1PHASE_DRP or drp_tx_pi_state = REGISTER_0PHASE_DRP or drp_tx_pi_state = PRE_REGISTER_0PHASE_DRP) else '0'; + + --============================================================================ + -- Process p_phase_acc + --! Increments or decrements phase accumulator + --! read: drp_tx_pi_state, inc_ndec_i, phase_step_i\n + --! write: \n + --! r/w: phase_acc\n + --============================================================================ + p_phase_acc : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(reset_i = '1') then + phase_acc <= to_unsigned(0, phase_acc'length); + else + if(drp_tx_pi_state = PHASE_ACCU) then + if(inc_ndec_i = '1') then + phase_acc <= phase_acc + unsigned(phase_step_i); + else + phase_acc <= phase_acc - unsigned(phase_step_i); + end if; + else + phase_acc <= phase_acc; + end if; + end if; + end if; + end process p_phase_acc; + + phase_o <= std_logic_vector(phase_acc); + done_o <= '1' when (drp_tx_pi_state = DONE_DRP) else '0'; + + end generate gen_drp_interface; + + + -- ============================================================================== + -- ======================== Interface 2: PORT interface ========================= + -- ============================================================================== + -- Only generated if user chooses to use port control + gen_port_interface : if not g_DRP_NPORT_CTRL generate + -- Tie to zero unused DRP signals + drpaddr_o <= (others => '0'); + drpen_o <= '0'; + drpdi_o <= (others => '0'); + drpwe_o <= '0'; + + + -- Closed-loop clock-domain crossing strategy for strobe pulse and done as acknowledgment + --============================================================================ + -- Process p_strobe_toggle + --! Creates strobe toggle register with rising edge of strobe + --! read: strobe_i\n + --! write: -\n + --! r/w: strobe_r, strobe_toggle\n + --============================================================================ + p_strobe_toggle : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + strobe_r <= strobe_i; + if(strobe_i = '1' and strobe_r = '0') then + strobe_toggle <= not strobe_toggle; + end if; + end if; + end process p_strobe_toggle; + + --============================================================================ + -- Process p_strobe_toggle_txusrsync + --! Creates a rising edge sync to clk_txusr_i when strobe_toggle changes level and generates acknowledgment + --! read: strobe_toggle\n + --! write: done_toggle\n + --! r/w: strobe_txusr_r, strobe_txusr, strobe_toggle_txusr_r2, strobe_toggle_txusr_r, strobe_toggle_txusr_meta\n + --============================================================================ + p_strobe_toggle_txusrsync : process(clk_txusr_i) + begin + if(rising_edge(clk_txusr_i)) then + -- capture strobe + strobe_toggle_txusr_meta <= strobe_toggle; + strobe_toggle_txusr_r <= strobe_toggle_txusr_meta; + strobe_toggle_txusr_r2 <= strobe_toggle_txusr_r; + strobe_txusr <= strobe_toggle_txusr_r2 xor strobe_toggle_txusr_r; + strobe_txusr_r <= strobe_txusr; + strobe_txusr_extend <= strobe_txusr or strobe_txusr_r; + + -- acknowledgment (done) + if(strobe_txusr_r = '1') then + done_toggle <= not done_toggle; + end if; + end if; + end process p_strobe_toggle_txusrsync; + + -- Pulses txpippmen for two clock cycles - see Xilinx transceiver User Guide (reason for extension of strobe pulse in txusr domain) + txpippmen_o <= strobe_txusr_extend; + + -- Tie other signals + txpippmovrden_o <= '0'; + txpippmsel_o <= '1'; + txpippmpd_o <= '0'; + txpippmstepsize_o(4) <= inc_ndec_i; -- obs: those signals should be stable between strobe->done, the latency of the closed-loop CDC ensures a proper capture + txpippmstepsize_o(3 downto 0) <= phase_step_i; -- obs: those signals should be stable between strobe->done, the latency of the closed-loop CDC ensures a proper capture + + --============================================================================ + -- Process p_done_toggle_syssync + --! Creates a rising edge sync to clk_sys_i when done_toggle changes level + --! read: done_toggle\n + --! write: done_toggle_sys_r2\n + --! r/w: done_toggle_sys_meta, done_toggle_sys_r\n + --============================================================================ + p_done_toggle_syssync : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + done_toggle_sys_meta <= done_toggle; + done_toggle_sys_r <= done_toggle_sys_meta; + done_toggle_sys_r2 <= done_toggle_sys_r; + end if; + end process p_done_toggle_syssync; + done <= done_toggle_sys_r2 xor done_toggle_sys_r; + + --============================================================================ + -- Process p_phase_acc + --! Increments or decrements phase accumulator + --! read: done, inc_ndec_i, phase_step_i\n + --! write: done_o\n + --! r/w: phase_acc\n + --============================================================================ + p_phase_acc : process(clk_sys_i) + begin + if(rising_edge(clk_sys_i)) then + if(reset_i = '1') then + phase_acc <= to_unsigned(0, phase_acc'length); + done_o <= '0'; + else + if(done = '1') then + if(inc_ndec_i = '1') then + phase_acc <= phase_acc + unsigned(phase_step_i); + else + phase_acc <= phase_acc - unsigned(phase_step_i); + end if; + done_o <= '1'; + else + phase_acc <= phase_acc; + done_o <= '0'; + end if; + end if; + end if; + end process p_phase_acc; + phase_o <= std_logic_vector(phase_acc); + + end generate gen_port_interface; + + +end architecture rtl; +--============================================================================== +-- architecture end +--============================================================================== diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_example_bit_synchronizer.v b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_bit_synchronizer.v new file mode 100644 index 0000000..e98272a --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_bit_synchronizer.v @@ -0,0 +1,91 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ********************************************************************************************************************* +// IMPORTANT +// This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the +// existing behavior and the effects of any modifications you may choose to make. +// ********************************************************************************************************************* + +module gtwizard_ultrascale_0_example_bit_synchronizer # ( + + parameter INITIALIZE = 5'b00000, + parameter FREQUENCY = 512 + +)( + + input wire clk_in, + input wire i_in, + output wire o_out + +); + + // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to + // enable clustering. Their GSR default values are provided by the INITIALIZE parameter. + + (* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0]; + (* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1]; + (* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2]; + (* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3]; + reg i_in_out = INITIALIZE[4]; + + always @(posedge clk_in) begin + i_in_meta <= i_in; + i_in_sync1 <= i_in_meta; + i_in_sync2 <= i_in_sync1; + i_in_sync3 <= i_in_sync2; + i_in_out <= i_in_sync3; + end + + assign o_out = i_in_out; + + +endmodule diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_example_checking_raw.v b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_checking_raw.v new file mode 100644 index 0000000..8a351a8 --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_checking_raw.v @@ -0,0 +1,124 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design checking module checks PRBS31 data at the appropriate parallel data width from the receiver, +// along with performing any data manipulation or sideband signaling necessary for the selected data decoding. This +// module instance checks data from a single transceiver channel for data reception demonstration purposes. +// ===================================================================================================================== + +module gtwizard_ultrascale_0_example_checking_raw ( + input wire gtwiz_reset_all_in, + input wire gtwiz_userclk_rx_usrclk2_in, + input wire gtwiz_userclk_rx_active_in, + input wire [29:0] rxdata_in, + output reg prbs_match_out = 1'b0 +); + + + // ------------------------------------------------------------------------------------------------------------------- + // Reset synchronizer + // ------------------------------------------------------------------------------------------------------------------- + + // Synchronize the example stimulus reset condition into the rxusrclk2 domain + wire example_checking_reset_int = gtwiz_reset_all_in || ~gtwiz_userclk_rx_active_in; + wire example_checking_reset_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_reset_synchronizer example_checking_reset_synchronizer_inst ( + .clk_in (gtwiz_userclk_rx_usrclk2_in), + .rst_in (example_checking_reset_int), + .rst_out (example_checking_reset_sync) + ); + + + // ------------------------------------------------------------------------------------------------------------------- + // PRBS checker enable and sideband control generation + // ------------------------------------------------------------------------------------------------------------------- + + // For raw mode data reception, the PRBS checker is always enabled + wire prbs_any_chk_en_int = 1'b1; + + + // ------------------------------------------------------------------------------------------------------------------- + // PRBS checker block + // ------------------------------------------------------------------------------------------------------------------- + + // The prbs_any block, described in Xilinx Application Note 884 (XAPP884), "An Attribute-Programmable PRBS Generator + // and Checker", generates or checks a parameterizable PRBS sequence. Instantiate and parameterize a prbs_any block + // to check a PRBS31 sequence with parallel data sized to the receiver user data width. + wire [29:0] prbs_any_chk_error_int; + + gtwizard_ultrascale_0_prbs_any # ( + .CHK_MODE (1), + .INV_PATTERN (0), // non-inverting EBSM + .POLY_LENGHT (31), + .POLY_TAP (28), + .NBITS (30) + ) prbs_any_chk_inst ( + .RST (example_checking_reset_sync), + .CLK (gtwiz_userclk_rx_usrclk2_in), + .DATA_IN (rxdata_in), + .EN (prbs_any_chk_en_int), + .DATA_OUT (prbs_any_chk_error_int) + ); + + // The prbs_any block indicates a match of the parallel PRBS data when all DATA_OUT bits are 0. Register the result + // of the NOR function as the PRBS match indicator. + always @(posedge gtwiz_userclk_rx_usrclk2_in) begin + if (example_checking_reset_sync) + prbs_match_out <= 1'b0; + else + prbs_match_out <= ~(|prbs_any_chk_error_int); + end + + +endmodule diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_example_init.v b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_init.v new file mode 100644 index 0000000..b9f1b87 --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_init.v @@ -0,0 +1,293 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design initialization module provides a demonstration of how initialization logic can be constructed to +// interact with and enhance the reset controller helper block in order to assist with successful system bring-up. This +// example initialization logic monitors for timely reset completion, retrying resets as necessary to mitigate problems +// with system bring-up such as clock or data connection readiness. This is an example and can be modified as necessary. +// ===================================================================================================================== + +module gtwizard_ultrascale_0_example_init # ( + + parameter real P_FREERUN_FREQUENCY = 125, + parameter real P_TX_TIMER_DURATION_US = 30000 + 200000, + parameter real P_RX_TIMER_DURATION_US = 130000 + 200000 + +)( + + input wire clk_freerun_in, + input wire reset_all_in, + input wire tx_init_done_in, + input wire rx_init_done_in, + input wire rx_data_good_in, + output reg reset_all_out = 1'b0, + output reg reset_rx_out = 1'b0, + output reg init_done_out = 1'b0, + output reg [3:0] retry_ctr_out = 4'd0 + +); + + + // ------------------------------------------------------------------------------------------------------------------- + // Synchronizers + // ------------------------------------------------------------------------------------------------------------------- + + // Synchronize the "reset all" input signal into the free-running clock domain + // The reset_all_in input should be driven by the master "reset all" example design input + wire reset_all_sync; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_reset_synchronizer reset_synchronizer_reset_all_inst ( + .clk_in (clk_freerun_in), + .rst_in (reset_all_in), + .rst_out (reset_all_sync) + ); + + // Synchronize the TX initialization done indicator into the free-running clock domain + // The tx_init_done_in input should be driven by the signal or logical combination of signals that represents a + // completed TX initialization process; for example, the reset helper block gtwiz_reset_tx_done_out signal, or the + // logical AND of gtwiz_reset_tx_done_out with gtwiz_buffbypass_tx_done_out if the TX buffer is bypassed. + wire tx_init_done_sync; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_tx_init_done_inst ( + .clk_in (clk_freerun_in), + .i_in (tx_init_done_in), + .o_out (tx_init_done_sync) + ); + + // Synchronize the RX initialization done indicator into the free-running clock domain + // The rx_init_done_in input should be driven by the signal or logical combination of signals that represents a + // completed RX initialization process; for example, the reset helper block gtwiz_reset_rx_done_out signal, or the + // logical AND of gtwiz_reset_rx_done_out with gtwiz_buffbypass_rx_done_out if the RX elastic buffer is bypassed. + wire rx_init_done_sync; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_rx_init_done_inst ( + .clk_in (clk_freerun_in), + .i_in (rx_init_done_in), + .o_out (rx_init_done_sync) + ); + + // Synchronize the RX data good indicator into the free-running clock domain + // The rx_data_good_in input should be driven the user application's indication of continual good data reception. + // The example design drives rx_data_good_in high when no PRBS checker errors are seen in the 8 most recent + // consecutive clock cycles of data reception. + wire rx_data_good_sync; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_rx_data_good_inst ( + .clk_in (clk_freerun_in), + .i_in (rx_data_good_in), + .o_out (rx_data_good_sync) + ); + + + // ------------------------------------------------------------------------------------------------------------------- + // Timer + // ------------------------------------------------------------------------------------------------------------------- + + // Declare registers and local parameters used for the shared TX and RX initialization timer + // The free-running clock frequency is specified by the P_FREERUN_FREQUENCY parameter. The TX initialization timer + // duration is specified by the P_TX_TIMER_DURATION_US parameter (default 30,000us), and the resulting terminal count + // is assigned to p_tx_timer_term_cyc_int. The RX initialization timer duration is specified by the + // P_RX_TIMER_DURATION_US parameter (default 130,000us), and the resulting terminal count is assigned to + // p_rx_timer_term_cyc_int. + reg timer_clr = 1'b1; + reg [24:0] timer_ctr = 25'd0; + reg tx_timer_sat = 1'b0; + reg rx_timer_sat = 1'b0; + wire [24:0] p_tx_timer_term_cyc_int = P_TX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; + wire [24:0] p_rx_timer_term_cyc_int = P_RX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; + + // When the timer is enabled by the initialization state machine, increment the timer_ctr counter until its value + // reaches p_rx_timer_term_cyc_int RX terminal count and rx_timer_sat is asserted. Assert tx_timer_sat when the + // counter value reaches the p_tx_timer_term_cyc_int TX terminal count. Clear the timer and remove assertions when the + // timer is disabled by the initialization state machine. + always @(posedge clk_freerun_in) begin + if (timer_clr) begin + timer_ctr <= 25'd0; + tx_timer_sat <= 1'b0; + rx_timer_sat <= 1'b0; + end + else begin + if (timer_ctr == p_tx_timer_term_cyc_int) + tx_timer_sat <= 1'b1; + + if (timer_ctr == p_rx_timer_term_cyc_int) + rx_timer_sat <= 1'b1; + else + timer_ctr <= timer_ctr + 25'd1; + end + end + + + // ------------------------------------------------------------------------------------------------------------------- + // Retry counter + // ------------------------------------------------------------------------------------------------------------------- + + // Increment the retry_ctr_out register for each TX or RX reset asserted by the initialization state machine until the + // register saturates at 4'd15. This value, which is initialized on device programming and is never reset, could be + // useful for debugging purposes. The initialization state machine will continue to retry as needed beyond the retry + // register saturation point indicated, so 4'd15 should be interpreted as "15 or more attempts since programming." + reg retry_ctr_incr = 1'b0; + + always @(posedge clk_freerun_in) begin + if ((retry_ctr_incr == 1'b1) && (retry_ctr_out != 4'd15)) + retry_ctr_out <= retry_ctr_out + 4'd1; + end + + + // ------------------------------------------------------------------------------------------------------------------- + // Initialization state machine + // ------------------------------------------------------------------------------------------------------------------- + + // Declare local parameters and state register for the initialization state machine + localparam [1:0] ST_START = 2'd0; + localparam [1:0] ST_TX_WAIT = 2'd1; + localparam [1:0] ST_RX_WAIT = 2'd2; + localparam [1:0] ST_MONITOR = 2'd3; + reg [1:0] sm_init = ST_START; + reg sm_init_active = 1'b0; + + // Implement the initialization state machine control and its outputs as a single sequential process. The state + // machine is reset by the synchronized reset_all_in input, and does not begin operating until its first use. Note + // that this state machine is designed to interact with and enhance the reset controller helper block. + always @(posedge clk_freerun_in) begin + if (reset_all_sync) begin + timer_clr <= 1'b1; + reset_all_out <= 1'b0; + reset_rx_out <= 1'b0; + retry_ctr_incr <= 1'b0; + init_done_out <= 1'b0; + sm_init_active <= 1'b1; + sm_init <= ST_START; + end + else begin + case (sm_init) + + // When starting the initialization procedure, clear the timer and remove reset outputs, then proceed to wait + // for completion of TX initialization + ST_START: begin + if (sm_init_active) begin + timer_clr <= 1'b1; + reset_all_out <= 1'b0; + reset_rx_out <= 1'b0; + retry_ctr_incr <= 1'b0; + if(tx_init_done_sync == 1'b0) begin // EBSM: After a reset the tx init done should necessarily go to 0 before being asserted to 1 + sm_init <= ST_TX_WAIT; + end + end + end + + // Enable the timer. If TX initialization completes before the counter's TX terminal count, clear the timer and + // proceed to wait for RX initialization. If the TX terminal count is reached, clear the timer, assert the + // reset_all_out output (which in this example causes a master reset_all assertion), and increment the retry + // counter. Completion conditions for TX initialization are described above. + ST_TX_WAIT: begin + if (tx_init_done_sync) begin + timer_clr <= 1'b1; + reset_rx_out <= 1'b0; + sm_init <= ST_RX_WAIT; + end + else begin + if (tx_timer_sat) begin + timer_clr <= 1'b1; + reset_all_out <= 1'b1; + reset_rx_out <= 1'b0; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; + end + else begin + timer_clr <= 1'b0; + reset_rx_out <= 1'b1; + end + end + end + + // Enable the timer. When the RX terminal count is reached, check whether RX initialization has completed and + // whether the data good indicator is high. If both conditions are met, transition to the MONITOR state. If + // either condition is not met, then clear the timer, assert the reset_rx_out output (which in this example + // either drives gtwiz_reset_rx_pll_and_datapath_in or gtwiz_reset_rx_datapath_in, depending on PLL sharing), + // and increnent the retry counter. + ST_RX_WAIT: begin + if (rx_timer_sat) begin + if (rx_init_done_sync && rx_data_good_sync) begin + init_done_out <= 1'b1; + sm_init <= ST_MONITOR; + end + else begin + timer_clr <= 1'b1; + reset_rx_out <= 1'b1; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; + end + end + else begin + timer_clr <= 1'b0; + end + end + + // In this MONITOR state, assert the init_done_out output for use as desired. If RX initialization or the data + // good indicator is lost while in this state, reset the RX components as described in the ST_RX_WAIT state. + ST_MONITOR: begin + if (~rx_init_done_sync || ~rx_data_good_sync) begin + init_done_out <= 1'b0; + timer_clr <= 1'b1; + reset_rx_out <= 1'b1; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; + end + end + + endcase + end + end + + +endmodule diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_example_reset_synchronizer.v b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_reset_synchronizer.v new file mode 100644 index 0000000..4ecfcbf --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_reset_synchronizer.v @@ -0,0 +1,101 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ********************************************************************************************************************* +// IMPORTANT +// This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the +// existing behavior and the effects of any modifications you may choose to make. +// ********************************************************************************************************************* + +module gtwizard_ultrascale_0_example_reset_synchronizer # ( + + parameter FREQUENCY = 512 + +)( + + input wire clk_in, + input wire rst_in, + output wire rst_out + +); + + // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to + // enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also + // asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the + // downstream logic is also removed from reset synchronously. This module is designed for active-high reset use. + + (* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0; + (* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0; + (* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0; + (* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0; + reg rst_in_out = 1'b0; + + always @(posedge clk_in, posedge rst_in) begin + if (rst_in) begin + rst_in_meta <= 1'b1; + rst_in_sync1 <= 1'b1; + rst_in_sync2 <= 1'b1; + rst_in_sync3 <= 1'b1; + rst_in_out <= 1'b1; + end + else begin + rst_in_meta <= 1'b0; + rst_in_sync1 <= rst_in_meta; + rst_in_sync2 <= rst_in_sync1; + rst_in_sync3 <= rst_in_sync2; + rst_in_out <= rst_in_sync3; + end + end + + assign rst_out = rst_in_out; + + +endmodule diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_example_stimulus_raw.v b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_stimulus_raw.v new file mode 100644 index 0000000..dadd8bb --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_stimulus_raw.v @@ -0,0 +1,111 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design stimulus module generates PRBS31 data at the appropriate parallel data width for the transmitter, +// along with any sideband signaling necessary for the selected data encoding. The stimulus provided by this module +// instance drives a single transceiver channel for data transmission demonstration purposes. +// ===================================================================================================================== + +module gtwizard_ultrascale_0_example_stimulus_raw ( + input wire gtwiz_reset_all_in, + input wire gtwiz_userclk_tx_usrclk2_in, + input wire gtwiz_userclk_tx_active_in, + output wire [29:0] txdata_out +); + + + // ------------------------------------------------------------------------------------------------------------------- + // Reset synchronizer + // ------------------------------------------------------------------------------------------------------------------- + + // Synchronize the example stimulus reset condition into the txusrclk2 domain + wire example_stimulus_reset_int = gtwiz_reset_all_in || ~gtwiz_userclk_tx_active_in; + wire example_stimulus_reset_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_reset_synchronizer example_stimulus_reset_synchronizer_inst ( + .clk_in (gtwiz_userclk_tx_usrclk2_in), + .rst_in (example_stimulus_reset_int), + .rst_out (example_stimulus_reset_sync) + ); + + + // ------------------------------------------------------------------------------------------------------------------- + // PRBS generator output enable and sideband control generation + // ------------------------------------------------------------------------------------------------------------------- + + // For raw mode data transmission, the PRBS generator is always enabled + wire prbs_any_gen_en_int = 1'b1; + + + // ------------------------------------------------------------------------------------------------------------------- + // PRBS generator block + // ------------------------------------------------------------------------------------------------------------------- + + // The prbs_any block, described in Xilinx Application Note 884 (XAPP884), "An Attribute-Programmable PRBS Generator + // and Checker", generates or checks a parameterizable PRBS sequence. Instantiate and parameterize a prbs_any block + // to generate a PRBS31 sequence with parallel data sized to the transmitter user data width. + gtwizard_ultrascale_0_prbs_any # ( + .CHK_MODE (0), + .INV_PATTERN (0), // non-inverting EBSM + .POLY_LENGHT (31), + .POLY_TAP (28), + .NBITS (30) + ) prbs_any_gen_inst ( + .RST (example_stimulus_reset_sync), + .CLK (gtwiz_userclk_tx_usrclk2_in), + .DATA_IN (30'b0), + .EN (prbs_any_gen_en_int), + .DATA_OUT (txdata_out) + ); + +endmodule diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_example_top.v b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_top.v new file mode 100644 index 0000000..b33887a --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_top.v @@ -0,0 +1,1157 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design top module instantiates the example design wrapper; slices vectored ports for per-channel +// assignment; and instantiates example resources such as buffers, pattern generators, and pattern checkers for core +// demonstration purposes +// ===================================================================================================================== + +module gtwizard_ultrascale_0_example_top ( + + // Differential reference clock inputs + input wire mgtrefclk0_x0y3_p, + input wire mgtrefclk0_x0y3_n, + input wire mgtrefclk1_x0y2_p, + input wire mgtrefclk1_x0y2_n, + + // Differential recovered clock outputs + output wire rxrecclkout_chx0y11_p, + output wire rxrecclkout_chx0y11_n, + + output wire rxusrclk, // Added by EBSM (this clock goes through the fabric) + + // Serial data ports for transceiver channel 0 + input wire ch0_gthrxn_in, + input wire ch0_gthrxp_in, + output wire ch0_gthtxn_out, + output wire ch0_gthtxp_out, + + // User-provided ports for reset helper block(s) + input wire hb_gtwiz_reset_clk_freerun_in_p, + input wire hb_gtwiz_reset_clk_freerun_in_n, + input wire hb_gtwiz_reset_all_in, + + // PRBS-based link status ports + input wire link_down_latched_reset_in, + output wire link_status_out, + output reg link_down_latched_out = 1'b1, + + // Link locking status + output wire rx_locked_out, + output wire tx_aligned_out + +); + + + // =================================================================================================================== + // PER-CHANNEL SIGNAL ASSIGNMENTS + // =================================================================================================================== + + // The core and example design wrapper vectorize ports across all enabled transceiver channel and common instances for + // simplicity and compactness. This example design top module assigns slices of each vector to individual, per-channel + // signal vectors for use if desired. Signals which connect to helper blocks are prefixed "hb#", signals which connect + // to transceiver common primitives are prefixed "cm#", and signals which connect to transceiver channel primitives + // are prefixed "ch#", where "#" is the sequential resource number. + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gthrxn_int; + assign gthrxn_int[0:0] = ch0_gthrxn_in; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gthrxp_int; + assign gthrxp_int[0:0] = ch0_gthrxp_in; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gthtxn_int; + assign ch0_gthtxn_out = gthtxn_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gthtxp_int; + assign ch0_gthtxp_out = gthtxp_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_tx_reset_int; + wire [0:0] hb0_gtwiz_userclk_tx_reset_int; + assign gtwiz_userclk_tx_reset_int[0:0] = hb0_gtwiz_userclk_tx_reset_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_tx_srcclk_int; + wire [0:0] hb0_gtwiz_userclk_tx_srcclk_int; + assign hb0_gtwiz_userclk_tx_srcclk_int = gtwiz_userclk_tx_srcclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_tx_usrclk_int; + wire [0:0] hb0_gtwiz_userclk_tx_usrclk_int; + assign hb0_gtwiz_userclk_tx_usrclk_int = gtwiz_userclk_tx_usrclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_tx_usrclk2_int; + wire [0:0] hb0_gtwiz_userclk_tx_usrclk2_int; + assign hb0_gtwiz_userclk_tx_usrclk2_int = gtwiz_userclk_tx_usrclk2_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_tx_active_int; + wire [0:0] hb0_gtwiz_userclk_tx_active_int; + assign hb0_gtwiz_userclk_tx_active_int = gtwiz_userclk_tx_active_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_rx_reset_int; + wire [0:0] hb0_gtwiz_userclk_rx_reset_int; + assign gtwiz_userclk_rx_reset_int[0:0] = hb0_gtwiz_userclk_rx_reset_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_rx_srcclk_int; + wire [0:0] hb0_gtwiz_userclk_rx_srcclk_int; + assign hb0_gtwiz_userclk_rx_srcclk_int = gtwiz_userclk_rx_srcclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_rx_usrclk_int; + wire [0:0] hb0_gtwiz_userclk_rx_usrclk_int; + assign hb0_gtwiz_userclk_rx_usrclk_int = gtwiz_userclk_rx_usrclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_rx_usrclk2_int; + wire [0:0] hb0_gtwiz_userclk_rx_usrclk2_int; + assign hb0_gtwiz_userclk_rx_usrclk2_int = gtwiz_userclk_rx_usrclk2_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_userclk_rx_active_int; + wire [0:0] hb0_gtwiz_userclk_rx_active_int; + assign hb0_gtwiz_userclk_rx_active_int = gtwiz_userclk_rx_active_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_buffbypass_rx_reset_int; + wire [0:0] hb0_gtwiz_buffbypass_rx_reset_int; + assign gtwiz_buffbypass_rx_reset_int[0:0] = hb0_gtwiz_buffbypass_rx_reset_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_buffbypass_rx_start_user_int; + wire [0:0] hb0_gtwiz_buffbypass_rx_start_user_int = 1'b0; + assign gtwiz_buffbypass_rx_start_user_int[0:0] = hb0_gtwiz_buffbypass_rx_start_user_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_buffbypass_rx_done_int; + wire [0:0] hb0_gtwiz_buffbypass_rx_done_int; + assign hb0_gtwiz_buffbypass_rx_done_int = gtwiz_buffbypass_rx_done_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_buffbypass_rx_error_int; + wire [0:0] hb0_gtwiz_buffbypass_rx_error_int; + assign hb0_gtwiz_buffbypass_rx_error_int = gtwiz_buffbypass_rx_error_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_clk_freerun_int; + wire [0:0] hb0_gtwiz_reset_clk_freerun_int = 1'b0; + assign gtwiz_reset_clk_freerun_int[0:0] = hb0_gtwiz_reset_clk_freerun_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_all_int; + wire [0:0] hb0_gtwiz_reset_all_int = 1'b0; + assign gtwiz_reset_all_int[0:0] = hb0_gtwiz_reset_all_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_tx_pll_and_datapath_int; + wire [0:0] hb0_gtwiz_reset_tx_pll_and_datapath_int; + //assign gtwiz_reset_tx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_tx_pll_and_datapath_int; //commented by EBSM, tx reset can also be issued by tx_phase_aligner + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_tx_datapath_int; + wire [0:0] hb0_gtwiz_reset_tx_datapath_int; + assign gtwiz_reset_tx_datapath_int[0:0] = hb0_gtwiz_reset_tx_datapath_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_rx_pll_and_datapath_int; + wire [0:0] hb0_gtwiz_reset_rx_pll_and_datapath_int = 1'b0; + assign gtwiz_reset_rx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_rx_pll_and_datapath_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_rx_datapath_int; + wire [0:0] hb0_gtwiz_reset_rx_datapath_int = 1'b0; + assign gtwiz_reset_rx_datapath_int[0:0] = hb0_gtwiz_reset_rx_datapath_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_rx_cdr_stable_int; + wire [0:0] hb0_gtwiz_reset_rx_cdr_stable_int; + assign hb0_gtwiz_reset_rx_cdr_stable_int = gtwiz_reset_rx_cdr_stable_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_tx_done_int; + wire [0:0] hb0_gtwiz_reset_tx_done_int; + assign hb0_gtwiz_reset_tx_done_int = gtwiz_reset_tx_done_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtwiz_reset_rx_done_int; + wire [0:0] hb0_gtwiz_reset_rx_done_int; + assign hb0_gtwiz_reset_rx_done_int = gtwiz_reset_rx_done_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [31:0] gtwiz_userdata_tx_int; + wire [31:0] hb0_gtwiz_userdata_tx_int; + wire tx_data_sel; + assign gtwiz_userdata_tx_int[31:0] = (tx_data_sel) ? (32'b00000000000000011111111111111110) : hb0_gtwiz_userdata_tx_int; //modified by EBSM to include clock pattern + + //-------------------------------------------------------------------------------------------------------------------- + wire [31:0] gtwiz_userdata_rx_int; + wire [31:0] hb0_gtwiz_userdata_rx_int; + assign hb0_gtwiz_userdata_rx_int = gtwiz_userdata_rx_int[31:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtrefclk00_int; + wire [0:0] cm0_gtrefclk00_int; + assign gtrefclk00_int[0:0] = cm0_gtrefclk00_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] gtrefclk01_int; + wire [0:0] cm0_gtrefclk01_int; + assign gtrefclk01_int[0:0] = cm0_gtrefclk01_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] qpll0outclk_int; + wire [0:0] cm0_qpll0outclk_int; + assign cm0_qpll0outclk_int = qpll0outclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] qpll0outrefclk_int; + wire [0:0] cm0_qpll0outrefclk_int; + assign cm0_qpll0outrefclk_int = qpll0outrefclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] qpll1outclk_int; + wire [0:0] cm0_qpll1outclk_int; + assign cm0_qpll1outclk_int = qpll1outclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] qpll1outrefclk_int; + wire [0:0] cm0_qpll1outrefclk_int; + assign cm0_qpll1outrefclk_int = qpll1outrefclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [8:0] drpaddr_int; + //wire [8:0] ch0_drpaddr_int = 9'b000000000; //commented by EBSM - controlled by phase aligner + //assign drpaddr_int[8:0] = ch0_drpaddr_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] drpclk_int; + //wire [0:0] ch0_drpclk_int = 1'b0; //commented by EBSM - use clk_sys for drp for phase aligner + //assign drpclk_int[0:0] = ch0_drpclk_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [15:0] drpdi_int; + //wire [15:0] ch0_drpdi_int = 16'b0000000000000000; //commented by EBSM - controlled by phase aligner + //assign drpdi_int[15:0] = ch0_drpdi_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] drpen_int; + //wire [0:0] ch0_drpen_int = 1'b0; //commented by EBSM - controlled by phase aligner + //assign drpen_int[0:0] = ch0_drpen_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] drpwe_int; + //wire [0:0] ch0_drpwe_int = 1'b0; //commented by EBSM - controlled by phase aligner + //assign drpwe_int[0:0] = ch0_drpwe_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [2:0] loopback_int; + // This vector is not sliced because it is directly assigned in a debug core instance below + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxcdrreset_int; + // This vector is not sliced because it is directly assigned in a debug core instance below + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxpolarity_int; + wire [0:0] ch0_rxpolarity_int = 1'b0; + assign rxpolarity_int[0:0] = ch0_rxpolarity_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxprbscntreset_int; + // This vector is not sliced because it is directly assigned in a debug core instance below + + //-------------------------------------------------------------------------------------------------------------------- + wire [3:0] rxprbssel_int; + // This vector is not sliced because it is directly assigned in a debug core instance below + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxslide_int; + //wire [0:0] ch0_rxslide_int = 1'b0; //commented by EBSM - controlled by word aligner + //assign rxslide_int[0:0] = ch0_rxslide_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txpippmen_int; + //wire [0:0] ch0_txpippmen_int = 1'b0; //commented by EBSM - controlled by phase aligner + //assign txpippmen_int[0:0] = ch0_txpippmen_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txpippmovrden_int; + //wire [0:0] ch0_txpippmovrden_int = 1'b0; //commented by EBSM - controlled by phase aligner + //assign txpippmovrden_int[0:0] = ch0_txpippmovrden_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txpippmpd_int; + //wire [0:0] ch0_txpippmpd_int = 1'b0; //commented by EBSM - controlled by phase aligner + //assign txpippmpd_int[0:0] = ch0_txpippmpd_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txpippmsel_int; + //wire [0:0] ch0_txpippmsel_int = 1'b0; //commented by EBSM - controlled by phase aligner + //assign txpippmsel_int[0:0] = ch0_txpippmsel_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [4:0] txpippmstepsize_int; + //wire [4:0] ch0_txpippmstepsize_int = 5'b00000; //commented by EBSM - controlled by phase aligner + //assign txpippmstepsize_int[4:0] = ch0_txpippmstepsize_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txpolarity_int; + wire [0:0] ch0_txpolarity_int = 1'b0; + assign txpolarity_int[0:0] = ch0_txpolarity_int; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txprbsforceerr_int; + // This vector is not sliced because it is directly assigned in a debug core instance below + + //-------------------------------------------------------------------------------------------------------------------- + wire [3:0] txprbssel_int; + // This vector is not sliced because it is directly assigned in a debug core instance below + + //-------------------------------------------------------------------------------------------------------------------- + wire [15:0] drpdo_int; + wire [15:0] ch0_drpdo_int; + assign ch0_drpdo_int = drpdo_int[15:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] drprdy_int; + wire [0:0] ch0_drprdy_int; + assign ch0_drprdy_int = drprdy_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxcdrlock_int; + wire [0:0] ch0_rxcdrlock_int; + assign ch0_rxcdrlock_int = rxcdrlock_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxoutclk_int; + wire [0:0] ch0_rxoutclk_int; + assign ch0_rxoutclk_int = rxoutclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxoutclkpcs_int; + wire [0:0] ch0_rxoutclkpcs_int; + assign ch0_rxoutclkpcs_int = rxoutclkpcs_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxpmaresetdone_int; + wire [0:0] ch0_rxpmaresetdone_int; + assign ch0_rxpmaresetdone_int = rxpmaresetdone_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxprbserr_int; + wire [0:0] ch0_rxprbserr_int; + assign ch0_rxprbserr_int = rxprbserr_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxprbslocked_int; + wire [0:0] ch0_rxprbslocked_int; + assign ch0_rxprbslocked_int = rxprbslocked_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] rxrecclkout_int; + wire [0:0] ch0_rxrecclkout_int; + assign ch0_rxrecclkout_int = rxrecclkout_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [1:0] txbufstatus_int; + wire [1:0] ch0_txbufstatus_int; + assign ch0_txbufstatus_int = txbufstatus_int[1:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txoutclk_int; + wire [0:0] ch0_txoutclk_int; + assign ch0_txoutclk_int = txoutclk_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txoutclkfabric_int; + wire [0:0] ch0_txoutclkfabric_int; + assign ch0_txoutclkfabric_int = txoutclkfabric_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txoutclkpcs_int; + wire [0:0] ch0_txoutclkpcs_int; + assign ch0_txoutclkpcs_int = txoutclkpcs_int[0:0]; + + //-------------------------------------------------------------------------------------------------------------------- + wire [0:0] txpmaresetdone_int; + wire [0:0] ch0_txpmaresetdone_int; + assign ch0_txpmaresetdone_int = txpmaresetdone_int[0:0]; + + + // =================================================================================================================== + // BUFFERS + // =================================================================================================================== + + // Buffer the hb_gtwiz_reset_all_in input and logically combine it with the internal signal from the example + // initialization block as well as the VIO-sourced reset + wire hb_gtwiz_reset_all_vio_int; + wire hb_gtwiz_reset_all_buf_int; + wire hb_gtwiz_reset_all_init_int; + wire hb_gtwiz_reset_all_int; + + IBUF ibuf_hb_gtwiz_reset_all_inst ( + .I (hb_gtwiz_reset_all_in), + .O (hb_gtwiz_reset_all_buf_int) + ); + + assign hb_gtwiz_reset_all_int = hb_gtwiz_reset_all_buf_int || hb_gtwiz_reset_all_init_int || hb_gtwiz_reset_all_vio_int; + + // Globally buffer the free-running input clock + wire hb_gtwiz_reset_clk_freerun_buf_int; + + //Modified by EBSM - use differential buffer for free-running clock + // IBUFDS: Differential Input Buffer + // UltraScale + // Xilinx HDL Libraries Guide, version 2014.1 + IBUFDS #( + .DQS_BIAS("FALSE") // (FALSE, TRUE) + ) + IBUFDS_inst ( + .O(hb_gtwiz_reset_clk_freerun_buf_int), // 1-bit output: Buffer output + .I(hb_gtwiz_reset_clk_freerun_in_p), // 1-bit input: Diff_p buffer input (connect directly to top-level port) + .IB(hb_gtwiz_reset_clk_freerun_in_n) // 1-bit input: Diff_n buffer input (connect directly to top-level port) + ); + // End of IBUFDS_inst instantiation + + //BUFG bufg_clk_freerun_inst ( + // .I (hb_gtwiz_reset_clk_freerun_in), + // .O (hb_gtwiz_reset_clk_freerun_buf_int) + //); + + // Instantiate a differential reference clock buffer for each reference clock differential pair in this configuration, + // and assign the single-ended output of each differential reference clock buffer to the appropriate PLL input signal + + // Differential reference clock buffer for MGTREFCLK0_X0Y3 + wire mgtrefclk0_x0y3_int; + + IBUFDS_GTE3 #( + .REFCLK_EN_TX_PATH (1'b0), + .REFCLK_HROW_CK_SEL (2'b00), + .REFCLK_ICNTL_RX (2'b00) + ) IBUFDS_GTE3_MGTREFCLK0_X0Y3_INST ( + .I (mgtrefclk0_x0y3_p), + .IB (mgtrefclk0_x0y3_n), + .CEB (1'b0), + .O (mgtrefclk0_x0y3_int), + .ODIV2 () + ); + + // Differential reference clock buffer for MGTREFCLK1_X0Y2 + wire mgtrefclk1_x0y2_int; + + IBUFDS_GTE3 #( + .REFCLK_EN_TX_PATH (1'b0), + .REFCLK_HROW_CK_SEL (2'b00), + .REFCLK_ICNTL_RX (2'b00) + ) IBUFDS_GTE3_MGTREFCLK1_X0Y2_INST ( + .I (mgtrefclk1_x0y2_p), + .IB (mgtrefclk1_x0y2_n), + .CEB (1'b0), + .O (mgtrefclk1_x0y2_int), + .ODIV2 () + ); + + assign cm0_gtrefclk00_int = mgtrefclk1_x0y2_int; + assign cm0_gtrefclk01_int = mgtrefclk0_x0y3_int; + + // Instantiate a differential recovered clock output buffer for each channel which drives out its recovered clock + + // Differential recovered clock buffer for channel X0Y11 + OBUFDS_GTE3 #( + .REFCLK_EN_TX_PATH (1'b1), + .REFCLK_ICNTL_TX (5'b00111) + ) OBUFDS_GTE3_CHX0Y11_INST ( + .O (rxrecclkout_chx0y11_p), + .OB (rxrecclkout_chx0y11_n), + .CEB (1'b0), + .I (ch0_rxrecclkout_int) + ); + + // Added by EBSM - output the recovered clock which goes through the fabric + wire rxusrclk_oddr; + + // ODDRE1: Dedicated Dual Data Rate (DDR) Output Register + // Ultrascale + // Xilinx HDL Libraries Guide, version 2014.1 + ODDRE1 #( + .IS_C_INVERTED(1'b0) // Optional inversion for C + ,.IS_D1_INVERTED(1'b0) // Optional inversion for D1 + ,.IS_D2_INVERTED(1'b0) // Optional inversion for D2 + ,.SRVAL(1'b0) // Initializes the ODDRE1 Flip-Flops to the specified value ('0', '1') + ) + ODDRE1_rxusrclk_inst( + .Q(rxusrclk_oddr) // 1-bit output: Data output to IOB + ,.C(hb0_gtwiz_userclk_rx_usrclk2_int[0]) // 1-bit input: High-speed clock input + ,.D1(1'b0) // 1-bit input: Parallel data input 1 + ,.D2(1'b1) // 1-bit input: Parallel data input 2 + ,.SR(1'b0) // 1-bit input: Active High Async Reset + ); + // End of ODDRE1_rxoutclk_inst instantiation + + assign rxusrclk = rxusrclk_oddr; + + //// OBUFDS: Differential Output Buffer + //// UltraScale + //// Xilinx HDL Libraries Guide, version 2014.1 + //OBUFDS #( + //) OBUFDS_rxoutclk_inst ( + // .O(rxusrclk_p), // 1-bit output: Diff_p output (connect directly to top-level port) + // .OB(rxusrclk_n), // 1-bit output: Diff_n output (connect directly to top-level port) + // .I(rxusrclk_oddr) // 1-bit input: Buffer input + // ); + // End of OBUFDS_rxoutclk_inst instantiation + + + // =================================================================================================================== + // USER CLOCKING RESETS + // =================================================================================================================== + + // The TX user clocking helper block should be held in reset until the clock source of that block is known to be + // stable. The following assignment is an example of how that stability can be determined, based on the selected TX + // user clock source. Replace the assignment with the appropriate signal or logic to achieve that behavior as needed. + assign hb0_gtwiz_userclk_tx_reset_int = ~(&txpmaresetdone_int); + + // The RX user clocking helper block should be held in reset until the clock source of that block is known to be + // stable. The following assignment is an example of how that stability can be determined, based on the selected RX + // user clock source. Replace the assignment with the appropriate signal or logic to achieve that behavior as needed. + assign hb0_gtwiz_userclk_rx_reset_int = ~(&rxpmaresetdone_int); + + + // =================================================================================================================== + // BUFFER BYPASS CONTROLLER RESETS + // =================================================================================================================== + + // The RX buffer bypass controller helper block should be held in reset until the RX user clocking network helper + // block which drives it is active + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_reset_synchronizer reset_synchronizer_gtwiz_buffbypass_rx_reset_inst ( + .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), + .rst_in (~hb0_gtwiz_userclk_rx_active_int), + .rst_out (hb0_gtwiz_buffbypass_rx_reset_int) + ); + + + // =================================================================================================================== + // PRBS STIMULUS, CHECKING, AND LINK MANAGEMENT + // =================================================================================================================== + + // PRBS stimulus + // ------------------------------------------------------------------------------------------------------------------- + //The block gtwizard_ultrascale_0_example_stimulus_raw was modified by EBSM - 30b prbs generation + // PRBS-based data stimulus module for transceiver channel 0 + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_stimulus_raw example_stimulus_inst0 ( + .gtwiz_reset_all_in (hb_gtwiz_reset_all_int), + .gtwiz_userclk_tx_usrclk2_in (hb0_gtwiz_userclk_tx_usrclk2_int), + .gtwiz_userclk_tx_active_in (tx_aligned), //hb0_gtwiz_userclk_tx_active_int), + .txdata_out (hb0_gtwiz_userdata_tx_int[31:2]) + ); + + assign hb0_gtwiz_userdata_tx_int[1:0] = 2'b10; // 2b header for word alignment + + // PRBS checking + // ------------------------------------------------------------------------------------------------------------------- + + // Declare a signal vector of PRBS match indicators, with one indicator bit per transceiver channel + wire [0:0] prbs_match_int; + + //The block gtwizard_ultrascale_0_example_checking_raw was modified by EBSM - 30b prbs checking + // PRBS-based data checking module for transceiver channel 0 + gtwizard_ultrascale_0_example_checking_raw example_checking_inst0 ( + .gtwiz_reset_all_in (hb_gtwiz_reset_all_int || ~hb0_gtwiz_reset_rx_done_int || ~hb0_gtwiz_buffbypass_rx_done_int), + .gtwiz_userclk_rx_usrclk2_in (hb0_gtwiz_userclk_rx_usrclk2_int), + .gtwiz_userclk_rx_active_in (hb0_gtwiz_userclk_rx_active_int), + .rxdata_in (hb0_gtwiz_userdata_rx_int[31:2]), + .prbs_match_out (prbs_match_int[0]) + ); + + // Added Rx word alignment by EBSM + // Rx word alignment + wire reset_word_aligner = ~(gtwiz_reset_rx_done_int && gtwiz_buffbypass_rx_done_int); + wire header; + assign header = hb0_gtwiz_userdata_rx_int[1] & (~hb0_gtwiz_userdata_rx_int[0]); + wire rx_locked; + wire rx_reset_from_word_aligner; + + rx_word_aligner rx_word_aligner_inst + ( + .clk_rxusr_i(hb0_gtwiz_userclk_rx_usrclk2_int) + ,.reset_i(reset_word_aligner) + ,.enable_i(1'b1) + ,.header_i(header) + ,.rx_locked_o(rx_locked) + ,.rx_slide_o(rxslide_int[0]) + ,.clk_sys_i(hb_gtwiz_reset_clk_freerun_buf_int) + ,.rx_reset_o(rx_reset_from_word_aligner) + ); + + assign rx_locked_out = rx_locked; + + // PRBS match and related link management + // ------------------------------------------------------------------------------------------------------------------- + + // Perform a bitwise NAND of all PRBS match indicators, creating a combinatorial indication of any PRBS mismatch + // across all transceiver channels + wire prbs_error_any_async = ~(&prbs_match_int); + wire prbs_error_any_sync; + + // Synchronize the PRBS mismatch indicator the free-running clock domain, using a reset synchronizer with asynchronous + // reset and synchronous removal + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_reset_synchronizer reset_synchronizer_prbs_match_all_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .rst_in (prbs_error_any_async), + .rst_out(prbs_error_any_sync) + ); + + // Implement an example link status state machine using a simple leaky bucket mechanism. The link status indicates + // the continual PRBS match status to both the top-level observer and the initialization state machine, while being + // tolerant of occasional bit errors. This is an example and can be modified as necessary. + localparam ST_LINK_DOWN = 1'b0; + localparam ST_LINK_UP = 1'b1; + reg sm_link = ST_LINK_DOWN; + reg [6:0] link_ctr = 7'd0; + + always @(posedge hb_gtwiz_reset_clk_freerun_buf_int) begin + case (sm_link) + // The link is considered to be down when the link counter initially has a value less than 67. When the link is + // down, the counter is incremented on each cycle where all PRBS bits match, but reset whenever any PRBS mismatch + // occurs. When the link counter reaches 67, transition to the link up state. + ST_LINK_DOWN: begin + if (prbs_error_any_sync !== 1'b0 ) begin + link_ctr <= 7'd0; + end + else begin + if (link_ctr < 7'd67) + link_ctr <= link_ctr + 7'd1; + else + sm_link <= ST_LINK_UP; + end + end + + // When the link is up, the link counter is decreased by 34 whenever any PRBS mismatch occurs, but is increased by + // only 1 on each cycle where all PRBS bits match, up to its saturation point of 67. If the link counter reaches + // 0 (including rollover protection), transition to the link down state. + ST_LINK_UP: begin + if (prbs_error_any_sync !== 1'b0) begin + if (link_ctr > 7'd33) begin + link_ctr <= link_ctr - 7'd34; + if (link_ctr == 7'd34) + sm_link <= ST_LINK_DOWN; + end + else begin + link_ctr <= 7'd0; + sm_link <= ST_LINK_DOWN; + end + end + else begin + if (link_ctr < 7'd67) + link_ctr <= link_ctr + 7'd1; + end + end + + endcase + end + + // Synchronize the latched link down reset input and the VIO-driven signal into the free-running clock domain + wire link_down_latched_reset_vio_int; + wire link_down_latched_reset_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_link_down_latched_reset_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (link_down_latched_reset_in || link_down_latched_reset_vio_int), + .o_out (link_down_latched_reset_sync) + ); + + // Reset the latched link down indicator when the synchronized latched link down reset signal is high. Otherwise, set + // the latched link down indicator upon losing link. This indicator is available for user reference. + always @(posedge hb_gtwiz_reset_clk_freerun_buf_int) begin + if (link_down_latched_reset_sync) + link_down_latched_out <= 1'b0; + else if (!sm_link) + link_down_latched_out <= 1'b1; + end + + // Assign the link status indicator to the top-level two-state output for user reference + assign link_status_out = sm_link; + + // =================================================================================================================== + // TX_PHASE_ALIGNER signals - EBSM + // =================================================================================================================== + wire tx_aligned; // The Transmitter reset is only considered to be finished once the phase aligner has finished alignment + wire reset_tx_phase_aligner; + assign reset_tx_phase_aligner = ~gtwiz_reset_tx_done_vio_sync; + + wire [6:0] tx_pi_phase; + wire [31:0] tx_fifo_fill_pd; + + wire tx_ui_align_calib; + wire [6:0] tx_pi_phase_calib; + wire [31:0] tx_fifo_fill_pd_max; + wire tx_fine_realign; + + assign gtwiz_reset_tx_pll_and_datapath_int[0:0] = hb0_gtwiz_reset_tx_pll_and_datapath_int; + + assign tx_aligned_out = tx_aligned; + + // =================================================================================================================== + // INITIALIZATION + // =================================================================================================================== + + // Declare the receiver reset signals that interface to the reset controller helper block. For this configuration, + // which uses different PLL types for transmitter and receiver, the "reset RX datapath" feature is not used. + wire hb_gtwiz_reset_rx_pll_and_datapath_int; + wire hb_gtwiz_reset_rx_datapath_int = 1'b0; + + // Declare signals which connect the VIO instance to the initialization module for debug purposes + wire init_done_int; + wire [3:0] init_retry_ctr_int; + + // Combine the receiver reset signals form the initialization module and the VIO to drive the appropriate reset + // controller helper block reset input + wire hb_gtwiz_reset_rx_pll_and_datapath_vio_int; + wire hb_gtwiz_reset_rx_datapath_vio_int; + wire hb_gtwiz_reset_rx_pll_and_datapath_init_int; + + assign hb_gtwiz_reset_rx_pll_and_datapath_int = hb_gtwiz_reset_rx_pll_and_datapath_init_int || hb_gtwiz_reset_rx_pll_and_datapath_vio_int || rx_reset_from_word_aligner; //Included also reset from word aligner (EBSM) + + // The block gtwizard_ultrascale_0_example_init and its connections were modified by EBSM + // The example initialization module interacts with the reset controller helper block and other example design logic + // to retry failed reset attempts in order to mitigate bring-up issues such as initially-unavilable reference clocks + // or data connections. It also resets the receiver in the event of link loss in an attempt to regain link, so please + // note the possibility that this behavior can have the effect of overriding or disturbing user-provided inputs that + // destabilize the data stream. It is a demonstration only and can be modified to suit your system needs. + gtwizard_ultrascale_0_example_init example_init_inst ( + .clk_freerun_in (hb_gtwiz_reset_clk_freerun_buf_int), + .reset_all_in (hb_gtwiz_reset_all_int), + .tx_init_done_in (tx_aligned),//(gtwiz_reset_tx_done_int), The Transmitter reset is only considered to be finished once the phase aligner has finished alignment + .rx_init_done_in (rx_locked), //(gtwiz_reset_rx_done_int && gtwiz_buffbypass_rx_done_int), The receiver is only considered locked when the word aligner has finished + .rx_data_good_in (1'b1), //(sm_link), do not reset if seeing prbs errors + .reset_all_out (hb_gtwiz_reset_all_init_int), + .reset_rx_out (hb_gtwiz_reset_rx_pll_and_datapath_init_int), + .init_done_out (init_done_int), + .retry_ctr_out (init_retry_ctr_int) + ); + + + // =================================================================================================================== + // VIO FOR HARDWARE BRING-UP AND DEBUG + // =================================================================================================================== + + // Synchronize txpmaresetdone into the free-running clock domain for VIO usage + wire [0:0] txpmaresetdone_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txpmaresetdone_0_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (txpmaresetdone_int[0]), + .o_out (txpmaresetdone_vio_sync[0]) + ); + + // Synchronize rxpmaresetdone into the free-running clock domain for VIO usage + wire [0:0] rxpmaresetdone_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxpmaresetdone_0_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (rxpmaresetdone_int[0]), + .o_out (rxpmaresetdone_vio_sync[0]) + ); + + // Synchronize gtwiz_reset_tx_done into the free-running clock domain for VIO usage + wire [0:0] gtwiz_reset_tx_done_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_gtwiz_reset_tx_done_0_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (gtwiz_reset_tx_done_int[0]), + .o_out (gtwiz_reset_tx_done_vio_sync[0]) + ); + + // Synchronize gtwiz_reset_rx_done into the free-running clock domain for VIO usage + wire [0:0] gtwiz_reset_rx_done_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_gtwiz_reset_rx_done_0_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (gtwiz_reset_rx_done_int[0]), + .o_out (gtwiz_reset_rx_done_vio_sync[0]) + ); + + // Synchronize gtwiz_buffbypass_rx_done into the free-running clock domain for VIO usage + wire [0:0] gtwiz_buffbypass_rx_done_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_rx_done_0_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (gtwiz_buffbypass_rx_done_int[0]), + .o_out (gtwiz_buffbypass_rx_done_vio_sync[0]) + ); + + // Synchronize gtwiz_buffbypass_rx_error into the free-running clock domain for VIO usage + wire [0:0] gtwiz_buffbypass_rx_error_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_gtwiz_buffbypass_rx_error_0_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (gtwiz_buffbypass_rx_error_int[0]), + .o_out (gtwiz_buffbypass_rx_error_vio_sync[0]) + ); + + // Synchronize rxprbserr into the free-running clock domain for VIO usage + wire [0:0] rxprbserr_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbserr_0_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (rxprbserr_int[0]), + .o_out (rxprbserr_vio_sync[0]) + ); + + // Synchronize rxprbslocked into the free-running clock domain for VIO usage + wire [0:0] rxprbslocked_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbslocked_0_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (rxprbslocked_int[0]), + .o_out (rxprbslocked_vio_sync[0]) + ); + + // Synchronize rx_locked into the free-running clock domain for VIO usage (EBSM) + wire [0:0] rx_locked_vio_sync; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rx_locked_inst ( + .clk_in (hb_gtwiz_reset_clk_freerun_buf_int), + .i_in (rx_locked), + .o_out (rx_locked_vio_sync[0]) + ); + + // Synchronize txprbssel into the TXUSRCLK2 clock domain from VIO usage + wire [3:0] txprbssel_vio_async; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbssel_0_inst ( + .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), + .i_in (txprbssel_vio_async[0]), + .o_out (txprbssel_int[0]) + ); + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbssel_1_inst ( + .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), + .i_in (txprbssel_vio_async[1]), + .o_out (txprbssel_int[1]) + ); + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbssel_2_inst ( + .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), + .i_in (txprbssel_vio_async[2]), + .o_out (txprbssel_int[2]) + ); + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbssel_3_inst ( + .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), + .i_in (txprbssel_vio_async[3]), + .o_out (txprbssel_int[3]) + ); + + // Synchronize rxprbssel into the RXUSRCLK2 clock domain from VIO usage + wire [3:0] rxprbssel_vio_async; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbssel_0_inst ( + .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), + .i_in (rxprbssel_vio_async[0]), + .o_out (rxprbssel_int[0]) + ); + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbssel_1_inst ( + .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), + .i_in (rxprbssel_vio_async[1]), + .o_out (rxprbssel_int[1]) + ); + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbssel_2_inst ( + .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), + .i_in (rxprbssel_vio_async[2]), + .o_out (rxprbssel_int[2]) + ); + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbssel_3_inst ( + .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), + .i_in (rxprbssel_vio_async[3]), + .o_out (rxprbssel_int[3]) + ); + + // Synchronize txprbsforceerr into the TXUSRCLK2 clock domain from VIO usage + wire [0:0] txprbsforceerr_vio_async; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_txprbsforceerr_0_inst ( + .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), + .i_in (txprbsforceerr_vio_async[0]), + .o_out (txprbsforceerr_int[0]) + ); + + // Synchronize rxprbscntreset into the RXUSRCLK2 clock domain from VIO usage + wire [0:0] rxprbscntreset_vio_async; + + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_rxprbscntreset_0_inst ( + .clk_in (hb0_gtwiz_userclk_rx_usrclk2_int), + .i_in (rxprbscntreset_vio_async[0]), + .o_out (rxprbscntreset_int[0]) + ); + + // Synchronize tx_data_sel into the TXUSRCLK2 clock domain from VIO usage (EBSM) + wire tx_data_sel_vio_async; + (* DONT_TOUCH = "TRUE" *) + gtwizard_ultrascale_0_example_bit_synchronizer bit_synchronizer_vio_tx_data_sel_0_inst ( + .clk_in (hb0_gtwiz_userclk_tx_usrclk2_int), + .i_in (tx_data_sel_vio_async), + .o_out (tx_data_sel) + ); + // Instantiate the VIO IP core for hardware bring-up and debug purposes, connecting relevant debug and analysis + // signals which have been enabled during Wizard IP customization. This initial set of connected signals is + // provided as a convenience and example, but more or fewer ports can be used as needed; simply re-customize and + // re-generate the VIO instance, then connect any exposed signals that are needed. Signals which are synchronous to + // clocks other than the free-running clock will require synchronization. For usage, refer to Vivado Design Suite + // User Guide: Programming and Debugging (UG908) + gtwizard_ultrascale_0_vio_0 gtwizard_ultrascale_0_vio_0_inst ( + .clk (hb_gtwiz_reset_clk_freerun_buf_int) + ,.probe_in0 (link_status_out) + ,.probe_in1 (link_down_latched_out) + ,.probe_in2 (init_done_int) + ,.probe_in3 (init_retry_ctr_int) + ,.probe_in4 (txpmaresetdone_vio_sync) + ,.probe_in5 (rxpmaresetdone_vio_sync) + ,.probe_in6 (gtwiz_reset_tx_done_vio_sync) + ,.probe_in7 (gtwiz_reset_rx_done_vio_sync) + ,.probe_in8 (gtwiz_buffbypass_rx_done_vio_sync) + ,.probe_in9 (gtwiz_buffbypass_rx_error_vio_sync) + ,.probe_in10 (rxprbserr_vio_sync) + ,.probe_in11 (rxprbslocked_vio_sync) + + ,.probe_in12 (tx_aligned) //Added for the phase aligner exdsg (EBSM) + ,.probe_in13 (tx_pi_phase) //Added for the phase aligner exdsg (EBSM) + ,.probe_in14 (tx_fifo_fill_pd) //Added for the phase aligner exdsg (EBSM) + ,.probe_in15 (rx_locked_vio_sync) //Added to check receiver is properly word locked (EBSM) + + ,.probe_out0 (hb_gtwiz_reset_all_vio_int) + ,.probe_out1 (hb0_gtwiz_reset_tx_pll_and_datapath_int) + ,.probe_out2 (hb0_gtwiz_reset_tx_datapath_int) + ,.probe_out3 (hb_gtwiz_reset_rx_pll_and_datapath_vio_int) + ,.probe_out4 (hb_gtwiz_reset_rx_datapath_vio_int) + ,.probe_out5 (link_down_latched_reset_vio_int) + ,.probe_out6 (rxcdrreset_int) + ,.probe_out7 (loopback_int) + ,.probe_out8 (txprbssel_vio_async) + ,.probe_out9 (rxprbssel_vio_async) + ,.probe_out10 (txprbsforceerr_vio_async) + ,.probe_out11 (rxprbscntreset_vio_async) + + ,.probe_out12 (tx_ui_align_calib) //Added for the phase aligner exdsg (EBSM) + ,.probe_out13 (tx_fine_realign) //Added for the phase aligner exdsg (EBSM) + ,.probe_out14 (tx_pi_phase_calib) //Added for the phase aligner exdsg (EBSM) + ,.probe_out15 (tx_fifo_fill_pd_max) //Added for the phase aligner exdsg (EBSM) + ,.probe_out16 (tx_data_sel_vio_async) //Added for the phase aligner exdsg (EBSM) + ); + + // =================================================================================================================== + // EXAMPLE WRAPPER INSTANCE + // =================================================================================================================== + + // Instantiate the example design wrapper, mapping its enabled ports to per-channel internal signals and example + // resources as appropriate + gtwizard_ultrascale_0_example_wrapper example_wrapper_inst ( + .gthrxn_in (gthrxn_int) + ,.gthrxp_in (gthrxp_int) + ,.gthtxn_out (gthtxn_int) + ,.gthtxp_out (gthtxp_int) + ,.gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_int) + ,.gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_int) + ,.gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_int) + ,.gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_int) + ,.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_int) + ,.gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_int) + ,.gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_int) + ,.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_int) + ,.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_int) + ,.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_int) + ,.gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_int) + ,.gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_int) + ,.gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_int) + ,.gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_int) + ,.gtwiz_reset_clk_freerun_in ({1{hb_gtwiz_reset_clk_freerun_buf_int}}) + ,.gtwiz_reset_all_in ({1{hb_gtwiz_reset_all_int}}) + ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_int) + ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_int) + ,.gtwiz_reset_rx_pll_and_datapath_in ({1{hb_gtwiz_reset_rx_pll_and_datapath_int}}) + ,.gtwiz_reset_rx_datapath_in ({1{hb_gtwiz_reset_rx_datapath_int}}) + ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_int) + ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_int) + ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_int) + ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_int) + ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_int) + ,.gtrefclk00_in (gtrefclk00_int) + ,.gtrefclk01_in (gtrefclk01_int) + ,.qpll0outclk_out (qpll0outclk_int) + ,.qpll0outrefclk_out (qpll0outrefclk_int) + ,.qpll1outclk_out (qpll1outclk_int) + ,.qpll1outrefclk_out (qpll1outrefclk_int) + ,.drpaddr_in (drpaddr_int) + ,.drpclk_in (hb_gtwiz_reset_clk_freerun_buf_int)//(drpclk_int) (EBSM) + ,.drpdi_in (drpdi_int) + ,.drpen_in (drpen_int) + ,.drpwe_in (drpwe_int) + ,.loopback_in (loopback_int) + ,.rxcdrreset_in (rxcdrreset_int) + ,.rxpolarity_in (rxpolarity_int) + ,.rxprbscntreset_in (rxprbscntreset_int) + ,.rxprbssel_in (rxprbssel_int) + ,.rxslide_in (rxslide_int) + ,.txpippmen_in (txpippmen_int) + ,.txpippmovrden_in (txpippmovrden_int) + ,.txpippmpd_in (txpippmpd_int) + ,.txpippmsel_in (txpippmsel_int) + ,.txpippmstepsize_in (txpippmstepsize_int) + ,.txpolarity_in (txpolarity_int) + ,.txprbsforceerr_in (txprbsforceerr_int) + ,.txprbssel_in (txprbssel_int) + ,.drpdo_out (drpdo_int) + ,.drprdy_out (drprdy_int) + ,.rxcdrlock_out (rxcdrlock_int) + ,.rxoutclk_out (rxoutclk_int) + ,.rxoutclkpcs_out (rxoutclkpcs_int) + ,.rxpmaresetdone_out (rxpmaresetdone_int) + ,.rxprbserr_out (rxprbserr_int) + ,.rxprbslocked_out (rxprbslocked_int) + ,.rxrecclkout_out (rxrecclkout_int) + ,.txbufstatus_out (txbufstatus_int) + ,.txoutclk_out (txoutclk_int) + ,.txoutclkfabric_out (txoutclkfabric_int) + ,.txoutclkpcs_out (txoutclkpcs_int) + ,.txpmaresetdone_out (txpmaresetdone_int) +); + + wire tx_ps_done; + + //============================================================================== + // Phase aligner instantiation + //============================================================================== + tx_phase_aligner tx_phase_aligner_inst( + //============================================================================== + // User control/monitor ports + //============================================================================== + // Clock / reset + .clk_sys_i(hb_gtwiz_reset_clk_freerun_buf_int) // system clock input + ,.reset_i(reset_tx_phase_aligner) // active high sync. reset + + // Top level interface + ,.tx_aligned_o(tx_aligned) // Use it as a reset for the user transmitter logic + + // Config (for different flavours) + ,.tx_pi_phase_calib_i(tx_pi_phase_calib) // previous calibrated tx pi phase (tx_pi_phase_o after first reset calibration) + ,.tx_ui_align_calib_i(tx_ui_align_calib) // align with previous calibrated tx pi phase + ,.tx_fifo_fill_pd_max_i(tx_fifo_fill_pd_max) // phase detector accumulated max output, sets precision of phase detector + // this is supposedly a static signal, this block shall be reset whenever this signal changes + // the time for each phase detection after a clear is given by tx_fifo_fill_pd_max_i * PERIOD_clk_txusr_i + ,.tx_fine_realign_i(tx_fine_realign) + + // It is only valid to re-shift clock once aligned (tx_aligned_o = '1') + ,.ps_strobe_i(1'b0) + ,.ps_inc_ndec_i(1'b0) + ,.ps_phase_step_i(4'h0) + ,.ps_done_o(tx_ps_done) + + // Tx PI phase value + ,.tx_pi_phase_o(tx_pi_phase) // phase shift accumulated + + // Tx fifo fill level phase detector + ,.tx_fifo_fill_pd_o(tx_fifo_fill_pd) // phase detector output, when aligned this value should be close to (0x2_0000) + + //============================================================================== + // MGT ports + //============================================================================== + ,.clk_txusr_i(hb0_gtwiz_userclk_tx_usrclk2_int) // txusr2clk + // Tx fifo fill level - see Xilinx transceiver User Guide for more information + ,.tx_fifo_fill_level_i(txbufstatus_int[0]) // connect to txbufstatus[0] + + // Transmitter PI ports - see Xilinx transceiver User Guide for more information + // obs1: all txpi ports shall be connected to the transceiver even when using this block in DRP-mode + ,.txpippmen_o(txpippmen_int) // enable tx phase interpolator controller + ,.txpippmovrden_o(txpippmovrden_int) // enable DRP control of tx phase interpolator + ,.txpippmsel_o(txpippmsel_int) // set to 1 when using tx pi ppm controler + ,.txpippmpd_o(txpippmpd_int) // power down transmitter phase interpolator + ,.txpippmstepsize_o(txpippmstepsize_int) // sets step size and direction of phase shift with port control PI code stepping mode + + // DRP interface - see Xilinx transceiver User Guide for more information + // obs2: connect clk_sys_i to drpclk + // obs3: if using this block in port-mode, DRP output can be left floating and input connected to '0' + ,.drpaddr_o(drpaddr_int) // For devices with a 10-bit DRP address interface, connect MSB to '0' + ,.drpen_o(drpen_int) // DRP enable transaction + ,.drpdi_o(drpdi_int) // DRP data write + ,.drprdy_i(drprdy_int) // DRP finished transaction + ,.drpdo_i(drpdo_int) // DRP data read; not used nowadays, write only interface + ,.drpwe_o(drpwe_int) // DRP write enable + ); + +endmodule diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper.v b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper.v new file mode 100644 index 0000000..1773680 --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper.v @@ -0,0 +1,238 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design wrapper module instantiates the core and any helper blocks which the user chose to exclude from +// the core, connects them as appropriate, and maps enabled ports +// ===================================================================================================================== + +module gtwizard_ultrascale_0_example_wrapper ( + input wire [0:0] gthrxn_in + ,input wire [0:0] gthrxp_in + ,output wire [0:0] gthtxn_out + ,output wire [0:0] gthtxp_out + ,input wire [0:0] gtwiz_userclk_tx_reset_in + ,output wire [0:0] gtwiz_userclk_tx_srcclk_out + ,output wire [0:0] gtwiz_userclk_tx_usrclk_out + ,output wire [0:0] gtwiz_userclk_tx_usrclk2_out + ,output wire [0:0] gtwiz_userclk_tx_active_out + ,input wire [0:0] gtwiz_userclk_rx_reset_in + ,output wire [0:0] gtwiz_userclk_rx_srcclk_out + ,output wire [0:0] gtwiz_userclk_rx_usrclk_out + ,output wire [0:0] gtwiz_userclk_rx_usrclk2_out + ,output wire [0:0] gtwiz_userclk_rx_active_out + ,input wire [0:0] gtwiz_buffbypass_rx_reset_in + ,input wire [0:0] gtwiz_buffbypass_rx_start_user_in + ,output wire [0:0] gtwiz_buffbypass_rx_done_out + ,output wire [0:0] gtwiz_buffbypass_rx_error_out + ,input wire [0:0] gtwiz_reset_clk_freerun_in + ,input wire [0:0] gtwiz_reset_all_in + ,input wire [0:0] gtwiz_reset_tx_pll_and_datapath_in + ,input wire [0:0] gtwiz_reset_tx_datapath_in + ,input wire [0:0] gtwiz_reset_rx_pll_and_datapath_in + ,input wire [0:0] gtwiz_reset_rx_datapath_in + ,output wire [0:0] gtwiz_reset_rx_cdr_stable_out + ,output wire [0:0] gtwiz_reset_tx_done_out + ,output wire [0:0] gtwiz_reset_rx_done_out + ,input wire [31:0] gtwiz_userdata_tx_in + ,output wire [31:0] gtwiz_userdata_rx_out + ,input wire [0:0] gtrefclk00_in + ,input wire [0:0] gtrefclk01_in + ,output wire [0:0] qpll0outclk_out + ,output wire [0:0] qpll0outrefclk_out + ,output wire [0:0] qpll1outclk_out + ,output wire [0:0] qpll1outrefclk_out + ,input wire [8:0] drpaddr_in + ,input wire [0:0] drpclk_in + ,input wire [15:0] drpdi_in + ,input wire [0:0] drpen_in + ,input wire [0:0] drpwe_in + ,input wire [2:0] loopback_in + ,input wire [0:0] rxcdrreset_in + ,input wire [0:0] rxpolarity_in + ,input wire [0:0] rxprbscntreset_in + ,input wire [3:0] rxprbssel_in + ,input wire [0:0] rxslide_in + ,input wire [0:0] txpippmen_in + ,input wire [0:0] txpippmovrden_in + ,input wire [0:0] txpippmpd_in + ,input wire [0:0] txpippmsel_in + ,input wire [4:0] txpippmstepsize_in + ,input wire [0:0] txpolarity_in + ,input wire [0:0] txprbsforceerr_in + ,input wire [3:0] txprbssel_in + ,output wire [15:0] drpdo_out + ,output wire [0:0] drprdy_out + ,output wire [0:0] rxcdrlock_out + ,output wire [0:0] rxoutclk_out + ,output wire [0:0] rxoutclkpcs_out + ,output wire [0:0] rxpmaresetdone_out + ,output wire [0:0] rxprbserr_out + ,output wire [0:0] rxprbslocked_out + ,output wire [0:0] rxrecclkout_out + ,output wire [1:0] txbufstatus_out + ,output wire [0:0] txoutclk_out + ,output wire [0:0] txoutclkfabric_out + ,output wire [0:0] txoutclkpcs_out + ,output wire [0:0] txpmaresetdone_out +); + + + // =================================================================================================================== + // PARAMETERS AND FUNCTIONS + // =================================================================================================================== + + // Declare and initialize local parameters and functions used for HDL generation + localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000; + `include "gtwizard_ultrascale_0_example_wrapper_functions.vh" + localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(11); + localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(11); + + + // =================================================================================================================== + // HELPER BLOCKS + // =================================================================================================================== + + // Any helper blocks which the user chose to exclude from the core will appear below. In addition, some signal + // assignments related to optionally-enabled ports may appear below. + + wire [0:0] txoutclk_int; + + // Required assignment to expose the TXOUTCLK port per user request + assign txoutclk_out = txoutclk_int; + + wire [0:0] rxoutclk_int; + + // Required assignment to expose the RXOUTCLK port per user request + assign rxoutclk_out = rxoutclk_int; + wire [0:0] rxcdrlock_int; + + // Required assignment to expose the RXCDRLOCK port per user request + assign rxcdrlock_out = rxcdrlock_int; + + + // =================================================================================================================== + // CORE INSTANCE + // =================================================================================================================== + + // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate + gtwizard_ultrascale_0 gtwizard_ultrascale_0_inst ( + .gthrxn_in (gthrxn_in) + ,.gthrxp_in (gthrxp_in) + ,.gthtxn_out (gthtxn_out) + ,.gthtxp_out (gthtxp_out) + ,.gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in) + ,.gtwiz_userclk_tx_srcclk_out (gtwiz_userclk_tx_srcclk_out) + ,.gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out) + ,.gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out) + ,.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out) + ,.gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in) + ,.gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out) + ,.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out) + ,.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out) + ,.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out) + ,.gtwiz_buffbypass_rx_reset_in (gtwiz_buffbypass_rx_reset_in) + ,.gtwiz_buffbypass_rx_start_user_in (gtwiz_buffbypass_rx_start_user_in) + ,.gtwiz_buffbypass_rx_done_out (gtwiz_buffbypass_rx_done_out) + ,.gtwiz_buffbypass_rx_error_out (gtwiz_buffbypass_rx_error_out) + ,.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in) + ,.gtwiz_reset_all_in (gtwiz_reset_all_in) + ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in) + ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in) + ,.gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in) + ,.gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in) + ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out) + ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out) + ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out) + ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in) + ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out) + ,.gtrefclk00_in (gtrefclk00_in) + ,.gtrefclk01_in (gtrefclk01_in) + ,.qpll0outclk_out (qpll0outclk_out) + ,.qpll0outrefclk_out (qpll0outrefclk_out) + ,.qpll1outclk_out (qpll1outclk_out) + ,.qpll1outrefclk_out (qpll1outrefclk_out) + ,.drpaddr_in (drpaddr_in) + ,.drpclk_in (drpclk_in) + ,.drpdi_in (drpdi_in) + ,.drpen_in (drpen_in) + ,.drpwe_in (drpwe_in) + ,.loopback_in (loopback_in) + ,.rxcdrreset_in (rxcdrreset_in) + ,.rxpolarity_in (rxpolarity_in) + ,.rxprbscntreset_in (rxprbscntreset_in) + ,.rxprbssel_in (rxprbssel_in) + ,.rxslide_in (rxslide_in) + ,.txpippmen_in (txpippmen_in) + ,.txpippmovrden_in (txpippmovrden_in) + ,.txpippmpd_in (txpippmpd_in) + ,.txpippmsel_in (txpippmsel_in) + ,.txpippmstepsize_in (txpippmstepsize_in) + ,.txpolarity_in (txpolarity_in) + ,.txprbsforceerr_in (txprbsforceerr_in) + ,.txprbssel_in (txprbssel_in) + ,.drpdo_out (drpdo_out) + ,.drprdy_out (drprdy_out) + ,.rxcdrlock_out (rxcdrlock_int) + ,.rxoutclk_out (rxoutclk_int) + ,.rxoutclkpcs_out (rxoutclkpcs_out) + ,.rxpmaresetdone_out (rxpmaresetdone_out) + ,.rxprbserr_out (rxprbserr_out) + ,.rxprbslocked_out (rxprbslocked_out) + ,.rxrecclkout_out (rxrecclkout_out) + ,.txbufstatus_out (txbufstatus_out) + ,.txoutclk_out (txoutclk_int) + ,.txoutclkfabric_out (txoutclkfabric_out) + ,.txoutclkpcs_out (txoutclkpcs_out) + ,.txpmaresetdone_out (txpmaresetdone_out) +); + +endmodule diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper_functions.vh b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper_functions.vh new file mode 100644 index 0000000..66767a7 --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper_functions.vh @@ -0,0 +1,241 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +// ===================================================================================================================== +// This file contains functions available for example design HDL generation as required +// ===================================================================================================================== + +// Function to populate a bit mapping of enabled transceiver common blocks to transceiver quads +function [47:0] f_pop_cm_en ( + input integer in_null +); +begin : main_f_pop_cm_en + integer i; + reg [47:0] tmp; + for (i = 0; i < 192; i = i + 4) begin + if ((P_CHANNEL_ENABLE[i] == 1'b1) || + (P_CHANNEL_ENABLE[i+1] == 1'b1) || + (P_CHANNEL_ENABLE[i+2] == 1'b1) || + (P_CHANNEL_ENABLE[i+3] == 1'b1)) + tmp[i/4] = 1'b1; + else + tmp[i/4] = 1'b0; + end + f_pop_cm_en = tmp; +end +endfunction + +// Function to calculate a pointer to a master channel's packed index +function integer f_calc_pk_mc_idx ( + input integer idx_mc +); +begin : main_f_calc_pk_mc_idx + integer i, j; + integer tmp; + j = 0; + for (i = 0; i < 192; i = i + 1) begin + if (P_CHANNEL_ENABLE[i] == 1'b1) begin + if (i == idx_mc) + tmp = j; + else + j = j + 1; + end + end + f_calc_pk_mc_idx = tmp; +end +endfunction + +// Function to calculate the upper bound of a transceiver common-related signal within a packed vector, for a given +// signal width and unpacked common index +function integer f_ub_cm ( + input integer width, + input integer index +); +begin : main_f_ub_cm + integer i, j; + j = 0; + for (i = 0; i <= index; i = i + 4) begin + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + end + f_ub_cm = (width * j) - 1; +end +endfunction + +// Function to calculate the lower bound of a transceiver common-related signal within a packed vector, for a given +// signal width and unpacked common index +function integer f_lb_cm ( + input integer width, + input integer index +); +begin : main_f_lb_cm + integer i, j; + j = 0; + for (i = 0; i < index; i = i + 4) begin + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + end + f_lb_cm = (width * j); +end +endfunction + +// Function to calculate the packed vector index of a transceiver common, provided the packed vector index of the +// associated transceiver channel +function integer f_idx_cm ( + input integer index +); +begin : main_f_idx_cm + integer i, j, k, flag, result; + j = 0; + k = 0; + flag = 0; + for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) begin + k = k + 1; + if (P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+2] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+1] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i] == 1'b1) + j = j + 1; + end + + if (j >= (index + 1)) begin + flag = 1; + result = k; + end + end + f_idx_cm = result - 1; +end +endfunction + +// Function to calculate the packed vector index of the upper bound transceiver channel which is associated with the +// provided transceiver common packed vector index +function integer f_idx_ch_ub ( + input integer index +); +begin : main_f_idx_ch_ub + integer i, j, k, flag, result; + j = 0; + k = 0; + flag = 0; + for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin + + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) begin + k = k + 1; + if (P_CHANNEL_ENABLE[i] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+1] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+2] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + if (k == index + 1) begin + flag = 1; + result = j; + end + end + + end + f_idx_ch_ub = result - 1; +end +endfunction + +// Function to calculate the packed vector index of the lower bound transceiver channel which is associated with the +// provided transceiver common packed vector index +function integer f_idx_ch_lb ( + input integer index +); +begin : main_f_idx_ch_lb + integer i, j, k, flag, result; + j = 0; + k = 0; + flag = 0; + for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin + + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) begin + k = k + 1; + if (k == index + 1) begin + flag = 1; + result = j + 1; + end + else begin + if (P_CHANNEL_ENABLE[i] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+1] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+2] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + end + end + + end + f_idx_ch_lb = result - 1; +end +endfunction diff --git a/source/synth/imports/example_design/gtwizard_ultrascale_0_prbs_any.v b/source/synth/imports/example_design/gtwizard_ultrascale_0_prbs_any.v new file mode 100644 index 0000000..c7e4f7b --- /dev/null +++ b/source/synth/imports/example_design/gtwizard_ultrascale_0_prbs_any.v @@ -0,0 +1,195 @@ +//------------------------------------------------------------------------------ +// File Name: PRBS_ANY.v +// Version: 1.0 +// Date: 6-jul-10 +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + +//-------------------------------------------------------------------------- +// DESCRIPTION +//-------------------------------------------------------------------------- +// This module generates or check a PRBS pattern. The following table shows how +// to set the PARAMETERS for compliance to ITU-T Recommendation O.150 Section 5. +// +// When the CHK_MODE is "false", it uses a LFSR strucure to generate the +// PRBS pattern. +// When the CHK_MODE is "true", the incoming data are loaded into prbs registers +// and compared with the locally generated PRBS +// +//-------------------------------------------------------------------------- +// PARAMETERS +//-------------------------------------------------------------------------- +// CHK_MODE : true => check mode +// false => generate mode +// INV_PATTERN : true : invert prbs pattern +// in "generate mode" the generated prbs is inverted bit-wise at outputs +// in "check mode" the input data are inverted before processing +// POLY_LENGHT : length of the polynomial (= number of shift register stages) +// POLY_TAP : intermediate stage that is xor-ed with the last stage to generate to next prbs bit +// NBITS : bus size of DATA_IN and DATA_OUT +// +//-------------------------------------------------------------------------- +// NOTES +//-------------------------------------------------------------------------- +// +// +// Set paramaters to the following values for a ITU-T compliant PRBS +//------------------------------------------------------------------------------ +// POLY_LENGHT POLY_TAP INV_PATTERN || nbr of bit seq. max 0 feedback +// || stages length sequence stages +//------------------------------------------------------------------------------ +// 7 6 false || 7 127 6 ni 6, 7 (*) +// 9 5 false || 9 511 8 ni 5, 9 +// 11 9 false || 11 2047 10 ni 9,11 +// 15 14 true || 15 32767 15 i 14,15 +// 20 3 false || 20 1048575 19 ni 3,20 +// 23 18 true || 23 8388607 23 i 18,23 +// 29 27 true || 29 536870911 29 i 27,29 +// 31 28 true || 31 2147483647 31 i 28,31 +// +// i=inverted, ni= non-inverted +// (*) non standard +//---------------------------------------------------------------------------- +// +// In the generated parallel PRBS, LSB is the first generated bit, for example +// if the PRBS serial stream is : 000001111011... then +// the generated PRBS with a parallelism of 3 bit becomes: +// data_out(2) = 0 1 1 1 ... +// data_out(1) = 0 0 1 1 ... +// data_out(0) = 0 0 1 0 ... +// In the received parallel PRBS, LSB is oldest bit received +// +// RESET pin is not needed for power-on reset : all registers are properly inizialized +// in the source code. +// +//------------------------------------------------------------------------------ +// PINS DESCRIPTION +//------------------------------------------------------------------------------ +// +// RST : in : syncronous reset active high +// CLK : in : system clock +// DATA_IN : in : inject error (in generate mode) +// data to be checked (in check mode) +// EN : in : enable/pause pattern generation/check +// DATA_OUT : out: generated prbs pattern (in generate mode) +// error found (in check mode) +// +//------------------------------------------------------------------------------------------------- +// History: +// Version : 1.0 +// Date : 6-jul-10 +// Author : Daniele Riccardi +// Description: First release +// +// Subsequent cosmetic modifications by Xilinx for integration into the UltraScale FPGAs +// Transceivers Wizard example design. +//------------------------------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module gtwizard_ultrascale_0_prbs_any(RST, CLK, DATA_IN, EN, DATA_OUT); + + //-------------------------------------------- + // Configuration parameters + //-------------------------------------------- + parameter CHK_MODE = 0; + parameter INV_PATTERN = 0; + parameter POLY_LENGHT = 31; + parameter POLY_TAP = 3; + parameter NBITS = 16; + + //-------------------------------------------- + // Input/Outputs + //-------------------------------------------- + + input wire RST; + input wire CLK; + input wire [NBITS - 1:0] DATA_IN; + input wire EN; + output reg [NBITS - 1:0] DATA_OUT = {NBITS{1'b1}}; + + //-------------------------------------------- + // Internal variables + //-------------------------------------------- + + wire [1:POLY_LENGHT] prbs[NBITS:0]; + wire [NBITS - 1:0] data_in_i; + wire [NBITS - 1:0] prbs_xor_a; + wire [NBITS - 1:0] prbs_xor_b; + wire [NBITS:1] prbs_msb; + reg [1:POLY_LENGHT]prbs_reg = {(POLY_LENGHT){1'b1}}; + + //-------------------------------------------- + // Implementation + //-------------------------------------------- + + assign data_in_i = INV_PATTERN == 0 ? DATA_IN : ( ~DATA_IN); + assign prbs[0] = prbs_reg; + + genvar I; + generate for (I=0; IDependencies:\n +--! +--! +--! References:\n +--! \n +--! +--! +--! Modified by:\n +--! Author: Eduardo Brandao de Souza Mendes +------------------------------------------------------------------------------- +--! \n\nLast changes:\n +--! 22\05\2018 - EBSM - Created\n +--! +------------------------------------------------------------------------------- +--! @todo - \n +--! \n +-- +------------------------------------------------------------------------------- + +--============================================================================== +--! Entity declaration for rx_word_aligner +--============================================================================== +entity rx_word_aligner is + generic( + g_HDR_GOOD_TO_LOCK : integer := 64; --! number of consecutive good headers to lock + g_HDR_BAD_TO_UNLOCK : integer := 4; --! number of consecutive bad headers to unlock + g_DATA_WORD_WIDTH : integer := 32; --! rx data word width + g_SKIP_PULSE_DURATION : integer := 2; --! duration of the skip pulse (for K7, it is one clock cycle, for KU it is 2) + g_WAIT_BETWEEN_SKIP : integer := 32 --! minimum number of clock cycles (rxusrclk2) to wait between rx_slide pulses + ); + port ( + clk_rxusr_i : in std_logic; --! rxusrclk2 + reset_i : in std_logic; --! active high sync. reset + enable_i : in std_logic; --! control scheduling + header_i : in std_logic; --! input header + rx_locked_o : out std_logic; --! rx locked was achieved + rx_slide_o : out std_logic; --! rx slide used for alignment + + clk_sys_i : in std_logic; --! clock system input (free-running) + rx_reset_o : out std_logic --! reset transceiver to avoid odd bitslip number + ); +end rx_word_aligner; + +--============================================================================== +-- architecture declaration +--============================================================================== + +architecture rtl of rx_word_aligner is + + --! Function declaration + function fcn_reduce_or(arg: std_logic_vector) return std_logic is + variable result: std_logic; + begin + result := '0'; + for i in arg'range loop + result := result or arg(i); + end loop; + return result; + end; + + function fcn_log2( input:integer ) return integer is +  variable temp,log:integer; +  begin +  temp:=input; +  log:=0; +  while (temp /= 0) loop +   temp:=temp/2; +   log:=log+1; +   end loop; +   return log; +  end function fcn_log2; + + --! Constant declaration + constant c_MAX_SKIP_WAIT : integer := g_SKIP_PULSE_DURATION+g_WAIT_BETWEEN_SKIP; + + --! Signal declaration + + -- FSM HDR-framing + -- principle: + -- HUNT : received a correct HDR -> GOING_SYNC + -- received a wrong HDR -> SKIP CYCLE + -- SKIP CYCLE : slips a bit and then -> SKIP_CYCLE_WAIT + -- SKIP_CYCLE_WAIT : waits the slip to be finished and then -> HUNT + -- GOING_SYNC : received a consecutive number of correct HDR and bit slip is even -> SYNC + -- received a consecutive number of correct HDR and bit slip is odd -> RESET_RX + -- received a wrong HDR -> HUNT + -- RESET_RX : basically waits forever (until the reset takes effect) + -- SYNC : received a wrong HDR -> GOING_HUNT + -- GOING_HUNT : received a consecutive number of wrong HDR -> HUNT + -- received a correct HDR -> SYNC + type t_FRAMING_FSM_STATE is (HUNT, SKIP_CYCLE, SKIP_CYCLE_WAIT, GOING_SYNC, SYNC, RESET_RX, GOING_HUNT); + signal framing_state : t_FRAMING_FSM_STATE; + + signal correct_hdr_count : integer range 0 to (g_HDR_GOOD_TO_LOCK + 1); + signal wrong_hdr_count : integer range 0 to (g_HDR_BAD_TO_UNLOCK + 1); + + signal skip_cycle_pipe : std_logic_vector(g_SKIP_PULSE_DURATION-1 downto 0); + signal skip_cycle_s : std_logic; + signal skip_cycle_cntr : integer range 0 to g_DATA_WORD_WIDTH-1; + signal skip_wait_cntr : integer range 0 to c_MAX_SKIP_WAIT; + + signal reset_rx_latch : std_logic; + signal reset_rx_sys_meta : std_logic; + signal reset_rx_sys_r : std_logic; + signal reset_rx_sys_r2 : std_logic; + signal reset_rx_pipe : std_logic_vector(4 downto 0); + +begin + + --============================================================================ + -- Process p_hdr_framing_fsm + --! FSM for HDR-framing locking procedure + --! read: enable_i, header_i, correct_hdr_count, wrong_hdr_count\n + --! write: -\n + --! r/w: framing_state \n + --============================================================================ + p_hdr_framing_fsm : process(clk_rxusr_i, reset_i) -- asynchronous + begin + if(reset_i = '1') then + framing_state <= HUNT; + elsif(clk_rxusr_i'event and clk_rxusr_i='1') then + case framing_state is + when HUNT => + if(enable_i='1') then + if(header_i='1') then + framing_state <= GOING_SYNC; + else + framing_state <= SKIP_CYCLE; + end if; + end if; + + when SKIP_CYCLE => + framing_state <= SKIP_CYCLE_WAIT; + + when SKIP_CYCLE_WAIT => + if(skip_wait_cntr >= g_WAIT_BETWEEN_SKIP) then + framing_state <= HUNT; + end if; + + when GOING_SYNC => + if(enable_i='1') then + if(correct_hdr_count >= g_HDR_GOOD_TO_LOCK) then + if( to_unsigned(skip_cycle_cntr,fcn_log2(g_DATA_WORD_WIDTH))(0) = '0' ) then + framing_state <= SYNC; + else + framing_state <= RESET_RX; + end if; + elsif(header_i='0') then + framing_state <= HUNT; + end if; + end if; + + when SYNC => + if(enable_i='1') then + if(header_i='0') then + framing_state <= GOING_HUNT; + end if; + end if; + + when RESET_RX => + framing_state <= RESET_RX; + + when GOING_HUNT => + if(enable_i='1') then + if(wrong_hdr_count >= g_HDR_BAD_TO_UNLOCK) then + framing_state <= HUNT; + elsif(header_i='1') then + framing_state <= SYNC; + end if; + end if; + + when others => framing_state <= HUNT; + end case; + end if; + end process p_hdr_framing_fsm; + + --============================================================================ + -- Process p_hdr_framing_fsm_aux + --! counters for consecutive correct/wrong HDR frame + --! read: clk_i, reset_i, nibble_sent_i, framing_state\n + --! write: - \n + --! r/w: correct_hdr_count, wrong_hdr_count \n + --============================================================================ + p_hdr_framing_fsm_aux : process(clk_rxusr_i) + begin + if(clk_rxusr_i'event and clk_rxusr_i='1') then + if(reset_i='1') then + correct_hdr_count <= 0; + wrong_hdr_count <= 0; + elsif(enable_i='1') then + if(framing_state=GOING_HUNT) then + if(header_i='0') then + wrong_hdr_count <= wrong_hdr_count + 1; + end if; + else + wrong_hdr_count <= 0; + end if; + + if(framing_state=GOING_SYNC) then + if(header_i='1') then + correct_hdr_count <= correct_hdr_count + 1; + end if; + else + correct_hdr_count <= 0; + end if; + end if; + end if; + end process p_hdr_framing_fsm_aux; + + --============================================================================ + -- Process p_skip_cycle + --! skip cycle related functions (counters, pulse generation) + --! read: framing_state\n + --! write: - \n + --! r/w: skip_cycle_cntr, skip_wait_cntr, skip_cycle_pipe, skip_cycle_s \n + --============================================================================ + p_skip_cycle : process(clk_rxusr_i) + begin + if(clk_rxusr_i'event and clk_rxusr_i='1') then + -- skip_cycle (rx_slide) generation + if(framing_state = SKIP_CYCLE) then + skip_cycle_pipe(0) <= '1'; + else + skip_cycle_pipe(0) <= '0'; + end if; + skip_cycle_pipe(skip_cycle_pipe'left downto 1) <= skip_cycle_pipe(skip_cycle_pipe'left - 1 downto 0); + + skip_cycle_s <= fcn_reduce_or(skip_cycle_pipe); + + -- skip_cycle counter to keep track of even/odd bitslip + -- the author of the code is aware that a single bit here is needed but in future it might be interesting to know how many skips were issued + if(reset_i='1') then + skip_cycle_cntr <= 0; + elsif(framing_state = SKIP_CYCLE) then + if(skip_cycle_cntr < g_DATA_WORD_WIDTH-1) then + skip_cycle_cntr <= skip_cycle_cntr + 1; + else + skip_cycle_cntr <= 0; + end if; + end if; + + -- wait between skip pulses counter + if(framing_state = SKIP_CYCLE_WAIT) then + if(skip_wait_cntr < c_MAX_SKIP_WAIT) then + skip_wait_cntr <= skip_wait_cntr + 1; + end if; + else + skip_wait_cntr <= 0; + end if; + + end if; + end process p_skip_cycle; + rx_slide_o <= skip_cycle_s; + + -- create the reset latched whose rising edge will be used in the clk sys domain + p_reset_rx : process(clk_rxusr_i) + begin + if(clk_rxusr_i'event and clk_rxusr_i='1') then + if(framing_state = RESET_RX) then + reset_rx_latch <= '1'; + else + reset_rx_latch <= '0'; + end if; + end if; + end process p_reset_rx; + + -- reset is issued with the clk_sys_i (free-running) to ensure stability + p_reset_sync : process(clk_sys_i) + begin + if(clk_sys_i'event and clk_sys_i='1') then + reset_rx_sys_meta <= reset_rx_latch; + reset_rx_sys_r <= reset_rx_sys_meta; + reset_rx_sys_r2 <= reset_rx_sys_r; + if(reset_rx_sys_r = '1' and reset_rx_sys_r2 = '0') then + reset_rx_pipe(0) <= '1'; + else + reset_rx_pipe(0) <= '0'; + end if; + reset_rx_pipe(reset_rx_pipe'left downto 1) <= reset_rx_pipe(reset_rx_pipe'left-1 downto 0); + rx_reset_o <= fcn_reduce_or(reset_rx_pipe); + end if; + end process p_reset_sync; + + + -- rx locked condition + p_rx_locked : process(clk_rxusr_i, reset_i) + begin + if(reset_i='1') then + rx_locked_o <= '0'; + elsif(clk_rxusr_i'event and clk_rxusr_i='1') then + if(framing_state = SYNC or framing_state = GOING_HUNT) then + rx_locked_o <= '1'; + else + rx_locked_o <= '0'; + end if; + end if; + end process p_rx_locked; + +end architecture rtl; +--============================================================================== +-- architecture end +--============================================================================== diff --git a/source/synth/ip/gtwizard_ultrascale_0.xcix b/source/synth/ip/gtwizard_ultrascale_0.xcix new file mode 100644 index 0000000..d238259 Binary files /dev/null and b/source/synth/ip/gtwizard_ultrascale_0.xcix differ diff --git a/source/synth/ip/gtwizard_ultrascale_0_vio_0.xcix b/source/synth/ip/gtwizard_ultrascale_0_vio_0.xcix new file mode 100644 index 0000000..a922a85 Binary files /dev/null and b/source/synth/ip/gtwizard_ultrascale_0_vio_0.xcix differ diff --git a/tx_aligner_proj.tcl b/tx_aligner_proj.tcl new file mode 100644 index 0000000..f34258e --- /dev/null +++ b/tx_aligner_proj.tcl @@ -0,0 +1,344 @@ +#***************************************************************************************** +# Vivado (TM) v2019.1.3 (64-bit) +# +# tx_aligner_proj.tcl: Tcl script for re-creating project 'tx_aligner_proj' +# +# Generated by Vivado on Sat Jan 30 15:36:01 +0100 2021 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (tx_aligner_proj.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# +# +# 3. The following remote source files that were added to the original project:- +# +# "C:/GIT/tx_phase_aligner/source/synth/ip/gtwizard_ultrascale_0/gtwizard_ultrascale_0.xci" +# "C:/GIT/tx_phase_aligner/source/synth/ip/gtwizard_ultrascale_0_vio_0/gtwizard_ultrascale_0_vio_0.xci" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_example_bit_synchronizer.v" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_example_checking_raw.v" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_example_init.v" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_example_reset_synchronizer.v" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_example_stimulus_raw.v" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper_functions.vh" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper.v" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_prbs_any.v" +# "C:/GIT/tx_phase_aligner/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/rx_word_aligner.vhd" +# "C:/GIT/tx_phase_aligner/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd" +# "C:/GIT/tx_phase_aligner/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd" +# "C:/GIT/tx_phase_aligner/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd" +# "C:/GIT/tx_phase_aligner/source/synth/imports/example_design/gtwizard_ultrascale_0_example_top.v" +# "C:/GIT/tx_phase_aligner/source/constrs/imports/example_design/gtwizard_ultrascale_0_example_top.xdc" +# "C:/GIT/tx_phase_aligner/source/sim/imports/example_design/gtwizard_ultrascale_0_example_top_sim.v" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "tx_aligner_proj" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "tx_aligner_proj.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/tx_aligner_proj"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xcku040-ffva1156-2-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "xilinx.com:kcu105:part0:1.1" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "kcu105" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "generate_ip_upgrade_log" -value "0" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "target_language" -value "VHDL" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/source/synth/ip/gtwizard_ultrascale_0/gtwizard_ultrascale_0.xci"] \ + [file normalize "${origin_dir}/source/synth/ip/gtwizard_ultrascale_0_vio_0/gtwizard_ultrascale_0_vio_0.xci"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_example_bit_synchronizer.v"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_example_checking_raw.v"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_example_init.v"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_example_reset_synchronizer.v"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_example_stimulus_raw.v"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper_functions.vh"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper.v"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_prbs_any.v"] \ + [file normalize "${origin_dir}/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/rx_word_aligner.vhd"] \ + [file normalize "${origin_dir}/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd"] \ + [file normalize "${origin_dir}/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd"] \ + [file normalize "${origin_dir}/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd"] \ + [file normalize "${origin_dir}/source/synth/imports/example_design/gtwizard_ultrascale_0_example_top.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property "top" "gtwizard_ultrascale_0_example_top" $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/source/synth/ip/gtwizard_ultrascale_0/gtwizard_ultrascale_0.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/source/synth/ip/gtwizard_ultrascale_0_vio_0/gtwizard_ultrascale_0_vio_0.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +set file "$origin_dir/source/synth/imports/example_design/gtwizard_ultrascale_0_example_wrapper_functions.vh" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "Verilog Header" -objects $file_obj + +set file "$origin_dir/source/synth/imports/design_tx_aligner/fifo_fill_level_acc.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/synth/imports/example_design/rx_word_aligner.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/synth/imports/design_tx_aligner/tx_phase_aligner.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/synth/imports/design_tx_aligner/tx_phase_aligner_fsm.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/synth/imports/design_tx_aligner/tx_pi_ctrl.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "gtwizard_ultrascale_0_example_top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/source/constrs/imports/example_design/gtwizard_ultrascale_0_example_top.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/source/constrs/imports/example_design/gtwizard_ultrascale_0_example_top.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +set files [list \ + [file normalize "${origin_dir}/source/sim/imports/example_design/gtwizard_ultrascale_0_example_top_sim.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "gtwizard_ultrascale_0_example_top_sim" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xcku040-ffva1156-2-e -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2016" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xcku040-ffva1156-2-e -flow {Vivado Implementation 2016} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2016" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:tx_aligner_proj" + + +# ---------------------- Synthesis -> P&R ----------------------- +update_compile_order -fileset sources_1 +launch_runs impl_1 -to_step write_bitstream -jobs 4 +wait_on_run impl_1 + +puts "INFO: Compilled project tx_aligner_proj" + +# ------------------ post synthesis simulation ------------------ +generate_target Simulation [get_files $origin_dir/synth/ip/gtwizard_ultrascale_0/gtwizard_ultrascale_0.xci] +export_ip_user_files -of_objects [get_files $origin_dir/synth/ip/gtwizard_ultrascale_0/gtwizard_ultrascale_0.xci] -no_script -force -quiet +generate_target Simulation [get_files $origin_dir/synth/ip/gtwizard_ultrascale_0_vio_0/gtwizard_ultrascale_0_vio_0.xci] +export_ip_user_files -of_objects [get_files $origin_dir/synth/ip/gtwizard_ultrascale_0_vio_0/gtwizard_ultrascale_0_vio_0.xci] -no_script -force -quiet +launch_simulation +#launch_simulation -mode post-synthesis -type functional + +# Close if any window is opened +close_wave_config + +# Init simulation with waves to be observed +open_wave_config {./scripts/sim/tx_phase_aligner_simu.wcfg} + +source ./scripts/sim/tx_phase_aligner_simu.tcl \ No newline at end of file diff --git a/tx_phase_aligner_reference_note.pdf b/tx_phase_aligner_reference_note.pdf new file mode 100644 index 0000000..ddf9e70 Binary files /dev/null and b/tx_phase_aligner_reference_note.pdf differ