From: Benedikt Gutsche Date: Wed, 10 Jan 2024 10:32:53 +0000 (+0100) Subject: included core in top-level X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8e4adc4bd1406018ae94899c82c45ee14202d3bb;p=trb5sc.git included core in top-level --- diff --git a/vldb/trb5sc_mimosis.lpf b/vldb/trb5sc_mimosis.lpf new file mode 100644 index 0000000..1407584 --- /dev/null +++ b/vldb/trb5sc_mimosis.lpf @@ -0,0 +1,49 @@ + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + + +BLOCK NET "THE_MIMOSIS/THE_IN/reset_i"; +BLOCK NET "THE_MIMOSIS/THE_WORDS/reset_i"; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/PROC_REGS.add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/add_re*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/CONF*" 20 ns; +MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.control_re*" 20 ns; + +BLOCK PATH TO CELL "THE_MIMOSIS/THE_IN/PROC_REGS.BUS_TX.dat*"; +BLOCK PATH TO CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.BUS_TX.dat*"; diff --git a/vldb/trb5sc_mimosis.prj b/vldb/trb5sc_mimosis.prj new file mode 100644 index 0000000..df0bfb1 --- /dev/null +++ b/vldb/trb5sc_mimosis.prj @@ -0,0 +1,284 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_mimosis" +set_option -resource_sharing false +set_option -vhdl2008 true + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_mimosis.edf" +set_option log_file "workdir/trb5sc_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" + +add_file -vhdl -lib work "./cores/mimosis_inp.vhd" +add_file -vhdl -lib work "./cores/testout.vhd" +add_file -vhdl -lib work "./code/MimosisInput.vhd" +add_file -vhdl -lib work "./code/InputStage.vhd" +add_file -vhdl -lib work "./code/WordAlign.vhd" +add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd" + + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v" +# Choose your SerDes location here +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd" + +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd" + + + + + + + + + +add_file -vhdl -lib work "./trb5sc_mimosis.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/vldb/trb5sc_mimosis.vhd b/vldb/trb5sc_mimosis.vhd new file mode 100644 index 0000000..2560c25 --- /dev/null +++ b/vldb/trb5sc_mimosis.vhd @@ -0,0 +1,511 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_mimosis is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --AddOn + --FE_GPIO : inout std_logic_vector(11 downto 0); + --FE_CLK : out std_logic_vector( 2 downto 1); + --FE_DIFF : inout std_logic_vector(63 downto 0); + --INP : inout std_logic_vector(63 downto 0); + --LED_ADDON : out std_logic_vector(5 downto 0); + LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0); + LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0); + LED_ADDON_RJ : out std_logic_vector(1 downto 0); + SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0); + SFP_ADDON_LOS : in std_logic_vector(1 downto 0); + + RJ : inout std_logic_vector(3 downto 0); + H1 : inout std_logic_vector(4 downto 0); + H2 : inout std_logic_vector(4 downto 0); + H3 : inout std_logic_vector(4 downto 0); + H4 : inout std_logic_vector(4 downto 0); + H5 : inout std_logic_vector(3 downto 0); + H6 : inout std_logic_vector(4 downto 0); + H7 : inout std_logic_vector(4 downto 0); + + PIN : out std_logic_vector(8 downto 1); + + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --GBTSCA + SCA_RX : in std_logic_vector(1 downto 0); + SCA_TX : out std_logic_vector(1 downto 0); + SCA_CLK : out std_logic_vector(1 downto 0); + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); --on v1 only + --COMMON_SDA, COMMON_SCL : inout std_logic + HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + +end entity; + + +architecture arch of trb5sc_mimosis is + + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40, clk_80 : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal external_clock_lock : std_logic := '0'; + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbtcore_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbtcore_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal add_reg : std_logic_vector(31 downto 0); + alias led_off : std_logic is add_reg(0); + + signal out_data : std_logic_vector(15 downto 0); + signal out_i : std_logic_vector( 7 downto 0); + signal inp_i : std_logic_vector( 7 downto 0); + signal gbe_status : std_logic_vector(15 downto 0); + + signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); + signal i2c_reg_2 : std_logic_vector(31 downto 0); + signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); + signal mimosis_scl_drv, mimosis_sda_drv : std_logic; + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + signal counter : unsigned(23 downto 0); + + --signal fwd_dst_mac : std_logic_vector(47 downto 0); + --signal fwd_dst_ip : std_logic_vector(31 downto 0); + --signal fwd_dst_port : std_logic_vector(15 downto 0); + --signal fwd_data : std_logic_vector(7 downto 0); + --signal fwd_datavalid : std_logic; + --signal fwd_sop : std_logic; + --signal fwd_eop : std_logic; + --signal fwd_ready : std_logic; + --signal fwd_full : std_logic; + --signal fwd_length : std_logic_vector(15 downto 0); + --signal fwd_do_send : std_logic; + +begin + + + trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + THE_160_PLL : entity work.pll_200_160 + port map( + CLKI => clk_full_osc, + CLKOP => clk_160, + CLKOS => clk_320, + CLKOS2=> clk_40 + CLKOS3=> clk_80 + ); + + H5(3) <= clk_320; + RJ(0) <= clk_40; + + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => SERDES_NUM, + USE_NEW_ECP5_RESET => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => BROADCAST_BITMASK, + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16, + USE_GBE => USE_GBE + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_125 => CLK_125, + CLEAR_N => GSR_N, + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer, + STATUS_GBE_OUT=> gbe_status + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busmimosis_rx, + BUS_RX(4) => busgbtcore_rx, + -- BUS_RX(4) => busi2c_rx, + -- BUS_RX(5) => busgbeip_rx, + -- BUS_RX(6) => busgbereg_rx, + -- BUS_RX(7) => busfwd_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busmimosis_tx, + BUS_TX(4) => busgbtcore_tx, + -- BUS_TX(4) => busi2c_tx, + -- BUS_TX(5) => busgbeip_tx, + -- BUS_TX(6) => busgbereg_tx, + -- BUS_TX(7) => busfwd_tx, + STAT_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393" + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + --HEADER_IO => open, + HEADER_IO(7) => HDR_IO(6), + HEADER_IO(8) => HDR_IO(7), + ADDITIONAL_REG => add_reg, + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'), + TRIG_GEN_INPUTS => (others => '0'), + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + +--counter <= counter + '1' when rising_edge(clk_sys); +--HDR_IO <= std_logic_vector(counter(15 downto 0)); +--LED <= std_logic_vector(counter(23 downto 16)); + + --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z'; + --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z'; + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + + +--------------------------------------------------------------------------- +-- GBT-SCA +--------------------------------------------------------------------------- + THE_GBT_CORE : entity work.gbt_core + port map( + CLK_sys => clk_sys, + CLK => clk_40, + + RESET => reset_i, + + BUS_RX => busgbtcore_rx, + BUS_TX => busgbtcore_tx, + + ELINK_RX => 0, + ELINK_TX => open + ); + + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9); + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)); + LED_SFP_YELLOW <= not med2int(0).stat_op(8); + LED <= x"FF"; + LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used + LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP) + LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used + LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP) + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used + + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; --for v1 boards + + FLASH_NCS <= flash_ncs_i; + + LED_ADDON_RJ <= "00"; + LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2)); + LED_ADDON_SFP_GREEN(1) <= '0'; + LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); + LED_ADDON_SFP_ORANGE(1) <= '0'; + + +--------------------------------------------------------------------------- +-- GBT Core +--------------------------------------------------------------------------- + THE_GBT_CORE : entity work.gbt_core + port map( + CLK_SYS => clk_sys, + CLK => clk_80, + RESET => reset_i, + + BUS_RX => busgbtcore_rx, + BUS_TX => busgbtcore_tx, + + ELINK_RX => H3(0), + ELINK_TX => H3(2) + ); + + +--------------------------------------------------------------------------- +-- Input stage +--------------------------------------------------------------------------- + THE_MIMOSIS : entity work.MimosisInput + port map( + CLK => clk_160, + CLK_SYS => clk_sys, + RESET => reset_i, + + INPUT => inp_i, + + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + + BUS_RX => busmimosis_rx, + BUS_TX => busmimosis_tx + ); + +-- inp_i <= H2(3 downto 0) & H1(3 downto 0); + inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0); +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + + SFP_ADDON_TX_DIS <= (others => '0'); +end architecture;