From: Tobias Weber <webert@kph.uni-mainz.de>
Date: Wed, 4 Sep 2013 09:28:24 +0000 (+0200)
Subject: Change Clocking
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=8eca045eed81e7a22f19b1ea96ecd03a51de78c6;p=trb3.git

Change Clocking
---

diff --git a/mupix/sources/graycounter.vhd b/mupix/sources/graycounter.vhd
index d33adfa..426da8e 100644
--- a/mupix/sources/graycounter.vhd
+++ b/mupix/sources/graycounter.vhd
@@ -5,7 +5,7 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
 
 
 entity Graycounter is
diff --git a/mupix/sources/injection_generator.vhd b/mupix/sources/injection_generator.vhd
index def3a93..1ebfb1e 100644
--- a/mupix/sources/injection_generator.vhd
+++ b/mupix/sources/injection_generator.vhd
@@ -61,7 +61,7 @@ begin
         counter1 <= counter_from_slv(15 downto 0);
         counter2 <= counter_from_slv(31 downto 16);
       end if;
-      
+
       if(counter1 > x"0000") then
         testpulse1_i <= '1';
         counter1     <= counter1 - 1;
@@ -81,39 +81,39 @@ begin
 
   testpulse_busy <= '1' when testpulse2_i = '1' or testpulse1_i = '1' else '0';
 
-  SLV_HANDLER : process is
+  SLV_HANDLER : process(clk)
   begin
-    wait until rising_edge(clk);
-    SLV_DATA_OUT         <= (others => '0');
-    SLV_UNKNOWN_ADDR_OUT <= '0';
-    SLV_NO_MORE_DATA_OUT <= '0';
-    SLV_ACK_OUT          <= '0';
-    slv_written          <= slv_written(0) & SLV_WRITE_IN;
-
-    if SLV_READ_IN = '1' then
-      if SLV_ADDR_IN = x"0060" then
-        SLV_DATA_OUT(31 downto 16) <= std_logic_vector(counter2);
-        SLV_DATA_OUT(15 downto 0)  <= std_logic_vector(counter1);
-        SLV_ACK_OUT                <= '1';
-      else
-        SLV_UNKNOWN_ADDR_OUT <= '1';
+    if rising_edge(clk) then
+      SLV_DATA_OUT         <= (others => '0');
+      SLV_UNKNOWN_ADDR_OUT <= '0';
+      SLV_NO_MORE_DATA_OUT <= '0';
+      SLV_ACK_OUT          <= '0';
+      slv_written          <= slv_written(0) & SLV_WRITE_IN;
+
+      if SLV_READ_IN = '1' then
+        if SLV_ADDR_IN = x"0060" then
+          SLV_DATA_OUT(31 downto 16) <= std_logic_vector(counter2);
+          SLV_DATA_OUT(15 downto 0)  <= std_logic_vector(counter1);
+          SLV_ACK_OUT                <= '1';
+        else
+          SLV_UNKNOWN_ADDR_OUT <= '1';
+        end if;
       end if;
-    end if;
 
-    if SLV_WRITE_IN = '1' then
-      if SLV_ADDR_IN = x"0060" then
-        if testpulse_busy = '0' then
-          counter_from_slv <= unsigned(SLV_DATA_IN);
-          SLV_ACK_OUT      <= '1';
+      if SLV_WRITE_IN = '1' then
+        if SLV_ADDR_IN = x"0060" then
+          if testpulse_busy = '0' then
+            counter_from_slv <= unsigned(SLV_DATA_IN);
+            SLV_ACK_OUT      <= '1';
+          else
+            SLV_ACK_OUT <= '1';
+          end if;
+          
         else
-          SLV_ACK_OUT <= '1';
+          SLV_UNKNOWN_ADDR_OUT <= '1';
         end if;
-        
-      else
-        SLV_UNKNOWN_ADDR_OUT <= '1';
       end if;
     end if;
-    
   end process SLV_HANDLER;
 
 --Output Signals
diff --git a/mupix/sources/spi_if.vhd b/mupix/sources/spi_if.vhd
index ad73375..537322f 100644
--- a/mupix/sources/spi_if.vhd
+++ b/mupix/sources/spi_if.vhd
@@ -128,45 +128,46 @@ begin
   --x0041: Injection-DACs Register 32 bits
   --x0042: WriteControl Register bit0: Write DACs
   -----------------------------------------------------------------------------
-  SLV_HANDLER : process
+  SLV_HANDLER : process(clk)
   begin  -- process SLV_HANDLER
-    wait until rising_edge(clk);
-    SLV_DATA_OUT         <= (others => '0');
-    SLV_UNKNOWN_ADDR_OUT <= '0';
-    SLV_NO_MORE_DATA_OUT <= '0';
-    SLV_ACK_OUT          <= '0';
-
-    if SLV_READ_IN = '1' then
-      case SLV_ADDR_IN is
-        when x"0040" =>
-          SLV_DATA_OUT <= x"0000" & threshold_reg;
-          SLV_ACK_OUT  <= '1';
-        when x"0041" =>
-          SLV_DATA_OUT <= injection2_reg & injection1_reg;
-          SLV_ACK_OUT  <= '1';
-        when x"0042" =>
-          SLV_DATA_OUT(0) <= wren;
-          SLV_ACK_OUT     <= '1';
-        when others =>
-          SLV_UNKNOWN_ADDR_OUT <= '1';
-      end case;
-    end if;
-
-    if SLV_WRITE_IN = '1' then
-      case SLV_ADDR_IN is
-        when x"0040" =>
-          threshold_reg <= SLV_DATA_IN(15 downto 0);
-          SLV_ACK_OUT  <= '1';
-        when x"0041" =>
-          injection2_reg <= SLV_DATA_IN(31 downto 16);
-          injection1_reg <= SLV_DATA_IN(15 downto 0);
-          SLV_ACK_OUT  <= '1';
-        when x"0042" =>
-          wren <= SLV_DATA_IN(0);
-          SLV_ACK_OUT     <= '1';
-        when others =>
-          SLV_UNKNOWN_ADDR_OUT <= '1';
-      end case;
+    if rising_edge(clk) then
+      SLV_DATA_OUT         <= (others => '0');
+      SLV_UNKNOWN_ADDR_OUT <= '0';
+      SLV_NO_MORE_DATA_OUT <= '0';
+      SLV_ACK_OUT          <= '0';
+
+      if SLV_READ_IN = '1' then
+        case SLV_ADDR_IN is
+          when x"0040" =>
+            SLV_DATA_OUT <= x"0000" & threshold_reg;
+            SLV_ACK_OUT  <= '1';
+          when x"0041" =>
+            SLV_DATA_OUT <= injection2_reg & injection1_reg;
+            SLV_ACK_OUT  <= '1';
+          when x"0042" =>
+            SLV_DATA_OUT(0) <= wren;
+            SLV_ACK_OUT     <= '1';
+          when others =>
+            SLV_UNKNOWN_ADDR_OUT <= '1';
+        end case;
+      end if;
+
+      if SLV_WRITE_IN = '1' then
+        case SLV_ADDR_IN is
+          when x"0040" =>
+            threshold_reg <= SLV_DATA_IN(15 downto 0);
+            SLV_ACK_OUT   <= '1';
+          when x"0041" =>
+            injection2_reg <= SLV_DATA_IN(31 downto 16);
+            injection1_reg <= SLV_DATA_IN(15 downto 0);
+            SLV_ACK_OUT    <= '1';
+          when x"0042" =>
+            wren        <= SLV_DATA_IN(0);
+            SLV_ACK_OUT <= '1';
+          when others =>
+            SLV_UNKNOWN_ADDR_OUT <= '1';
+        end case;
+      end if;
     end if;
   end process SLV_HANDLER;