From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Mon, 18 May 2015 14:10:28 +0000 (+0200)
Subject: Try with 80 again
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=90034d485dc908788b6dbda994f78781dd73314f;p=trb3.git

Try with 80 again
---

diff --git a/ADC/config.vhd b/ADC/config.vhd
index 9204326..6d6bf78 100644
--- a/ADC/config.vhd
+++ b/ADC/config.vhd
@@ -30,7 +30,7 @@ package config is
 --note that not all READOUT_MODEs will lead to timing-error free designs
 --the READOUT_MODE_PSA mode is usually only working with 40MHz
 --the READOUT_MODE_CFD mode is more robust against clock domain crossing issues 
-    constant ADC_SAMPLING_RATE      : integer := 64;
+    constant ADC_SAMPLING_RATE      : integer := 80;
     
 --These are currently used for the included features table only
     constant ADC_BASELINE_LOGIC     : integer := c_YES;