From: Jan Michel Date: Wed, 12 Oct 2016 15:44:53 +0000 (+0200) Subject: Latest version of twepp proceedings X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=903bb5304e565f771ea926750de555b32dee3f23;p=publication.git Latest version of twepp proceedings --- diff --git a/2016-twepp-rich/figures/precision.pdf b/2016-twepp-rich/figures/precision.pdf new file mode 100644 index 0000000..dc1593f Binary files /dev/null and b/2016-twepp-rich/figures/precision.pdf differ diff --git a/2016-twepp-rich/figures/precision.png b/2016-twepp-rich/figures/precision.png new file mode 100644 index 0000000..8e55f15 Binary files /dev/null and b/2016-twepp-rich/figures/precision.png differ diff --git a/2016-twepp-rich/richelectronics.pdf b/2016-twepp-rich/richelectronics.pdf index 36f06ec..18e4c72 100644 Binary files a/2016-twepp-rich/richelectronics.pdf and b/2016-twepp-rich/richelectronics.pdf differ diff --git a/2016-twepp-rich/richelectronics.tex b/2016-twepp-rich/richelectronics.tex index 5810f80..aedda39 100644 --- a/2016-twepp-rich/richelectronics.tex +++ b/2016-twepp-rich/richelectronics.tex @@ -60,7 +60,7 @@ These contain all necessary supply electronics, preamplifiers and FPGA-based TDC -\collaboration[c]{on behalf of the HADES and CBM collaborations} +% \collaboration[c]{on behalf of the HADES and CBM collaborations} % if you write for a special issue this may be useful @@ -76,7 +76,7 @@ These contain all necessary supply electronics, preamplifiers and FPGA-based TDC \section{Introduction} The two heavy ion spectrometers (HADES\cite{hades-web} and CBM\cite{cbm-web}) at the GSI Helmholtz Center for Heavy Ion Research (Darmstadt, Germany) and the FAIR accelerator contain a Ring Imaging Cherenkov (RICH) -detector for particle identification. The existing RICH at the HADES experiment is in operation since the year 2000. Originally, it was built using a CsI photo cathode plane for photon detection. At the moment it is being upgraded with a new MA-PMT readout plane consisting of 428 64-channel PMTs (Hamamatsu H12700). Here, the sensitive area of about $1.3~\rm{m}^2$ will be covered with 28,000 individual PMT cells. +detector for particle identification. The existing RICH at the HADES experiment is in operation since the year 2000. Originally, it was built using a CsI photo cathode plane for photon detection. At the moment it is being upgraded with a new MA-PMT readout plane consisting of 428 64-channel PMTs (Hamamatsu H12700). The sensitive area of about $1.3~\rm{m}^2$ will be covered with 28,000 individual PMT cells. The RICH detector for the CBM experiment will follow the same design, albeit with a larger read-out plane of about twice the size and an even larger sensitive volume. This detector is going to use identical electronics to the HADES setup, with modifications to the read-out system. As a third project, the PANDA experiment, to be built at FAIR during the next years, comprises a DIRC as one of its central parts that is planned to use identical electronics as well. The only component to change is the backplane to cope with the different detector geometry. @@ -87,7 +87,7 @@ As a third project, the PANDA experiment, to be built at FAIR during the next ye \includegraphics[width=.5\textwidth]{../figures/dirich/dirich_system.jpg} \caption{\label{fig:module} The full module, partially equipped. Connecting 6 MA-PMTs and all related electronics on a 10 cm by 15 cm backplane.} \end{figure} -The read-out plane of both RICH detectors is segmented into small modules, consisting of an array of two by three photo multipliers. Such a module measures 10 by 15 cm and houses 384 individual photon detection channels. Scalability dictates that all electronics necessary for this detector are to be integrated on the same footprint. Hence, a modular concept with individual plug-in cards has been developed. The main component is a backplane that connects all cards and is used to route all analog and digital connections as well as power lines. +The read-out plane of both RICH detectors is segmented into small modules, consisting of an array of two by three photo multipliers. Such a module measures 10 by 15 cm and houses 384 individual photon detection channels. Scalability dictates that all electronics necessary for this detector are to be integrated on the same footprint. Hence, a modular concept with individual plug-in cards has been developed. The main component is a backplane that connects all cards and is used to route all analog and digital connections as well as power lines. A partly equipped module is shown in figure~\ref{fig:module}. \subsection{The DiRich Board} @@ -97,7 +97,7 @@ The read-out plane of both RICH detectors is segmented into small modules, consi \caption{\label{fig:dirich} The DiRich board. From left to right: Backplane connector, Amplifiers, TDC-FPGA with threshold filters, auxillary electronics, voltage regulators} \end{figure} -The DiRich board houses all electronics necessary for PMT read-out, from the analog pre-amplifiers to the digital read-out data stream. It is completely based on off-the-shelf components to be independent of hard to acquire ASICs. Each board has 32 input channels, serving one half of a MA-PMT. Both boards have to fit to the back of a single photo multiplier to allow for seamless scaling of the system. The size of each board is $47 \times 100 \times 10~\rm{mm}^3$. To keep the cooling requirements on moderate levels, a low power consumption was one of the key design aspects. +The DiRich board (shown in figure~\ref{fig:dirich}) houses all electronics necessary for PMT read-out, from the analog pre-amplifiers to the digital read-out data stream. It is completely based on off-the-shelf components to be independent of hard to acquire ASICs. Each board has 32 input channels, serving one half of a MA-PMT. Both boards have to fit to the back of a single photo multiplier to allow for seamless scaling of the system. The size of each board is $47 \times 100 \times 10~\rm{mm}^3$. To keep the cooling requirements on moderate levels, a low power consumption was one of the key design aspects. The central part of the system is formed by an FPGA. The FPGA does not only do time-to-digital conversion (described below), but also contains the signal discriminator, threshold generation and the complete DAQ network stack. @@ -121,11 +121,23 @@ The typical input signals from the PMTs has a length of about 2~ns and an amplit The discrete amplification stage is built around a wide-band transistor (BFU760F) as a common emitter amplifier. The typical resistor at the collector has been replaced by an inductor (L77 in figure \ref{fig:analog}) in this circuit for various reasons. First, it allows to use a low operating voltage of only 1.1~V while keeping the static current in the transistor low. Additionally it helps in shaping the output signal as a high-pass filter. The rise time is preserved, but an undershoot is added at the end of the signal to help in returning to the baseline. In the current configuration, the amplifier takes only 50~ns to return to the baseline, avoiding pile-up and wrong time measurements for close signals. Lastly, the undershoot generates a fast crossing of the threshold resulting in a better time-over-threshold measurement. Each channel is galvanically isolated by a small transformer to decouple grounds of the PMT and the amplifier. -The amplification stage has been measured to consume 12~mW per channel. The typical amplification varies between 24 for small signals to 15 for the largest signals of about 40~mV amplitude. This is expected as the total charge the inductor can deliver for each pulse is limited. As the amplitude of the resulting pulse is not measured, there is no negative influence on the accuracy of acquired data. +The amplification stage has been measured to consume 12~mW per channel. The typical amplification varies between 24 for small signals and 15 for the largest signals of 40~mV amplitude. This is expected as the total charge the inductor can deliver for each pulse is limited. As the amplitude of the resulting pulse is not measured, there is no negative influence on the accuracy of acquired data. -The amplified signal with a fast rise time of less than 1~ns is then fed into an input of an LVDS-receiver of the FPGA (LFE5UM-85F-8BG381C). The individual threshold voltage for the discriminator is produced by a delta-sigma DAC output of the FPGA with a simple, two-stage low pass filter connected to the output pin. This DAC reaches a resolution of 38~$\upmu \rm{V}$ and shows no measurable ripple. The switching of the 32 channels is timed such that no two channels switch at the same time and the switching of each channel is limited to few MHz to keep the generated noise level as low as possible. +The amplified signal with a fast rise time of less than 1~ns is then fed into an input of an LVDS receiver of the FPGA (LFE5UM-85F-8BG381C). The individual threshold voltage for the discriminator is produced by a delta-sigma DAC output of the FPGA with a simple, two-stage low pass filter connected to the output pin. This DAC reaches a resolution of 38~$\upmu \rm{V}$ and shows no measurable ripple. The switching of the 32 channels is timed such that no two channels switch at the same time and the switching of each channel is limited to few MHz to keep the generated noise level as low as possible. \subsubsection{Time Measurement} +Time measurement is accomplished by a tapped delay line in the FPGA: The input signal travels along a line of about 300 delay elements (LUTs). If a hit is detected, the delay chain is read-out, decoded and stored in an internal buffer for read-out. + +The intrinsic dead-time of each TDC channel is 15~ns. Hence, to be able to measure both edges of the few nanosecond wide input signals, an internal stretcher in the FPGA is used. The input signal is sent through in-FPGA routing and such delayed by 20 to 30~ns. This gives the TDC time to measure, decode and store the leading edge, before the delayed trailing edge is measured in the same TDC channel as well. The TDC implementation is described in further detail in \cite{tdc}. + + \begin{figure} + \centering % \begin{center}/\end{center} takes some additional vertical space + \includegraphics[width=.7\textwidth]{figures/precision.pdf} + \caption{\label{fig:timing} Measured time precision as difference between two input channels for varying input signal amplitudes. Note that the absolute time shown in the figure is arbitrary.} + \end{figure} + +The actual timing precision of the DiRich module has been tested by supplying two channels of the board with a PMT-like input signal generated in a arbitrary waveform generator. A single output was used and the signal was split passively to guarantee a jitter-free relation between the signals at the two inputs. The measured time difference between the two channels was analyzed, the result is shown in figure~\ref{fig:timing}. Precision stays better than 20~$\rm{ps}_{\rm{rms}}$ for all expected input signals. The lower the signal amplitude, the lower is the timing precision achieved as the signal-to-noise ratio decreases and the slope of the signal gets slower. Nevertheless, even signals with only 1~mV amplitude can be detected with a very good precision of 61~$\rm{ps}_{\rm{rms}}$. + \subsection{Supplementary Boards} \begin{figure}[htbp] @@ -135,9 +147,9 @@ The amplified signal with a fast rise time of less than 1~ns is then fed into an \includegraphics[width=.4\textwidth]{../figures/dirich/dirich_concentrator.jpg} \caption{\label{fig:aux} The two auxillary boards: Power supplies (left) and data concentrator (right)} \end{figure} -The front-end module is complemented by two auxillary boards. The power board houses switiching and linear voltage regulators to provide all necessary supply voltages. Additionally, trigger (reference time) and clock signals are distributed to all front-ends from this board. Two ADC allow for detailed monitoring of all voltages and currents. The board currently forsees two possible powering schemes: A 24~V (8 -- 36~V) input and DC-DC converters provide the most simple external supply. A second option is the direct input of externally regulated low voltages (1.1~V -- 3.3~V). In this case, only linear regulators are active and the electromagnetic noise in the system is reduced. Which of the two options will be used in the final system is currently under investigation. +The front-end module is complemented by two auxillary boards. The power board (figure~\ref{fig:aux}, left side) houses switiching and linear voltage regulators to provide all necessary supply voltages. Additionally, trigger (reference time) and clock signals are distributed to all front-ends from this board. Two ADC allow for detailed monitoring of all voltages and currents. The board currently forsees two possible powering schemes: A 24~V (8 -- 36~V) input and DC-DC converters provide the most simple external supply. A second option is the direct input of externally regulated low voltages (1.1~V -- 3.3~V). In this case, only linear regulators are active and the electromagnetic noise in the system is reduced. Which of the two options will be used in the final system is currently under investigation. -The second board is the data concentrator. Built around a Lattice ECP3 FPGA, it serves as hub to connect all front-end modules to the central DAQ system. In the HADES configuration, this board runs a total of 13 links at 2 GBit/s using the TrbNet protocol. The reference time for all TDC is supplied by an additional LVDS signal generated by the central trigger system (CTS). A trigger request can be generated by the board as well: Every front-end can generate a signal based on a configurable combination of input signals or multiplicities and forward this via the concentrator board to the CTS, which in turn triggers the read-out of the full detector. +The second board is the data concentrator (figure~\ref{fig:aux}, right side). Built around a Lattice ECP3 FPGA, it serves as hub to connect all front-end modules to the central DAQ system. In the HADES configuration, this board runs a total of 13 links at 2 GBit/s using the TrbNet protocol. The reference time for all TDC is supplied by an additional LVDS signal generated by the central trigger system (CTS). A trigger request can be generated by the board as well: Every front-end can generate a signal based on a configurable combination of input signals or multiplicities and forward this via the concentrator board to the CTS, which in turn triggers the read-out of the full detector. In the CBM experiment, data acquisition will not be triggered, but free-streaming. This can be achieved by altering the data processing scheme inside the network and endpoints while keeping the underlying network protocol the same. In this setup, also the clock distribution and fixed-latency synchronization messages will be embedded into the optical data stream to reduce the number of electrical connections inside the detector. @@ -149,7 +161,7 @@ A complete set of data acquisition electronics for single-photon detectors has b \acknowledgments -This work has been supported by BMBF grant 05P15PXFCA. All photographs where kindly provided by G. Otto, GSI. +This work has been supported by BMBF grant 05P15PXFCA. All photographs were kindly provided by G. Otto, GSI.