From: Cahit <c.ugur@gsi.de>
Date: Thu, 11 Dec 2014 16:59:20 +0000 (+0100)
Subject: design table update
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=90715918a5ca0ec6fd57619ba264687af007e0c4;p=trb3web.git

design table update
---

diff --git a/designfiles.htm b/designfiles.htm
index e4392cd..4d6e1b6 100644
--- a/designfiles.htm
+++ b/designfiles.htm
@@ -3,22 +3,167 @@
 <p>The files can be downloaded from this server: <a 
 href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/">jspc29.x-matter.uni-frankfurt.de/bitfiles</a>
 
-<h4>XY AddOn</h4>
+<h4>CTS</h4>
 <table>
 <tr><th>Date
+    <th title="The main clock source for the design: external/internal">Clock
     <th title="Version of the TDC">TDC
-    <th title="Number of channels, not including reference time">Channels
-    <th title="Type: single edge, double edge (in same/alternating channel">Type
-    <th title="Buffer for each channel">Buf/Chan
-    <th title="Total buffer size in words">Buffer
+    <th title="Number of channels, not including reference channel">Channels
+    <th title="Other features of the design">Other1
+    <th title="Other features of the design">Other2
     <th title="Link to bitfile">Bitfile
+    <th title="Few words about the design">Comment
 
-<tr><td>2012-12-11<td>32<td>single edge<td>1.8.9<td>108<td>400<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/super.bit">super.bit</a>
+      <tr>
+	<td>2014.07.02
+	<td>Internal
+	<td>-
+	<td>-
+	<td>-
+	<td>-
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_central_cts_20140702.bit">trb3_central_cts_20140702.bit</a>
+	<td>???latest build???
 
-<tr class="outdated"><td>2012-10-01<td>32<td>single edge<td>1.8.9<td>108<td>400<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/super.bit">super.bit</a>
+      <tr class="outdated">
+	<td>2014.03.28
+	<td>Internal
+	<td>-
+	<td>-
+	<td>-
+	<td>-
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_central_cts_20140328.bit">trb3_central_cts_20140328.bit</a>
+	<td>CTS with MBS input
+      <tr class="outdated">
+	<td>2013.05.08
+	<td>Internal
+	<td>1.5.0
+	<td>4
+	<td>-
+	<td>-
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_central_cts_20130508_a2_tdc15.bit">trb3_central_cts_20130508_a2_tdc15.bit</a>
+	<td>Mainz A2 ETM (instead of MBS)
+</table>
+
+<h4>GbE</h4>
+<table>
+<tr><th>Date
+    <th title="The main clock source for the design: external/internal">Clock
+    <th title="Other features of the design">Other1
+    <th title="Other features of the design">Other2
+    <th title="Link to bitfile">Bitfile
+    <th title="Few words about the design">Comment
+
+      <tr>
+	<td>2014.06.27
+	<td>Internal
+	<td>-
+	<td>-
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_central_gbe2_20140627.bit">trb3_central_gbe2_20140627.bit</a>
+	<td>???latest build???
+
+      <tr class="outdated">
+	<td>2014.06.13
+	<td>Internal
+	<td>-
+	<td>-
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_central_gbe_20140613.bit">trb3_central_gbe_20140613.bit</a>
+	<td>
+</table>
 
+<h4>HUB-Central FPGA</h4>
+<table>
+<tr><th>Date
+    <th title="The main clock source for the design: external/internal">Clock
+    <th title="Other features of the design">Other1
+    <th title="Other features of the design">Other2
+    <th title="Link to bitfile">Bitfile
+    <th title="Few words about the design">Comment
+
+      <tr>
+	<td>2014.11.03
+	<td>External
+	<td>-
+	<td>-
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_central_hub_nogbe_extclock_20141103.bit">trb3_central_hub_nogbe_extclock_20141103.bit</a>
+	<td>
+
+      <tr class="outdated">
+	<td>2013.10.15
+	<td>Internal
+	<td>-
+	<td>-
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_central_hadeshub_20131015.bit">trb3_central_hadeshub_20131015.bit</a>
+	<td>Central hub with four sfp, use in Hades as central hub
+      <tr class="outdated">
+	<td>2013.07.13
+	<td>Internal
+	<td>-
+	<td>-
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_central_hub_20130713.bit">trb3_central_hub_20130713.bit</a>
+	<td>stable build
 </table>
 
+<h4>PADIWA AddOn-4ConnAddOn</h4>
+<table>
+<tr><th>Date
+    <th title="Version of the TDC">TDC
+    <th title="Number of physics channels, not including reference channel">Channels
+    <th title="single edge, double edge (same/alternating channel)">Type
+    <th title="Buffer size for each channel">Buff/Chan
+    <th title="Total buffer size in words">Buff
+    <th title="Few words about the design">Comment
+
+      <tr>
+	<td>2014.12.03
+	<td>2.0.0
+	<td>48
+	<td>DE same + stretcher
+	<td>117
+	<td>400
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_periph_padiwa_20141203.bit">trb3_periph_padiwa_20141203.bit</a>
+	<td>
+
+      <tr class="outdated">
+	<td>2014.11.04
+	<td>1.6.3
+	<td>16
+	<td>DE alternating
+	<td>117
+	<td>400
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_periph_padiwa_dbl_alt_20141104.bit">trb3_periph_padiwa_dbl_alt_20141104.bit</a>
+	<td>
+      <tr class="outdated">
+	<td>2014.04.08
+	<td>1.6
+	<td>16
+	<td>DE alternating
+	<td>108???
+	<td>400???
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_periph_padiwa_amps_dbl_alt_20140408.bit">trb3_periph_padiwa_amps_dbl_alt_20140408.bit</a>
+	<td>
+      <tr class="outdated">
+	<td>2014.06.25
+	<td>1.6???
+	<td>16
+	<td>DE alternating
+	<td>108???
+	<td>400???
+	<td><a href="http://jspc29.x-matter.uni-frankfurt.de/bitfiles/trb3_periph_hodoscope_dbl_alt_32ch_20140625.bit">trb3_periph_hodoscope_dbl_alt_32ch_20140625.bit</a>
+	<td>
+      
+</table>
+
+
+
+
+
+
+
+
+
+
+
+
 
 
 <h4>DreamPlug Designs</h4>