From: Michael Boehmer Date: Wed, 19 Oct 2022 06:33:52 +0000 (+0200) Subject: small changes X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9106b7592ab6cdb6eb26b0419be7e14f922ce96a;p=trb3sc.git small changes --- diff --git a/gbe_hub/clock_reset_handler.vhd b/gbe_hub/clock_reset_handler.vhd index ff888f2..2290986 100644 --- a/gbe_hub/clock_reset_handler.vhd +++ b/gbe_hub/clock_reset_handler.vhd @@ -128,8 +128,7 @@ begin RESET_OUT => reset_i ); - RESET_OUT <= reset_i; - + RESET_OUT <= reset_i; RESET_N_OUT <= not reset_i; THE_ENPIRION_PLL: entity pll_dcdc diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index 362dd0b..56d9ede 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -228,7 +228,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is begin -- SerDes usage: --- backplane: A0 uplink on backplane, (A1, A2, A3 unused)MOD1 +-- backplane: A0 uplink on backplane, (A1, A2, A3 unused) -- B0, B1, B2, B3 downlink on hub addon -- C0, C1, C2, C3 downlink on hub addon -- D0, D1 downlink on TRB3sc, (D2, D3 unused) @@ -238,6 +238,15 @@ begin -- B0, B1, B2, B3 unused -- C0, C1, C2, C3 unused +-- SerDes connections: +-- A0, A1, A2, A3 -> backplane (A0 is uplink in backplane configuration) +-- B0, B1 -> hub addon6, hub addon8 +-- B2, B3 -> hub addon8 +-- C0, C1, C2, C3 -> hubb addon6, hub addon8 +-- D0, D1 -> SFP on TRB3sc +-- D2, D3 unused +-- valid only for PCSSW set to x"e4"! + --------------------------------------------------------------------------- -- Serdes Select --------------------------------------------------------------------------- @@ -253,10 +262,10 @@ begin THE_CLOCK_RESET_HANDLER: entity clock_reset_handler port map( CLK_IN => CLK_SUPPL_PCLK, - GLOBAL_RESET_IN => global_reset_i, --'0', -- for sync operation + GLOBAL_RESET_IN => global_reset_i, RESET_FROM_NET_IN => '0', -- unused -- - CLK_OUT => clk_sys, + CLK_OUT => clk_sys, -- this is the LOCAL clock, for reference usage only! RESET_OUT => reset_i, RESET_N_OUT => reset_n_i, CLEAR_OUT => clear_i, @@ -979,7 +988,7 @@ begin tx_pll_lol_i <= tx_pll_lol_a_i or tx_pll_lol_b_i or tx_pll_lol_c_i or tx_pll_lol_d_i; - global_reset_i <= not tx_clk_avail_i; + global_reset_i <= not tx_clk_avail_i; -- keep everything in reset until we get some clock --------------------------------------------------------------------------- -- LED