From: Tobias Weber <webert@kph.uni-mainz.de>
Date: Wed, 4 Sep 2013 09:31:33 +0000 (+0200)
Subject: Add sources/remove last remaining nxyter lines
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9121472d5cd88a07a90d103a21243e9a7301e8cf;p=trb3.git

Add sources/remove last remaining nxyter lines
---

diff --git a/mupix/trb3_periph.prj b/mupix/trb3_periph.prj
index 65669a6..f011bfe 100644
--- a/mupix/trb3_periph.prj
+++ b/mupix/trb3_periph.prj
@@ -140,4 +140,19 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 
 
-
+#MuPix Files
+add_file -vhdl -lib "work" "trb3_periph.vhd"
+
+add_file -vhdl -lib "work" "sources/mupix_components.vhd"
+add_file -vhdl -lib "work" "sources/BlockMemory.vhd"
+add_file -vhdl -lib "work" "sources/EventBuffer.vhd"
+add_file -vhdl -lib "work" "sources/graycounter.vhd"
+add_file -vhdl -lib "work" "sources/Histogram.vhd"
+add_file -vhdl -lib "work" "sources/HitbusHistogram.vhd"
+add_file -vhdl -lib "work" "sources/injection_generator.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_board.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_interface.vhd"
+add_file -vhdl -lib "work" "sources/MuPix3_PixCtr.vhd"
+add_file -vhdl -lib "work" "sources/spi_if.vhd"
+
+add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
diff --git a/mupix/trb3_periph.vhd b/mupix/trb3_periph.vhd
index f5487c2..2728a80 100644
--- a/mupix/trb3_periph.vhd
+++ b/mupix/trb3_periph.vhd
@@ -13,7 +13,7 @@ use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb3_components.all;
 use work.version.all;
-use work.nxyter_components.all;
+use work.mupix_components.all;
 
 library ecp3;
 use ecp3.components.all;
@@ -113,9 +113,6 @@ entity trb3_periph is
   attribute syn_useioff of FPGA5_COMM       : signal is true;
   attribute syn_useioff of TEST_LINE        : signal is true;
   --attribute syn_useioff of INP           : signal is false;
-  attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
-  attribute syn_useioff of NX2_TIMESTAMP_IN : signal is true;
-  --attribute syn_useioff of NX1_ADC_NX_IN   : signal is true;
   --attribute syn_useioff of DAC_SDO       : signal is true;
   --attribute syn_useioff of DAC_SDI       : signal is true;
   --attribute syn_useioff of DAC_SCK       : signal is true;
@@ -684,28 +681,5 @@ begin
       );
 
 
-  -----------------------------------------------------------------------------
-  -- MuPix common Clocks
-  -----------------------------------------------------------------------------
-  pll_nx_clk256_1 : entity work.pll_nx_clk256
-    port map (
-      CLK   => clk_100_i,
-      CLKOP => nx_clk256,
-      LOCK  => pll_lock_clk256
-      );
-
-  NX1_CLK256A_OUT <= nx_clk256;
-  NX2_CLK256A_OUT <= nx_clk256;
-
-  -- ADC Receiver Clock
-  pll_adc_clk192_1 : pll_adc_clk192
-    port map (
-      CLK   => CLK_PCLK_LEFT,
-      CLKOP => clk_adc_dat,
-      LOCK  => clk_adc_dat_lock
-      );
-
- 
-
 
 end architecture;