From: hadeshyp Date: Wed, 25 Aug 2010 16:41:31 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~190 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9175a6503945609ba6ab0c3a12d98c0a99c5fec0;p=trbnet.git *** empty log message *** --- diff --git a/lattice/ecp2m/pll_in100_out25.lpc b/lattice/ecp2m/pll_in100_out25.lpc index 630d528..16cce13 100644 --- a/lattice/ecp2m/pll_in100_out25.lpc +++ b/lattice/ecp2m/pll_in100_out25.lpc @@ -16,8 +16,8 @@ CoreRevision=5.1 ModuleName=pll_in100_out25 SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=08/16/2010 -Time=18:01:31 +Date=08/19/2010 +Time=13:30:57 [Parameters] Verilog=0 @@ -28,7 +28,7 @@ Expression=None Order=None IO=0 Type=ehxpllb -mode=normal +mode=advanced IFrq=100 OFrq=25.000000 KFrq= @@ -42,8 +42,8 @@ Post=48 SecD=2 fb_mode=CLKOP PhaseDuty=Static -DelayControl=AUTO_NO_DELAY -External=AUTO +DelayControl=GPLL_NO_DELAY +External=DISABLED PCDR=0 ClkOPBp=0 EnCLKOS=0 diff --git a/lattice/ecp2m/pll_in100_out25.vhd b/lattice/ecp2m/pll_in100_out25.vhd index da6ff0f..0380a58 100644 --- a/lattice/ecp2m/pll_in100_out25.vhd +++ b/lattice/ecp2m/pll_in100_out25.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20) -- Module Version: 5.2 ---/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap AUTO -noclkos -noclkok -norst -e +--/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -mdiv 4 -ndiv 1 -vdiv 48 -delay_cntl GPLL_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -norst -e --- Mon Aug 16 18:01:32 2010 +-- Thu Aug 19 13:30:58 2010 library IEEE; use IEEE.std_logic_1164.all; @@ -64,8 +64,8 @@ architecture Structure of pll_in100_out25 is attribute CLKFB_DIV : string; attribute CLKI_DIV : string; attribute FIN : string; - attribute PLLCAP of PLLDInst_0 : label is "AUTO"; - attribute PLLTYPE of PLLDInst_0 : label is "AUTO"; + attribute PLLCAP of PLLDInst_0 : label is "DISABLED"; + attribute PLLTYPE of PLLDInst_0 : label is "GPLL"; attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; attribute CLKOK_DIV of PLLDInst_0 : label is "2"; @@ -92,7 +92,7 @@ begin PLLDInst_0: EPLLD -- synopsys translate_off - generic map (PLLCAP=> "AUTO", CLKOK_BYPASS=> "DISABLED", + generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED", CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 48, CLKFB_DIV=> 1, CLKI_DIV=> 4) diff --git a/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.lpc b/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.lpc index f8c2bf4..a3d871c 100644 --- a/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.lpc +++ b/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_fot_full_quad_ctc SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=08/18/2010 -Time=23:30:13 +Date=08/19/2010 +Time=21:29:46 [Parameters] Verilog=0 @@ -74,10 +74,10 @@ RxTermCh0=50 RxTermCh1=50 RxTermCh2=50 RxTermCh3=50 -RxCoupCh0=DC -RxCoupCh1=DC -RxCoupCh2=DC -RxCoupCh3=DC +RxCoupCh0=AC +RxCoupCh1=AC +RxCoupCh2=AC +RxCoupCh3=AC Loss=0 CDRLoss=0 TxTerm=50 diff --git a/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.txt b/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.txt index 678e4a8..1ce3297 100644 --- a/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.txt +++ b/media_interfaces/ecp2m_fot/serdes_fot_full_quad_ctc.txt @@ -46,10 +46,10 @@ CH0_RTERM_RX "50" CH1_RTERM_RX "50" CH2_RTERM_RX "50" CH3_RTERM_RX "50" -CH0_RX_DCC "DC" -CH1_RX_DCC "DC" -CH2_RX_DCC "DC" -CH3_RX_DCC "DC" +CH0_RX_DCC "AC" +CH1_RX_DCC "AC" +CH2_RX_DCC "AC" +CH3_RX_DCC "AC" LOS_THRESHOLD "0" PLL_TERM "50" PLL_DCC "DC" diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd index 41c025f..11d4091 100644 --- a/media_interfaces/trb_net16_med_ecp_fot.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot.vhd @@ -141,7 +141,10 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; signal request_cnt_i : unsigned(7 downto 0); signal reset_rx_control : std_logic; signal send_reset_words_ext : std_logic; - + signal ffs_plol_low_stable : std_logic; + signal ffs_plol_counter : std_logic_vector(18 downto 0); + signal tx_lane_reset_q : std_logic; + signal tx_lane_reset : std_logic; begin ----------------------------------------------------------------------- @@ -350,6 +353,19 @@ reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); D_OUT(8) => link_ok_q ); + TX_TO_CLK_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => '0', + D_IN(0) => tx_lane_reset, + CLK0 => CLK_25, + CLK1 => CLK, + D_OUT(0) => tx_lane_reset_q + ); + SYNC_INPUT_TO_CLK : signal_sync generic map( DEPTH => 2, @@ -398,6 +414,25 @@ reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); end if; end process; +----------------------------------------------------------------------- +--TX Reset +----------------------------------------------------------------------- + + tx_lane_reset <= ffs_plol or quad_rst_qtx or not ffs_plol_low_stable ; + + process(CLK_25) + begin + if rising_edge(CLK_25) then + if ffs_plol = '0' then + ffs_plol_low_stable <= '0'; + ffs_plol_counter <= (others => '0'); + elsif ffs_plol_counter(18 downto 17) /= "11" then + ffs_plol_low_stable <= ffs_plol_counter(18); + ffs_plol_counter <= ffs_plol_counter + 1; + end if; + end if; + end process; + ----------------------------------------------------------------------- --Debugging ----------------------------------------------------------------------- diff --git a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd index 175d5c1..57115b6 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd @@ -223,7 +223,7 @@ signal buf_med_packet_num_out : std_logic_vector(3*4-1 downto 0); signal rx_counter : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); signal sfp_los : std_logic_vector(3 downto 0); -signal led_counter : std_logic_vector(15 downto 0); +signal led_counter : std_logic_vector(14 downto 0); signal rx_led : std_logic_vector(3 downto 0); signal tx_led : std_logic_vector(3 downto 0); @@ -246,6 +246,10 @@ signal request_cnt_i : link_error_t; signal reset_rx_control : std_logic_vector(3 downto 0); signal enable_correction_i : std_logic_vector(3 downto 0); +signal ffs_plol_low_stable : std_logic; +signal ffs_plol_counter : std_logic_vector(18 downto 0); +signal tx_lane_reset_q : std_logic_vector(3 downto 0); +signal tx_lane_reset : std_logic; attribute syn_keep : boolean; attribute syn_preserve : boolean; @@ -276,7 +280,7 @@ gen_normal_serdes : if REVERSE_ORDER = c_NO generate ff_disp_err_ch0 => link_error(0)(0), ff_cv_ch0 => link_error(0)(1), ffc_rrst_ch0 => '0', - ffc_lane_tx_rst_ch0 => lane_rst(0), + ffc_lane_tx_rst_ch0 => lane_rst(0),--tx_lane_reset, -- ffc_lane_rx_rst_ch0 => lane_rst(0), ffc_txpwdnb_ch0 => '1', ffc_rxpwdnb_ch0 => '1', @@ -514,6 +518,28 @@ THE_SERDES: serdes_fot_full_quad_ctc ); end generate; + + +----------------------------------------------------------------------- +--TX Reset +----------------------------------------------------------------------- + + tx_lane_reset <= ffs_plol or quad_rst_qtx(0) or not ffs_plol_low_stable ; + + process(CLK_25) + begin + ffs_plol_low_stable <= '0'; + if rising_edge(CLK_25) then + if ffs_plol = '0' then + ffs_plol_low_stable <= '0'; + ffs_plol_counter <= (others => '0'); + elsif ffs_plol_counter(18 downto 17) /= "11" then + ffs_plol_low_stable <= ffs_plol_counter(18); + ffs_plol_counter <= ffs_plol_counter + 1; + end if; + end if; + end process; + gen_logic : for i in 0 to 3 generate ----------------------------------------------------------------------- @@ -524,7 +550,7 @@ gen_logic : for i in 0 to 3 generate TXCLK_IN => CLK_25, RXCLK_IN => CLK_25, SYSCLK_IN => CLK, - RESET_IN => RESET, + RESET_IN => lane_rst(i), TX_DATA_IN => MED_DATA_IN(i*16+15 downto i*16), TX_WRITE_IN => MED_DATAREADY_IN(i), @@ -557,7 +583,7 @@ gen_logic : for i in 0 to 3 generate RX_K_IN => rx_k(i), RX_CV_IN => link_error(i)(1), RX_DISP_ERR_IN => link_error(i)(0), - RX_ALLOW_IN => rx_allow_qtx(i), + RX_ALLOW_IN => rx_allow(i), -- media interface SYSCLK_IN => CLK, MED_DATA_OUT => buf_med_data_out(i*16+15 downto i*16), @@ -598,7 +624,7 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ SFP_LOS_IN => sfp_los(i), SD_LINK_OK_IN => link_ok_q(i), SD_LOS_IN => link_error_q(i)(2), - SD_TXCLK_BAD_IN => ffs_plol, + SD_TXCLK_BAD_IN => ffs_plol, -- SD_RXCLK_BAD_IN => link_error_q(i)(7), SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope SD_ALIGNMENT_IN => "10", @@ -647,16 +673,18 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ RX_TO_CLK_SYNC: signal_sync generic map( DEPTH => 2, - WIDTH => 9 + WIDTH => 10 ) port map( RESET => '0', D_IN(7 downto 0) => link_error(i), D_IN(8) => link_ok(i), + D_IN(9) => tx_lane_reset, CLK0 => CLK_25, CLK1 => CLK, D_OUT(7 downto 0) => link_error_q(i), - D_OUT(8) => link_ok_q(i) + D_OUT(8) => link_ok_q(i), + D_OUT(9) => tx_lane_reset_q(i) ); SYNC_INPUT_TO_CLK : signal_sync @@ -676,17 +704,18 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ + ----------------------------------------------------------------------- --STAT & Debug ----------------------------------------------------------------------- STAT_OP(i*16+7 downto i*16+0) <= FSM_STAT_OP(i*16+7 downto i*16+0); - STAT_OP(i*16+8) <= start_retransmit_i(i); + --STAT_OP(i*16+8) <= start_retransmit_i(i);--signal is registered! STAT_OP(i*16+9) <= FSM_STAT_OP(i*16+9); STAT_OP(i*16+10) <= rx_led(i); STAT_OP(i*16+11) <= tx_led(i); - STAT_OP(i*16+12) <= request_retransmit_i(i) when CTRL_OP(i*16+8) = '1' else (link_error(i)(1) and not send_reset_words(i) and tx_allow(i)); + --STAT_OP(i*16+12) <= --signal is registered! STAT_OP(i*16+13) <= make_trbnet_reset(i); STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); STAT_OP(i*16+15) <= send_reset_words(i); @@ -695,6 +724,13 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ process(CLK) begin if rising_edge(CLK) then + STAT_OP(i*16+8) <= start_retransmit_i(i); + if CTRL_OP(i*16+8) = '1' then + STAT_OP(i*16+12) <= request_retransmit_i(i); + else + STAT_OP(i*16+12) <= (link_error(i)(1) and not send_reset_words(i) and tx_allow(i)); + end if; + STAT_DEBUG(i*64+16) <= request_retransmit_i(i); STAT_DEBUG(i*64+17) <= start_retransmit_i(i); STAT_DEBUG(i*64+25 downto i*64+18) <= rx_data(i*8+7 downto i*8); @@ -727,15 +763,10 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ ----------------------------------------------------------------------- --LED Signals ----------------------------------------------------------------------- - THE_TX_RX_LED_PROC: process( clk_25 ) + THE_TX_LED_PROC: process( clk_25 ) begin if( rising_edge(CLK_25) ) then last_tx_k(i) <= tx_k(i); - if ( buf_med_dataready_out(i) = '1' ) then - rx_led(i) <= '1'; - elsif( led_counter = 0 ) then - rx_led(i) <= '0'; - end if; if( tx_k(i) = '0' and last_tx_k(i) = '0') then tx_led(i) <= '1'; elsif led_counter = 0 then @@ -744,13 +775,23 @@ reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_ end if; end process; + THE_RX_LED_PROC: process( clk_25 ) + begin + if( rising_edge(CLK_25) ) then + if ( buf_med_dataready_out(i) = '1' ) then + rx_led(i) <= '1'; + elsif( led_counter = 0 ) then + rx_led(i) <= '0'; + end if; + end if; + end process; end generate; - PROC_LED_COUNTER: process(CLK) + PROC_LED_COUNTER: process(CLK_25) begin - if( rising_edge(CLK) ) then + if( rising_edge(CLK_25) ) then led_counter <= led_counter + 1; end if; end process PROC_LED_COUNTER; diff --git a/media_interfaces/trb_net16_rx_comma_handler.vhd b/media_interfaces/trb_net16_rx_comma_handler.vhd index 25fbb65..58f7108 100644 --- a/media_interfaces/trb_net16_rx_comma_handler.vhd +++ b/media_interfaces/trb_net16_rx_comma_handler.vhd @@ -223,10 +223,10 @@ comma_locked_x <= '1' when (comma_ctr = x"f") else '0'; ---------------------------------------------------------------------- comma_valid_x <= comma_locked and (comma_idle or comma_error or comma_stx) - and not buf_cv(1) and not buf_cv(0) and not buf_disperr(0) and not buf_disperr(1); + and not buf_cv(1) and not buf_cv(0) ; --and not buf_disperr(0) and not buf_disperr(1); data_valid_x <= comma_locked and not buf_k(1) and not buf_k(0) - and not buf_cv(1) and not buf_cv(0) and not buf_disperr(0) and not buf_disperr(1); + and not buf_cv(1) and not buf_cv(0) ; --and not buf_disperr(0) and not buf_disperr(1); fifo_wr_x <= comma_toggle and data_valid_x and not fifo_inhibit; @@ -235,7 +235,7 @@ begin if( rising_edge(CLK_IN) ) then if ( (RESET_IN = '1') or (comma_stx = '1') or ENABLE_CORRECTION_IN = '0') then fifo_inhibit <= '0'; - elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') ) then + elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') and c_reset_x = '0' ) then fifo_inhibit <= '1'; end if; end if; diff --git a/media_interfaces/trb_net16_rx_control.vhd b/media_interfaces/trb_net16_rx_control.vhd index efa5096..e704217 100644 --- a/media_interfaces/trb_net16_rx_control.vhd +++ b/media_interfaces/trb_net16_rx_control.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; ---use work.trb_net_components.all; +use work.trb_net_components.all; entity trb_net16_rx_control is port( @@ -199,6 +199,8 @@ signal rx_resume : std_logic; signal rx_gone_wrong_x : std_logic; signal rx_gone_wrong : std_logic; +signal rx_allow_qrx : std_logic; +signal enable_correction_qrx: std_logic; signal comma_locked : std_logic; @@ -219,7 +221,7 @@ port map( RX_K_IN => RX_K_IN, RX_CV_IN => RX_CV_IN, RX_DISP_ERR_IN => RX_DISP_ERR_IN, - RX_ALLOW_IN => RX_ALLOW_IN, + RX_ALLOW_IN => rx_allow_qrx, -- FIFO interface FIFO_DATA_OUT => fifo_wr_data, FIFO_WR_OUT => fifo_wr_en, @@ -234,7 +236,7 @@ port map( -- reset handling SEND_RESET_WORDS_OUT => send_reset_words, MAKE_TRBNET_RESET_OUT => make_trbnet_reset, - ENABLE_CORRECTION_IN => ENABLE_CORRECTION_IN, + ENABLE_CORRECTION_IN => enable_correction_qrx, -- Debugging DEBUG_OUT => debug_rch ); @@ -270,6 +272,37 @@ port map( STATE_B_OUT => rx_gone_wrong ); +-- clock domain transfer for RX problems +THE_RX_ALLOW_SYNC: signal_sync +generic map( + DEPTH => 2, + WIDTH => 2 +) +port map( + RESET => '0', + D_IN(0) => RX_ALLOW_IN, + D_IN(1) => ENABLE_CORRECTION_IN, + CLK0 => CLK_IN, + CLK1 => CLK_IN, + D_OUT(0) => rx_allow_qrx, + D_OUT(1) => enable_correction_qrx +); + +-- THE_RX_ALLOW_SYNC: signal_sync +-- generic map( +-- DEPTH => 2, +-- WIDTH => 1 +-- ) +-- port map( +-- RESET => '0', +-- D_IN(0) => RX_ALLOW_IN, +-- CLK0 => SYSCLK_IN, +-- CLK1 => SYSCLK_IN, +-- D_OUT(0) => rx_allow_qrx +-- ); + + + ---------------------------------------------------------------------- -- the RX FIFO itself ---------------------------------------------------------------------- diff --git a/media_interfaces/trb_net16_rx_full_packets.vhd b/media_interfaces/trb_net16_rx_full_packets.vhd index 381a40d..3b3ba4b 100644 --- a/media_interfaces/trb_net16_rx_full_packets.vhd +++ b/media_interfaces/trb_net16_rx_full_packets.vhd @@ -89,6 +89,21 @@ signal rx_data_ctr : unsigned(7 downto 0); signal debug : std_logic_vector(15 downto 0); + +attribute syn_keep : boolean; +attribute syn_preserve : boolean; +attribute NOMERGE : string; +attribute NOCLIP : string; + +attribute syn_keep of bsm : signal is true; +attribute syn_preserve of bsm : signal is true; +attribute NOMERGE of bsm : signal is "ON"; +attribute NOCLIP of bsm : signal is "ON"; +attribute syn_keep of bsm_x : signal is true; +attribute syn_preserve of bsm_x : signal is true; +attribute NOMERGE of bsm_x : signal is "ON"; +attribute NOCLIP of bsm_x : signal is "ON"; + begin ---------------------------------------------------------------------- diff --git a/media_interfaces/trb_net16_tx_control.vhd b/media_interfaces/trb_net16_tx_control.vhd index f452b46..c95e0b3 100644 --- a/media_interfaces/trb_net16_tx_control.vhd +++ b/media_interfaces/trb_net16_tx_control.vhd @@ -81,6 +81,7 @@ architecture arch of trb_net16_tx_control is signal start_retransmit_i : std_logic; signal request_retransmit_i : std_logic; + signal buf_tx_read_out : std_logic; signal tx_data_25_i : std_logic_vector(15 downto 0); signal tx_allow_qtx : std_logic; signal send_link_reset_qtx : std_logic; @@ -110,8 +111,16 @@ begin AlmostFull => ct_fifo_afull ); -TX_READ_OUT <= TX_ALLOW_IN and not ct_fifo_afull ; -ct_fifo_write<= TX_ALLOW_IN and not ct_fifo_afull and TX_WRITE_IN; + THE_RD_PROC : process(SYSCLK_IN) + begin + if rising_edge(SYSCLK_IN) then + buf_tx_read_out <= TX_ALLOW_IN and not ct_fifo_afull ; + end if; + end process; + +TX_READ_OUT <= buf_tx_read_out; + +ct_fifo_write<= buf_tx_read_out and TX_WRITE_IN; ct_fifo_read <= tx_allow_qtx and not ram_afull; ---------------------------------------------------------------------- @@ -178,8 +187,8 @@ THE_RAM_WR_PROC : process(TXCLK_IN) --RAM empty - ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)); - ram_afull <= '1' when ram_fill_level > 5 else '0'; + ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN; + ram_afull <= '1' when ram_fill_level > 4 else '0'; @@ -255,8 +264,11 @@ THE_RAM_WR_PROC : process(TXCLK_IN) if current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or - current_state = SEND_REQUEST_H then - if send_link_reset_qtx = '1' then + current_state = SEND_REQUEST_H or + current_state = SLEEP then + if RESET_IN = '1' then + current_state <= SEND_IDLE_L; + elsif send_link_reset_qtx = '1' then current_state <= SEND_RESET; elsif make_request_i = '1' then current_state <= SEND_REQUEST_L; diff --git a/pinout/mdchub_fpga1234.lpf b/pinout/mdchub_fpga1234.lpf index 570ee05..e95469e 100644 --- a/pinout/mdchub_fpga1234.lpf +++ b/pinout/mdchub_fpga1234.lpf @@ -24,25 +24,25 @@ ##################################################################### # Test connector ##################################################################### - LOCATE COMP "TEST_LINE_0" SITE "F7"; - LOCATE COMP "TEST_LINE_1" SITE "D8"; - LOCATE COMP "TEST_LINE_2" SITE "J13"; - LOCATE COMP "TEST_LINE_3" SITE "G11"; - LOCATE COMP "TEST_LINE_4" SITE "H13"; - LOCATE COMP "TEST_LINE_5" SITE "H12"; - LOCATE COMP "TEST_LINE_6" SITE "E8"; - LOCATE COMP "TEST_LINE_7" SITE "D9"; - LOCATE COMP "TEST_LINE_8" SITE "D12"; - LOCATE COMP "TEST_LINE_9" SITE "E13"; - LOCATE COMP "TEST_LINE_10" SITE "J12"; - LOCATE COMP "TEST_LINE_11" SITE "H10"; - LOCATE COMP "TEST_LINE_12" SITE "E12"; - LOCATE COMP "TEST_LINE_13" SITE "D11"; - LOCATE COMP "TEST_LINE_14" SITE "H11"; - LOCATE COMP "TEST_LINE_15" SITE "F11"; - - DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; - IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; +# LOCATE COMP "TEST_LINE_0" SITE "F7"; +# LOCATE COMP "TEST_LINE_1" SITE "D8"; +# LOCATE COMP "TEST_LINE_2" SITE "J13"; +# LOCATE COMP "TEST_LINE_3" SITE "G11"; +# LOCATE COMP "TEST_LINE_4" SITE "H13"; +# LOCATE COMP "TEST_LINE_5" SITE "H12"; +# LOCATE COMP "TEST_LINE_6" SITE "E8"; +# LOCATE COMP "TEST_LINE_7" SITE "D9"; +# LOCATE COMP "TEST_LINE_8" SITE "D12"; +# LOCATE COMP "TEST_LINE_9" SITE "E13"; +# LOCATE COMP "TEST_LINE_10" SITE "J12"; +# LOCATE COMP "TEST_LINE_11" SITE "H10"; +# LOCATE COMP "TEST_LINE_12" SITE "E12"; +# LOCATE COMP "TEST_LINE_13" SITE "D11"; +# LOCATE COMP "TEST_LINE_14" SITE "H11"; +# LOCATE COMP "TEST_LINE_15" SITE "F11"; +# +# DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +# IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; ##################################################################### diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index f4051df..55dbafa 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -1384,10 +1384,14 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); proc_retransmit_counters : process(CLK) begin if rising_edge(CLK) then - if MED_STAT_OP(i*16+12) = '1' then + if HC_COMMON_CTRL_REGS(5) = '1' then + sent_retransmit_requests(i) <= (others => '0'); + elsif MED_STAT_OP(i*16+12) = '1' then sent_retransmit_requests(i) <= sent_retransmit_requests(i) + to_unsigned(1,1); end if; - if MED_STAT_OP(i*16+8) = '1' then + if HC_COMMON_CTRL_REGS(5) = '1' then + received_retransmit_requests(i) <= (others => '0'); + elsif MED_STAT_OP(i*16+8) = '1' then received_retransmit_requests(i) <= received_retransmit_requests(i) + to_unsigned(1,1); end if; end if;