From: Jan Michel <j.michel@gsi.de>
Date: Mon, 3 Feb 2014 17:43:17 +0000 (+0100)
Subject: Added ADC design files
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=9199a2c82fea081387714184f38740bc39cfa289;p=trb3.git

Added ADC design files
---

diff --git a/ADC/compile_periph_frankfurt.pl b/ADC/compile_periph_frankfurt.pl
new file mode 100755
index 0000000..79066c3
--- /dev/null
+++ b/ADC/compile_periph_frankfurt.pl
@@ -0,0 +1,152 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME                      = "trb3_periph_adc";  #Name of top-level entity
+my $lattice_path                 = '/d/jspc29/lattice/diamond/2.2_x64';
+my $synplify_path                = '/d/jspc29/lattice/synplify/G-2012.09-SP1/';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+###################################################################################
+
+
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
+
+
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
+
+
+
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA672";
+my $SPEEDGRADE="8";
+
+
+#create full lpf file
+system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+    constant VERSION_NUMBER_TIME  : integer   := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+
+
+foreach (@a)
+{
+    if(/\@E:/)
+    {
+	print "\n";
+	$c="cat $TOPNAME.srr | grep \"\@E\"";
+	system($c);
+        print "\n\n";
+	exit 129;
+    }
+}
+
+
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+system("rm $TOPNAME.ncd");
+
+#$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
+#  $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
+execute($c);
+# IOR IO Timing Report
+# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+# execute($c);
+
+# TWR Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No  $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd"  "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+    my ($c, $op) = @_;
+    #print "option: $op \n";
+    $op = "" if(!$op);
+    print "\n\ncommand to execute: $c \n";
+    $r=system($c);
+    if($r) {
+	print "$!";
+	if($op ne "do_not_exit") {
+	    exit;
+	}
+    }
+
+    return $r;
+
+}
diff --git a/ADC/config.vhd b/ADC/config.vhd
new file mode 100644
index 0000000..79fde73
--- /dev/null
+++ b/ADC/config.vhd
@@ -0,0 +1,56 @@
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+
+    
+--Run wih 125 MHz instead of 100 MHz     
+    constant USE_125_MHZ            : integer := c_NO;  --not implemented yet!  
+    
+--Use sync mode, RX clock for all parts of the FPGA
+    constant USE_RXCLOCK            : integer := c_NO;  --not implemented yet!
+    
+   
+--Address settings   
+    constant INIT_ADDRESS           : std_logic_vector := x"F30a";
+    constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4b";
+   
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------
+--Select settings by configuration 
+------------------------------------------------------------------------------
+    type intlist_t is array(0 to 7) of integer;
+    type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+    constant HW_INFO_BASE            : unsigned(31 downto 0) := x"91009480";
+    
+    constant CLOCK_FREQUENCY_ARR  : intlist_t := (100,125, others => 0);
+    constant MEDIA_FREQUENCY_ARR  : intlist_t := (200,125, others => 0);
+                          
+  --declare constants, filled in body                          
+    constant HARDWARE_INFO        : std_logic_vector(31 downto 0);
+    constant CLOCK_FREQUENCY      : integer;
+    constant MEDIA_FREQUENCY      : integer;
+
+end;
+
+package body config is
+--compute correct configuration mode
+  
+  constant HARDWARE_INFO        : std_logic_vector(31 downto 0) := std_logic_vector(
+                                      HW_INFO_BASE );
+  constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
+  constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
+  
+end package body;
\ No newline at end of file
diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
new file mode 100644
index 0000000..9e8a745
--- /dev/null
+++ b/ADC/trb3_periph_adc.prj
@@ -0,0 +1,150 @@
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN672C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3_periph_adc"
+set_option -resource_sharing true
+
+# map options
+set_option -frequency 200
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+#set_option -force_gsr 
+set_option -force_gsr false
+set_option -fixgatedclocks false #3
+set_option -fixgeneratedclocks false #3
+set_option -compiler_compatible true
+
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3_periph_adc.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#add_file options
+
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+
+add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd"
+add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
+add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
+add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200.vhd"
+add_file -vhdl -lib "work" "../base/code/adc_ad9219.vhd"
+
+add_file -vhdl -lib "work" "trb3_periph_adc.vhd"
+
diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd
new file mode 100644
index 0000000..1b2617a
--- /dev/null
+++ b/ADC/trb3_periph_adc.vhd
@@ -0,0 +1,581 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.config.all;
+use work.version.all;
+
+
+entity trb3_periph_adc is
+  port(
+    --Clocks
+    CLK_GPLL_LEFT        : in    std_logic;  --Clock Manager 1/(2468), 125 MHz
+    CLK_GPLL_RIGHT       : in    std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
+    CLK_PCLK_LEFT        : in    std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+    CLK_PCLK_RIGHT       : in    std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+    --Trigger
+    TRIGGER_LEFT         : in    std_logic;  --left side trigger input from fan-out
+    TRIGGER_RIGHT        : in    std_logic;  --right side trigger input from fan-out
+    --Serdes
+    CLK_SERDES_INT_LEFT  : in    std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
+    CLK_SERDES_INT_RIGHT : in    std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
+    SERDES_INT_TX        : out   std_logic_vector(3 downto 0);
+    SERDES_INT_RX        : in    std_logic_vector(3 downto 0);
+    SERDES_ADDON_TX      : out   std_logic_vector(11 downto 0);
+    SERDES_ADDON_RX      : in    std_logic_vector(11 downto 0);
+    --Inter-FPGA Communication
+    FPGA5_COMM           : inout std_logic_vector(11 downto 0);
+                                        --Bit 0/1 input, serial link RX active
+                                        --Bit 2/3 output, serial link TX active
+
+    --Connection to AddOn               
+    ADC1_CH              : in std_logic_vector(4 downto 0);
+    ADC2_CH              : in std_logic_vector(4 downto 0);
+    ADC3_CH              : in std_logic_vector(4 downto 0);
+    ADC4_CH              : in std_logic_vector(4 downto 0);
+    ADC5_CH              : in std_logic_vector(4 downto 0);
+    ADC6_CH              : in std_logic_vector(4 downto 0);
+    ADC7_CH              : in std_logic_vector(4 downto 0);
+    ADC8_CH              : in std_logic_vector(4 downto 0);
+    ADC9_CH              : in std_logic_vector(4 downto 0);
+    ADC10_CH             : in std_logic_vector(4 downto 0);
+    ADC11_CH             : in std_logic_vector(4 downto 0);
+    ADC12_CH             : in std_logic_vector(4 downto 0);
+    ADC_DCO              : in std_logic_vector(12 downto 1);
+
+    SPI_ADC_SCK          : out std_logic;
+    SPI_ADC_SDIO         : inout std_logic;
+    
+    LMK_CLK              : out std_logic;
+    LMK_DATA             : out std_logic;
+    LMK_LE_1             : out std_logic;
+    LMK_LE_2             : out std_logic;
+    
+    P_CLOCK              : out std_logic;
+    
+    FPGA_CS              : out std_logic;
+    FPGA_SCK             : out std_logic;
+    FPGA_SDI             : out std_logic;
+    FPGA_SDO             : in  std_logic;
+    
+    --Flash ROM & Reboot
+    FLASH_CLK  : out   std_logic;
+    FLASH_CS   : out   std_logic;
+    FLASH_DIN  : out   std_logic;
+    FLASH_DOUT : in    std_logic;
+    PROGRAMN   : out   std_logic;       --reboot FPGA
+    --Misc
+    TEMPSENS   : inout std_logic;       --Temperature Sensor
+    CODE_LINE  : in    std_logic_vector(1 downto 0);
+    LED_GREEN  : out   std_logic;
+    LED_ORANGE : out   std_logic;
+    LED_RED    : out   std_logic;
+    LED_YELLOW : out   std_logic;
+    SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
+    --Test Connectors
+    TEST_LINE  : out   std_logic_vector(15 downto 0)
+    );
+  attribute syn_useioff                  : boolean;
+  --no IO-FF for LEDs relaxes timing constraints
+  attribute syn_useioff of LED_GREEN     : signal is false;
+  attribute syn_useioff of LED_ORANGE    : signal is false;
+  attribute syn_useioff of LED_RED       : signal is false;
+  attribute syn_useioff of LED_YELLOW    : signal is false;
+  attribute syn_useioff of TEMPSENS      : signal is false;
+  attribute syn_useioff of PROGRAMN      : signal is false;
+  attribute syn_useioff of CODE_LINE     : signal is false;
+  attribute syn_useioff of TRIGGER_LEFT  : signal is false;
+  attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+  --important signals
+  attribute syn_useioff of FLASH_CLK     : signal is true;
+  attribute syn_useioff of FLASH_CS      : signal is true;
+  attribute syn_useioff of FLASH_DIN     : signal is true;
+  attribute syn_useioff of FLASH_DOUT    : signal is true;
+  attribute syn_useioff of FPGA5_COMM    : signal is true;
+  attribute syn_useioff of TEST_LINE     : signal is true;
+
+  
+
+end entity;
+
+
+architecture trb3_periph_adc_arch of trb3_periph_adc is
+
+  attribute syn_keep     : boolean;
+  attribute syn_preserve : boolean;
+
+  --Clock / Reset
+  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal clk_125_i                : std_logic;  -- 125 MHz, via Clock Manager and bypassed PLL
+  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
+  signal clear_i                  : std_logic;
+  signal reset_i                  : std_logic;
+  signal GSR_N                    : std_logic;
+  attribute syn_keep of GSR_N     : signal is true;
+  attribute syn_preserve of GSR_N : signal is true;
+
+  --Media Interface
+  signal med_stat_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_ctrl_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_stat_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_data_out       : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_out  : std_logic;
+  signal med_read_out       : std_logic;
+  signal med_data_in        : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_in  : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_in   : std_logic;
+  signal med_read_in        : std_logic;
+
+  --LVL1 channel
+  signal timing_trg_received_i  : std_logic;
+  signal trg_data_valid_i       : std_logic;
+  signal trg_timing_valid_i     : std_logic;
+  signal trg_notiming_valid_i   : std_logic;
+  signal trg_invalid_i          : std_logic;
+  signal trg_type_i             : std_logic_vector(3 downto 0);
+  signal trg_number_i           : std_logic_vector(15 downto 0);
+  signal trg_code_i             : std_logic_vector(7 downto 0);
+  signal trg_information_i      : std_logic_vector(23 downto 0);
+  signal trg_int_number_i       : std_logic_vector(15 downto 0);
+  signal trg_multiple_trg_i     : std_logic;
+  signal trg_timeout_detected_i : std_logic;
+  signal trg_spurious_trg_i     : std_logic;
+  signal trg_missing_tmg_trg_i  : std_logic;
+  signal trg_spike_detected_i   : std_logic;
+
+  --Data channel
+  signal fee_trg_release_i    : std_logic;
+  signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
+  signal fee_data_i           : std_logic_vector(31 downto 0);
+  signal fee_data_write_i     : std_logic;
+  signal fee_data_finished_i  : std_logic;
+  signal fee_almost_full_i    : std_logic;
+
+  --Slow Control channel
+  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+
+  --RegIO
+  signal regio_addr_out         : std_logic_vector (15 downto 0);
+  signal regio_read_enable_out  : std_logic;
+  signal regio_write_enable_out : std_logic;
+  signal regio_data_out         : std_logic_vector (31 downto 0);
+  signal regio_data_in          : std_logic_vector (31 downto 0);
+  signal regio_dataready_in     : std_logic;
+  signal regio_no_more_data_in  : std_logic;
+  signal regio_write_ack_in     : std_logic;
+  signal regio_unknown_addr_in  : std_logic;
+  signal regio_timeout_out      : std_logic;
+
+  --Timer
+  signal global_time         : std_logic_vector(31 downto 0);
+  signal local_time          : std_logic_vector(7 downto 0);
+  signal time_since_last_trg : std_logic_vector(31 downto 0);
+  signal timer_ticks         : std_logic_vector(1 downto 0);
+
+  --Flash
+  signal spimem_read_en          : std_logic;
+  signal spimem_write_en         : std_logic;
+  signal spimem_data_in          : std_logic_vector(31 downto 0);
+  signal spimem_addr             : std_logic_vector(8 downto 0);
+  signal spimem_data_out         : std_logic_vector(31 downto 0);
+  signal spimem_dataready_out    : std_logic;
+  signal spimem_no_more_data_out : std_logic;
+  signal spimem_unknown_addr_out : std_logic;
+  signal spimem_write_ack_out    : std_logic;
+
+  --SPI to FPGA
+  signal spifpga_read_en   : std_logic;
+  signal spifpga_write_en  : std_logic;
+  signal spifpga_data_in   : std_logic_vector(31 downto 0);
+  signal spifpga_addr      : std_logic_vector(4 downto 0);
+  signal spifpga_data_out  : std_logic_vector(31 downto 0);
+  signal spifpga_ack       : std_logic;
+  signal spifpga_busy      : std_logic;
+
+  signal clk_adcfast_i     : std_logic;
+  signal clk_adcref_i      : std_logic;
+  signal debug_adc         : std_logic_vector(31 downto 0);
+  signal adc_restart_i     : std_logic;
+  
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+  GSR_N <= pll_lock;
+
+  THE_RESET_HANDLER : trb_net_reset_handler
+    generic map(
+      RESET_DELAY => x"FEEE"
+      )
+    port map(
+      CLEAR_IN      => '0',              -- reset input (high active, async)
+      CLEAR_N_IN    => '1',              -- reset input (low active, async)
+      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
+      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
+      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
+      RESET_IN      => '0',              -- general reset signal (SYSCLK)
+      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
+      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
+      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
+      DEBUG_OUT     => open
+      );
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+  THE_MAIN_PLL : pll_in200_out100
+    port map(
+      CLK   => CLK_GPLL_RIGHT,
+      CLKOP => clk_100_i,
+      CLKOK => clk_200_i,
+      LOCK  => pll_lock
+      );
+
+  THE_ADC_PLL : entity work.pll_adc10bit
+    port map(
+      CLK   => CLK_PCLK_RIGHT,
+      CLKOS => open,
+      CLKOP => clk_adcref_i,
+      LOCK  => open
+      );
+      
+  clk_adcfast_i <= clk_200_i;
+  
+  
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+    generic map(
+      SERDES_NUM  => 1,                 --number of serdes in quad
+      EXT_CLOCK   => c_NO,              --use internal clock
+      USE_200_MHZ => c_YES,             --run on 200 MHz clock
+      USE_125_MHZ => c_NO,
+      USE_CTC     => c_NO
+      )
+    port map(
+      CLK                => clk_200_i,
+      SYSCLK             => clk_100_i,
+      RESET              => reset_i,
+      CLEAR              => clear_i,
+      CLK_EN             => '1',
+      --Internal Connection
+      MED_DATA_IN        => med_data_out,
+      MED_PACKET_NUM_IN  => med_packet_num_out,
+      MED_DATAREADY_IN   => med_dataready_out,
+      MED_READ_OUT       => med_read_in,
+      MED_DATA_OUT       => med_data_in,
+      MED_PACKET_NUM_OUT => med_packet_num_in,
+      MED_DATAREADY_OUT  => med_dataready_in,
+      MED_READ_IN        => med_read_out,
+      REFCLK2CORE_OUT    => open,
+      --SFP Connection
+      SD_RXD_P_IN        => SERDES_INT_RX(2),
+      SD_RXD_N_IN        => SERDES_INT_RX(3),
+      SD_TXD_P_OUT       => SERDES_INT_TX(2),
+      SD_TXD_N_OUT       => SERDES_INT_TX(3),
+      SD_REFCLK_P_IN     => open,
+      SD_REFCLK_N_IN     => open,
+      SD_PRSNT_N_IN      => FPGA5_COMM(0),
+      SD_LOS_IN          => FPGA5_COMM(0),
+      SD_TXDIS_OUT       => FPGA5_COMM(2),
+      -- Status and control port
+      STAT_OP            => med_stat_op,
+      CTRL_OP            => med_ctrl_op,
+      STAT_DEBUG         => med_stat_debug,
+      CTRL_DEBUG         => (others => '0')
+      );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+
+  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+    generic map(
+      REGIO_NUM_STAT_REGS       => 0,
+      REGIO_NUM_CTRL_REGS       => 0,
+      ADDRESS_MASK              => x"FFFF",
+      BROADCAST_BITMASK         => x"48",
+      BROADCAST_SPECIAL_ADDR    => BROADCAST_SPECIAL_ADDR,
+      REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+      REGIO_HARDWARE_VERSION    => HARDWARE_INFO,
+      REGIO_INIT_ADDRESS        => INIT_ADDRESS,
+      REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+      CLOCK_FREQUENCY           => CLOCK_FREQUENCY,
+      TIMING_TRIGGER_RAW        => c_YES,
+      --Configure data handler
+      DATA_INTERFACE_NUMBER     => 1,
+      DATA_BUFFER_DEPTH         => 13,           --13
+      DATA_BUFFER_WIDTH         => 32,
+      DATA_BUFFER_FULL_THRESH   => 2**13-800,    --2**13-(maximal 2**12) 
+      TRG_RELEASE_AFTER_DATA    => c_YES,
+      HEADER_BUFFER_DEPTH       => 9,
+      HEADER_BUFFER_FULL_THRESH => 2**9-16
+      )
+    port map(
+      CLK                => clk_100_i,
+      RESET              => reset_i,
+      CLK_EN             => '1',
+      MED_DATAREADY_OUT  => med_dataready_out,  -- open,  --
+      MED_DATA_OUT       => med_data_out,  -- open,  --
+      MED_PACKET_NUM_OUT => med_packet_num_out,  -- open,  --
+      MED_READ_IN        => med_read_in,
+      MED_DATAREADY_IN   => med_dataready_in,
+      MED_DATA_IN        => med_data_in,
+      MED_PACKET_NUM_IN  => med_packet_num_in,
+      MED_READ_OUT       => med_read_out,  -- open,  --
+      MED_STAT_OP_IN     => med_stat_op,
+      MED_CTRL_OP_OUT    => med_ctrl_op,
+
+      --Timing trigger in
+      TRG_TIMING_TRG_RECEIVED_IN  => timing_trg_received_i,
+      --LVL1 trigger to FEE
+      LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
+      LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
+      LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+      LVL1_INVALID_TRG_OUT        => trg_invalid_i,
+
+      LVL1_TRG_TYPE_OUT        => trg_type_i,
+      LVL1_TRG_NUMBER_OUT      => trg_number_i,
+      LVL1_TRG_CODE_OUT        => trg_code_i,
+      LVL1_TRG_INFORMATION_OUT => trg_information_i,
+      LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
+
+      --Information about trigger handler errors
+      TRG_MULTIPLE_TRG_OUT     => trg_multiple_trg_i,
+      TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+      TRG_SPURIOUS_TRG_OUT     => trg_spurious_trg_i,
+      TRG_MISSING_TMG_TRG_OUT  => trg_missing_tmg_trg_i,
+      TRG_SPIKE_DETECTED_OUT   => trg_spike_detected_i,
+
+      --Response from FEE
+      FEE_TRG_RELEASE_IN(0)       => fee_trg_release_i,
+      FEE_TRG_STATUSBITS_IN       => fee_trg_statusbits_i,
+      FEE_DATA_IN                 => fee_data_i,
+      FEE_DATA_WRITE_IN(0)        => fee_data_write_i,
+      FEE_DATA_FINISHED_IN(0)     => fee_data_finished_i,
+      FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+      -- Slow Control Data Port
+      REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
+      REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
+      REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
+      REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
+      REGIO_STAT_REG_IN                  => (others => '0'),
+      REGIO_CTRL_REG_OUT                 => open,
+      REGIO_STAT_STROBE_OUT              => open,
+      REGIO_CTRL_STROBE_OUT              => open,
+      REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
+      REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+      BUS_ADDR_OUT         => regio_addr_out,
+      BUS_READ_ENABLE_OUT  => regio_read_enable_out,
+      BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+      BUS_DATA_OUT         => regio_data_out,
+      BUS_DATA_IN          => regio_data_in,
+      BUS_DATAREADY_IN     => regio_dataready_in,
+      BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
+      BUS_WRITE_ACK_IN     => regio_write_ack_in,
+      BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
+      BUS_TIMEOUT_OUT      => regio_timeout_out,
+      ONEWIRE_INOUT        => TEMPSENS,
+      ONEWIRE_MONITOR_OUT  => open,
+
+      TIME_GLOBAL_OUT         => global_time,
+      TIME_LOCAL_OUT          => local_time,
+      TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+      TIME_TICKS_OUT          => timer_ticks,
+
+      STAT_DEBUG_IPU              => open,
+      STAT_DEBUG_1                => open,
+      STAT_DEBUG_2                => open,
+      STAT_DEBUG_DATA_HANDLER_OUT => open,
+      STAT_DEBUG_IPU_HANDLER_OUT  => open,
+      STAT_TRIGGER_OUT            => open,
+      CTRL_MPLEX                  => (others => '0'),
+      IOBUF_CTRL_GEN              => (others => '0'),
+      STAT_ONEWIRE                => open,
+      STAT_ADDR_DEBUG             => open,
+      DEBUG_LVL1_HANDLER_OUT      => open
+      );
+
+  timing_trg_received_i <= TRIGGER_LEFT;  --TRIGGER_RIGHT;  --
+  common_stat_reg       <= (others => '0');
+
+
+---------------------------------------------------------------------------
+-- AddOn
+---------------------------------------------------------------------------
+THE_ADC : entity work.adc_ad9219
+  generic map(
+    CHANNELS      => 4,
+    DEVICES_LEFT  => 7,
+    DEVICES_RIGHT => 5,
+    RESOLUTION    => 10
+    )
+  port map(
+    CLK        => clk_100_i,
+    CLK_ADCREF => clk_adcref_i,
+    CLK_ADCDAT => clk_adcfast_i,
+    RESTART_IN => adc_restart_i,
+    ADCCLK_OUT => P_CLOCK,
+    
+    ADC_DATA( 4 downto  0)   => ADC1_CH,
+    ADC_DATA( 9 downto  5)   => ADC2_CH,
+    ADC_DATA(14 downto 10)   => ADC3_CH,
+    ADC_DATA(19 downto 15)   => ADC4_CH,
+    ADC_DATA(24 downto 20)   => ADC5_CH,
+    ADC_DATA(29 downto 25)   => ADC6_CH,
+    ADC_DATA(34 downto 30)   => ADC7_CH,
+    ADC_DATA(39 downto 35)   => ADC8_CH,
+    ADC_DATA(44 downto 40)   => ADC9_CH,
+    ADC_DATA(49 downto 45)   => ADC10_CH,
+    ADC_DATA(54 downto 50)   => ADC11_CH,
+    ADC_DATA(59 downto 55)   => ADC12_CH,
+    
+    ADC_DCO    => ADC_DCO,
+    
+    DATA_OUT       => open,
+    FCO_OUT        => open,
+    DATA_VALID_OUT => open,
+    DEBUG          => debug_adc
+    );
+
+adc_restart_i <= '0';
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+  THE_BUS_HANDLER : trb_net16_regio_bus_handler
+    generic map(
+      PORT_NUMBER    => 2,
+      PORT_ADDRESSES => (0 => x"d000", 1 => x"d400",  others => x"0000"),
+      PORT_ADDR_MASK => (0 => 9,       1 => 5,        others => 0)
+      )
+    port map(
+      CLK   => clk_100_i,
+      RESET => reset_i,
+
+      DAT_ADDR_IN          => regio_addr_out,
+      DAT_DATA_IN          => regio_data_out,
+      DAT_DATA_OUT         => regio_data_in,
+      DAT_READ_ENABLE_IN   => regio_read_enable_out,
+      DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
+      DAT_TIMEOUT_IN       => regio_timeout_out,
+      DAT_DATAREADY_OUT    => regio_dataready_in,
+      DAT_WRITE_ACK_OUT    => regio_write_ack_in,
+      DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+      DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+    --Bus Handler (SPI Flash control)
+      BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
+      BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
+      BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
+      BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
+      BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+      BUS_TIMEOUT_OUT(0)                  => open,
+      BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
+      BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
+      BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
+      BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
+      BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
+      --Bus Handler (SPI to FPGA)
+      BUS_READ_ENABLE_OUT(1)              => spifpga_read_en,
+      BUS_WRITE_ENABLE_OUT(1)             => spifpga_write_en,
+      BUS_DATA_OUT(1*32+31 downto 1*32)   => spifpga_data_in,
+      BUS_ADDR_OUT(1*16+4 downto 1*16)    => spifpga_addr,
+      BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
+      BUS_TIMEOUT_OUT(1)                  => open,
+      BUS_DATA_IN(1*32+31 downto 1*32)    => spifpga_data_out,
+      BUS_DATAREADY_IN(1)                 => spifpga_ack,
+      BUS_WRITE_ACK_IN(1)                 => spifpga_ack,
+      BUS_NO_MORE_DATA_IN(1)              => spifpga_busy,
+      BUS_UNKNOWN_ADDR_IN(1)              => '0',
+
+      STAT_DEBUG => open
+      );
+
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
+  port map(
+    CLK_IN               => clk_100_i,
+    RESET_IN             => reset_i,
+    
+    BUS_ADDR_IN          => spimem_addr,
+    BUS_READ_IN          => spimem_read_en,
+    BUS_WRITE_IN         => spimem_write_en,
+    BUS_DATAREADY_OUT    => spimem_dataready_out,
+    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
+    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+    BUS_DATA_IN          => spimem_data_in,
+    BUS_DATA_OUT         => spimem_data_out,
+    
+    DO_REBOOT_IN         => common_ctrl_reg(15),     
+    PROGRAMN             => PROGRAMN,
+    
+    SPI_CS_OUT           => FLASH_CS,
+    SPI_SCK_OUT          => FLASH_CLK,
+    SPI_SDO_OUT          => FLASH_DIN,
+    SPI_SDI_IN           => FLASH_DOUT
+    );
+
+-------------------------------------------------------------------------------
+-- SPI
+-------------------------------------------------------------------------------
+
+FPGA_SPI : spi_ltc2600
+  generic map (
+    BITS       => 16,
+    WAITCYCLES => 15)
+  port map (
+    CLK_IN         => clk_100_i,
+    RESET_IN       => reset_i,
+    -- Slave bus
+    BUS_READ_IN    => spifpga_read_en,
+    BUS_WRITE_IN   => spifpga_write_en,
+    BUS_BUSY_OUT   => spifpga_busy,
+    BUS_ACK_OUT    => spifpga_ack,
+    BUS_ADDR_IN    => spifpga_addr,
+    BUS_DATA_IN    => spifpga_data_in,
+    BUS_DATA_OUT   => spifpga_data_out,
+    -- SPI connections
+    SPI_CS_OUT(0)  => FPGA_CS,
+    SPI_SDI_IN     => FPGA_SDO,
+    SPI_SDO_OUT    => FPGA_SDI,
+    SPI_SCK_OUT    => FPGA_SCK,
+    SPI_CLR_OUT(0) => open
+    );
+
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+LED_GREEN  <= not med_stat_op(9);
+LED_ORANGE <= not med_stat_op(10);
+LED_RED    <= not or_all(debug_adc) when rising_edge(clk_100_i);
+LED_YELLOW <= not med_stat_op(11);
+
+---------------------------------------------------------------------------
+-- Test Connector - Logic Analyser
+---------------------------------------------------------------------------
+
+  TEST_LINE <= (others => '0');
+
+end architecture;
diff --git a/base/code/adc_ad9219.vhd b/base/code/adc_ad9219.vhd
new file mode 100644
index 0000000..19a65cd
--- /dev/null
+++ b/base/code/adc_ad9219.vhd
@@ -0,0 +1,148 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb3_components.all;
+
+entity adc_ad9219 is
+  generic(
+    CHANNELS       : integer range 4 to 4 := 4;
+    DEVICES_LEFT   : integer range 1 to 7 := 7;
+    DEVICES_RIGHT  : integer range 1 to 7 := 5;
+    RESOLUTION     : integer range 10 to 10 := 10
+    );
+  port(
+    CLK        : in std_logic;
+    CLK_ADCREF : in std_logic;
+    CLK_ADCDAT : in std_logic;
+    RESTART_IN : in std_logic;
+    ADCCLK_OUT : out std_logic;
+        --FCO is another channel for each ADC    
+    ADC_DATA   : in  std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*(CHANNELS+1)-1 downto 0);
+    ADC_DCO    : in  std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT) downto 1);
+    
+    DATA_OUT       : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*CHANNELS*RESOLUTION-1 downto 0);
+    FCO_OUT        : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*RESOLUTION-1 downto 0);
+    DATA_VALID_OUT : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)-1 downto 0);
+    DEBUG          : out std_logic_vector(31 downto 0)
+    );
+end entity;
+
+
+
+architecture adc_ad9219_arch of  adc_ad9219 is
+
+type q_t is array(0 to 11) of std_logic_vector(19 downto 0);
+signal q : q_t;
+signal tmp : q_t;
+
+signal clk_data_left   : std_logic;
+signal clk_data_right  : std_logic;
+signal restart_i   : std_logic;
+
+begin
+
+  ADCCLK_OUT <= CLK_ADCREF;
+  restart_i <= RESTART_IN when rising_edge(clk_data_left);
+
+THE_LEFT : entity work.dqsinput_7x5
+    port map(
+        clk_0  => ADC_DCO(1),
+        clk_1  => ADC_DCO(2), 
+        clk_2  => ADC_DCO(3), 
+        clk_3  => ADC_DCO(4),
+        clk_4  => ADC_DCO(5),
+        clk_5  => ADC_DCO(6),
+        clk_6  => ADC_DCO(7),
+        clkdiv_reset => restart_i,
+        eclk   => CLK_ADCREF, 
+        reset_0 => restart_i,
+        reset_1 => restart_i, 
+        reset_2 => restart_i,
+        reset_3 => restart_i,
+        reset_4 => restart_i,
+        reset_5 => restart_i,
+        reset_6 => restart_i,
+        sclk    => clk_data_left,
+        datain_0 => ADC_DATA( 4 downto  0),
+        datain_1 => ADC_DATA( 9 downto  5),
+        datain_2 => ADC_DATA(14 downto 10),
+        datain_3 => ADC_DATA(19 downto 15),
+        datain_4 => ADC_DATA(24 downto 20),
+        datain_5 => ADC_DATA(29 downto 25),
+        datain_6 => ADC_DATA(34 downto 30),
+        q_0      => q(0),
+        q_1      => q(1),
+        q_2      => q(2),
+        q_3      => q(3),
+        q_4      => q(4),
+        q_5      => q(5),
+        q_6      => q(6)
+        );
+  
+THE_RIGHT : entity work.dqsinput_5x5
+    port map(
+        clk_0  => ADC_DCO(8),
+        clk_1  => ADC_DCO(9), 
+        clk_2  => ADC_DCO(10), 
+        clk_3  => ADC_DCO(11),
+        clk_4  => ADC_DCO(12),
+        clkdiv_reset => restart_i,
+        eclk   => CLK_ADCREF, 
+        reset_0 => restart_i,
+        reset_1 => restart_i, 
+        reset_2 => restart_i,
+        reset_3 => restart_i,
+        reset_4 => restart_i,
+        sclk    => clk_data_right,
+        datain_0 => ADC_DATA(39 downto 35),
+        datain_1 => ADC_DATA(44 downto 40),
+        datain_2 => ADC_DATA(49 downto 45),
+        datain_3 => ADC_DATA(54 downto 50),
+        datain_4 => ADC_DATA(59 downto 55),
+        q_0      => q(7),
+        q_1      => q(8),
+        q_2      => q(9),
+        q_3      => q(10),
+        q_4      => q(11)
+        );
+        
+        
+gen_chips_left : for i in 0 to DEVICES_LEFT-1 generate
+  THE_FIFO : fifo_cdt_200
+    port map(
+      Data(19 downto 0)  => q(i),
+      WrClock  => clk_data_left,
+      RdClock  => CLK,
+      WrEn     => '1',
+      RdEn     => '1',
+      Reset    => '0',
+      RPReset  => restart_i,
+      Q        => open,
+      Empty    => open,
+      Full     => open
+      );
+  DEBUG(i) <= or_all(tmp(i));    
+end generate;    
+
+gen_chips_right : for i in DEVICES_LEFT to DEVICES_LEFT+DEVICES_RIGHT-1 generate
+  THE_FIFO : fifo_cdt_200
+    port map(
+      Data(19 downto 0)  => q(i),
+      WrClock  => clk_data_right,
+      RdClock  => CLK,
+      WrEn     => '1',
+      RdEn     => '1',
+      Reset    => '0',
+      RPReset  => restart_i,
+      Q(19 downto 0)  => tmp(i),
+      Empty    => open,
+      Full     => open
+      );
+  DEBUG(i) <= or_all(tmp(i));    
+end generate;    
+
+
+end architecture;
\ No newline at end of file
diff --git a/base/cores/dqsinput_5x5.ipx b/base/cores/dqsinput_5x5.ipx
new file mode 100644
index 0000000..ec2de68
--- /dev/null
+++ b/base/cores/dqsinput_5x5.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="dqsinput_5x5" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 03 17:39:57.249" version="5.4" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="dqsinput_5x5.lpc" type="lpc" modified="2014 02 03 17:39:54.000"/>
+		<File name="dqsinput_5x5.vhd" type="top_level_vhdl" modified="2014 02 03 17:39:55.000"/>
+		<File name="dqsinput_5x5_tmpl.vhd" type="template_vhdl" modified="2014 02 03 17:39:55.000"/>
+  </Package>
+</DiamondModule>
diff --git a/base/cores/dqsinput_5x5.lpc b/base/cores/dqsinput_5x5.lpc
new file mode 100644
index 0000000..822c416
--- /dev/null
+++ b/base/cores/dqsinput_5x5.lpc
@@ -0,0 +1,62 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=5.4
+ModuleName=dqsinput_5x5
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=02/03/2014
+Time=17:39:54
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Receive
+trioddr=0
+io_type=LVDS25
+num_int=5
+width=5
+freq_in=200
+bandwidth=2000
+aligned=Centered
+pre-configuration=DISABLED
+mode2=Receive
+trioddr2=0
+io_type2=LVDS25
+freq_in2=200
+gear=2x
+aligned2=Centered
+num_int2=5
+width2=5
+Interface=GDDRX2_RX.DQS.Centered
+Delay=Bypass
+Number=5
+dqs1=5
+dqs2=5
+dqs3=5
+dqs4=5
+dqs5=5
+dqs6=
+dqs7=
+dqs8=
+val=
+Phase=TRDLLB/DLLDELB
+Divider=CLKDIVB
+Multiplier=2
+PllFreq=100
diff --git a/base/cores/dqsinput_5x5.vhd b/base/cores/dqsinput_5x5.vhd
new file mode 100644
index 0000000..cd81aba
--- /dev/null
+++ b/base/cores/dqsinput_5x5.vhd
@@ -0,0 +1,935 @@
+-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
+-- Module  Version: 5.4
+--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n dqsinput_5x5 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 200 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -dqs 3 5 -dqs 4 5 -dqs 5 5 -e 
+
+-- Mon Feb  3 17:39:55 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity dqsinput_5x5 is
+    port (
+        clk_0: in  std_logic; 
+        clk_1: in  std_logic; 
+        clk_2: in  std_logic; 
+        clk_3: in  std_logic; 
+        clk_4: in  std_logic; 
+        clkdiv_reset: in  std_logic; 
+        eclk: in  std_logic; 
+        reset_0: in  std_logic; 
+        reset_1: in  std_logic; 
+        reset_2: in  std_logic; 
+        reset_3: in  std_logic; 
+        reset_4: in  std_logic; 
+        sclk: out  std_logic; 
+        datain_0: in  std_logic_vector(4 downto 0); 
+        datain_1: in  std_logic_vector(4 downto 0); 
+        datain_2: in  std_logic_vector(4 downto 0); 
+        datain_3: in  std_logic_vector(4 downto 0); 
+        datain_4: in  std_logic_vector(4 downto 0); 
+        q_0: out  std_logic_vector(19 downto 0); 
+        q_1: out  std_logic_vector(19 downto 0); 
+        q_2: out  std_logic_vector(19 downto 0); 
+        q_3: out  std_logic_vector(19 downto 0); 
+        q_4: out  std_logic_vector(19 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of dqsinput_5x5 : entity is true;
+end dqsinput_5x5;
+
+architecture Structure of dqsinput_5x5 is
+
+    -- internal signal declarations
+    signal datain_4i_t4: std_logic;
+    signal datain_4i_t3: std_logic;
+    signal datain_4i_t2: std_logic;
+    signal datain_4i_t1: std_logic;
+    signal datain_4i_t0: std_logic;
+    signal buf_datain_4i4: std_logic;
+    signal buf_datain_4i3: std_logic;
+    signal buf_datain_4i2: std_logic;
+    signal buf_datain_4i1: std_logic;
+    signal buf_datain_4i0: std_logic;
+    signal datain_3i_t4: std_logic;
+    signal datain_3i_t3: std_logic;
+    signal datain_3i_t2: std_logic;
+    signal datain_3i_t1: std_logic;
+    signal datain_3i_t0: std_logic;
+    signal buf_datain_3i4: std_logic;
+    signal buf_datain_3i3: std_logic;
+    signal buf_datain_3i2: std_logic;
+    signal buf_datain_3i1: std_logic;
+    signal buf_datain_3i0: std_logic;
+    signal datain_2i_t4: std_logic;
+    signal datain_2i_t3: std_logic;
+    signal datain_2i_t2: std_logic;
+    signal datain_2i_t1: std_logic;
+    signal datain_2i_t0: std_logic;
+    signal buf_datain_2i4: std_logic;
+    signal buf_datain_2i3: std_logic;
+    signal buf_datain_2i2: std_logic;
+    signal buf_datain_2i1: std_logic;
+    signal buf_datain_2i0: std_logic;
+    signal datain_1i_t4: std_logic;
+    signal datain_1i_t3: std_logic;
+    signal datain_1i_t2: std_logic;
+    signal datain_1i_t1: std_logic;
+    signal datain_1i_t0: std_logic;
+    signal buf_datain_1i4: std_logic;
+    signal buf_datain_1i3: std_logic;
+    signal buf_datain_1i2: std_logic;
+    signal buf_datain_1i1: std_logic;
+    signal buf_datain_1i0: std_logic;
+    signal datain_0i_t4: std_logic;
+    signal datain_0i_t3: std_logic;
+    signal datain_0i_t2: std_logic;
+    signal datain_0i_t1: std_logic;
+    signal datain_0i_t0: std_logic;
+    signal buf_datain_0i4: std_logic;
+    signal buf_datain_0i3: std_logic;
+    signal buf_datain_0i2: std_logic;
+    signal buf_datain_0i1: std_logic;
+    signal buf_datain_0i0: std_logic;
+    signal qb124: std_logic;
+    signal qa124: std_logic;
+    signal qb024: std_logic;
+    signal qa024: std_logic;
+    signal datain_t24: std_logic;
+    signal qb123: std_logic;
+    signal qa123: std_logic;
+    signal qb023: std_logic;
+    signal qa023: std_logic;
+    signal datain_t23: std_logic;
+    signal qb122: std_logic;
+    signal qa122: std_logic;
+    signal qb022: std_logic;
+    signal qa022: std_logic;
+    signal datain_t22: std_logic;
+    signal qb121: std_logic;
+    signal qa121: std_logic;
+    signal qb021: std_logic;
+    signal qa021: std_logic;
+    signal datain_t21: std_logic;
+    signal qb120: std_logic;
+    signal qa120: std_logic;
+    signal qb020: std_logic;
+    signal qa020: std_logic;
+    signal datain_t20: std_logic;
+    signal qb119: std_logic;
+    signal qa119: std_logic;
+    signal qb019: std_logic;
+    signal qa019: std_logic;
+    signal datain_t19: std_logic;
+    signal qb118: std_logic;
+    signal qa118: std_logic;
+    signal qb018: std_logic;
+    signal qa018: std_logic;
+    signal datain_t18: std_logic;
+    signal qb117: std_logic;
+    signal qa117: std_logic;
+    signal qb017: std_logic;
+    signal qa017: std_logic;
+    signal datain_t17: std_logic;
+    signal qb116: std_logic;
+    signal qa116: std_logic;
+    signal qb016: std_logic;
+    signal qa016: std_logic;
+    signal datain_t16: std_logic;
+    signal qb115: std_logic;
+    signal qa115: std_logic;
+    signal qb015: std_logic;
+    signal qa015: std_logic;
+    signal datain_t15: std_logic;
+    signal qb114: std_logic;
+    signal qa114: std_logic;
+    signal qb014: std_logic;
+    signal qa014: std_logic;
+    signal datain_t14: std_logic;
+    signal qb113: std_logic;
+    signal qa113: std_logic;
+    signal qb013: std_logic;
+    signal qa013: std_logic;
+    signal datain_t13: std_logic;
+    signal qb112: std_logic;
+    signal qa112: std_logic;
+    signal qb012: std_logic;
+    signal qa012: std_logic;
+    signal datain_t12: std_logic;
+    signal qb111: std_logic;
+    signal qa111: std_logic;
+    signal qb011: std_logic;
+    signal qa011: std_logic;
+    signal datain_t11: std_logic;
+    signal qb110: std_logic;
+    signal qa110: std_logic;
+    signal qb010: std_logic;
+    signal qa010: std_logic;
+    signal datain_t10: std_logic;
+    signal qb19: std_logic;
+    signal qa19: std_logic;
+    signal qb09: std_logic;
+    signal qa09: std_logic;
+    signal datain_t9: std_logic;
+    signal qb18: std_logic;
+    signal qa18: std_logic;
+    signal qb08: std_logic;
+    signal qa08: std_logic;
+    signal datain_t8: std_logic;
+    signal qb17: std_logic;
+    signal qa17: std_logic;
+    signal qb07: std_logic;
+    signal qa07: std_logic;
+    signal datain_t7: std_logic;
+    signal qb16: std_logic;
+    signal qa16: std_logic;
+    signal qb06: std_logic;
+    signal qa06: std_logic;
+    signal datain_t6: std_logic;
+    signal qb15: std_logic;
+    signal qa15: std_logic;
+    signal qb05: std_logic;
+    signal qa05: std_logic;
+    signal datain_t5: std_logic;
+    signal qb14: std_logic;
+    signal qa14: std_logic;
+    signal qb04: std_logic;
+    signal qa04: std_logic;
+    signal datain_t4: std_logic;
+    signal qb13: std_logic;
+    signal qa13: std_logic;
+    signal qb03: std_logic;
+    signal qa03: std_logic;
+    signal datain_t3: std_logic;
+    signal qb12: std_logic;
+    signal qa12: std_logic;
+    signal qb02: std_logic;
+    signal qa02: std_logic;
+    signal datain_t2: std_logic;
+    signal qb11: std_logic;
+    signal qa11: std_logic;
+    signal qb01: std_logic;
+    signal qa01: std_logic;
+    signal datain_t1: std_logic;
+    signal qb10: std_logic;
+    signal qa10: std_logic;
+    signal qb00: std_logic;
+    signal qa00: std_logic;
+    signal datain_t0: std_logic;
+    signal dqclk14: std_logic;
+    signal dqclk04: std_logic;
+    signal eclkdqsr4: std_logic;
+    signal ddrlat4: std_logic;
+    signal datavalid4: std_logic;
+    signal prmbdet4: std_logic;
+    signal ddrclkpol4: std_logic;
+    signal dqsw4: std_logic;
+    signal dqclk13: std_logic;
+    signal dqclk03: std_logic;
+    signal eclkdqsr3: std_logic;
+    signal ddrlat3: std_logic;
+    signal datavalid3: std_logic;
+    signal prmbdet3: std_logic;
+    signal ddrclkpol3: std_logic;
+    signal dqsw3: std_logic;
+    signal dqclk12: std_logic;
+    signal dqclk02: std_logic;
+    signal eclkdqsr2: std_logic;
+    signal ddrlat2: std_logic;
+    signal datavalid2: std_logic;
+    signal prmbdet2: std_logic;
+    signal ddrclkpol2: std_logic;
+    signal dqsw2: std_logic;
+    signal dqclk11: std_logic;
+    signal dqclk01: std_logic;
+    signal eclkdqsr1: std_logic;
+    signal ddrlat1: std_logic;
+    signal datavalid1: std_logic;
+    signal prmbdet1: std_logic;
+    signal ddrclkpol1: std_logic;
+    signal dqsw1: std_logic;
+    signal dqclk10: std_logic;
+    signal dqclk00: std_logic;
+    signal eclkdqsr0: std_logic;
+    signal ddrlat0: std_logic;
+    signal datavalid0: std_logic;
+    signal prmbdet0: std_logic;
+    signal ddrclkpol0: std_logic;
+    signal dqsw0: std_logic;
+    signal scuba_vlo: std_logic;
+    signal dqsdel: std_logic;
+    signal dqsdll_lock: std_logic;
+    signal dqsdll_uddcntln: std_logic;
+    signal dqsdll_reset: std_logic;
+    signal clkos: std_logic;
+    signal cdiv8: std_logic;
+    signal cdiv4: std_logic;
+    signal cdiv1: std_logic;
+    signal scuba_vhi: std_logic;
+    signal clkok: std_logic;
+    signal buf_clk_4: std_logic;
+    signal buf_clk_3: std_logic;
+    signal buf_clk_2: std_logic;
+    signal buf_clk_1: std_logic;
+    signal buf_clk_0: std_logic;
+    signal sclk_t: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component IB
+        port (I: in  std_logic; O: out  std_logic);
+    end component;
+    component CLKDIVB
+        port (CLKI: in  std_logic; RST: in  std_logic; 
+            RELEASE: in  std_logic; CDIV1: out  std_logic; 
+            CDIV2: out  std_logic; CDIV4: out  std_logic; 
+            CDIV8: out  std_logic);
+    end component;
+    component IDDRX2D
+        generic (DELAYMODE : in String; SCLKLATENCY : in Integer);
+        port (D: in  std_logic; SCLK: in  std_logic; ECLK: in  std_logic; 
+            ECLKDQSR: in  std_logic; DDRLAT: in  std_logic; 
+            DDRCLKPOL: in  std_logic; QA0: out  std_logic; 
+            QB0: out  std_logic; QA1: out  std_logic; 
+            QB1: out  std_logic);
+    end component;
+    component DQSBUFD
+        generic (NRZMODE : in String; DYNDEL_CNTL : in String; 
+                DYNDEL_VAL : in Integer; DYNDEL_TYPE : in String);
+        port (DQSI: in  std_logic; SCLK: in  std_logic; 
+            READ: in  std_logic; DQSDEL: in  std_logic; 
+            ECLK: in  std_logic; ECLKW: in  std_logic; 
+            RST: in  std_logic; DYNDELPOL: in  std_logic; 
+            DYNDELAY6: in  std_logic; DYNDELAY5: in  std_logic; 
+            DYNDELAY4: in  std_logic; DYNDELAY3: in  std_logic; 
+            DYNDELAY2: in  std_logic; DYNDELAY1: in  std_logic; 
+            DYNDELAY0: in  std_logic; DQSW: out  std_logic; 
+            DDRCLKPOL: out  std_logic; PRMBDET: out  std_logic; 
+            DATAVALID: out  std_logic; DDRLAT: out  std_logic; 
+            ECLKDQSR: out  std_logic; DQCLK0: out  std_logic; 
+            DQCLK1: out  std_logic);
+    end component;
+    component DQSDLLB
+        generic (LOCK_SENSITIVITY : in String);
+        port (CLK: in  std_logic; RST: in  std_logic; 
+            UDDCNTLN: in  std_logic; LOCK: out  std_logic; 
+            DQSDEL: out  std_logic);
+    end component;
+    component DELAYC
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    attribute IDDRAPPS : string; 
+    attribute IO_TYPE : string; 
+    attribute IO_TYPE of Inst9_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB0 : label is "LVDS25";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_0 : label is "DQS_CENTERED";
+    attribute IO_TYPE of Inst1_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB0 : label is "LVDS25";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    udel_datain_4i4: DELAYC
+        port map (A=>buf_datain_4i4, Z=>datain_4i_t4);
+
+    udel_datain_4i3: DELAYC
+        port map (A=>buf_datain_4i3, Z=>datain_4i_t3);
+
+    udel_datain_4i2: DELAYC
+        port map (A=>buf_datain_4i2, Z=>datain_4i_t2);
+
+    udel_datain_4i1: DELAYC
+        port map (A=>buf_datain_4i1, Z=>datain_4i_t1);
+
+    udel_datain_4i0: DELAYC
+        port map (A=>buf_datain_4i0, Z=>datain_4i_t0);
+
+    Inst9_IB4: IB
+        port map (I=>datain_4(4), O=>buf_datain_4i4);
+
+    Inst9_IB3: IB
+        port map (I=>datain_4(3), O=>buf_datain_4i3);
+
+    Inst9_IB2: IB
+        port map (I=>datain_4(2), O=>buf_datain_4i2);
+
+    Inst9_IB1: IB
+        port map (I=>datain_4(1), O=>buf_datain_4i1);
+
+    Inst9_IB0: IB
+        port map (I=>datain_4(0), O=>buf_datain_4i0);
+
+    udel_datain_3i4: DELAYC
+        port map (A=>buf_datain_3i4, Z=>datain_3i_t4);
+
+    udel_datain_3i3: DELAYC
+        port map (A=>buf_datain_3i3, Z=>datain_3i_t3);
+
+    udel_datain_3i2: DELAYC
+        port map (A=>buf_datain_3i2, Z=>datain_3i_t2);
+
+    udel_datain_3i1: DELAYC
+        port map (A=>buf_datain_3i1, Z=>datain_3i_t1);
+
+    udel_datain_3i0: DELAYC
+        port map (A=>buf_datain_3i0, Z=>datain_3i_t0);
+
+    Inst8_IB4: IB
+        port map (I=>datain_3(4), O=>buf_datain_3i4);
+
+    Inst8_IB3: IB
+        port map (I=>datain_3(3), O=>buf_datain_3i3);
+
+    Inst8_IB2: IB
+        port map (I=>datain_3(2), O=>buf_datain_3i2);
+
+    Inst8_IB1: IB
+        port map (I=>datain_3(1), O=>buf_datain_3i1);
+
+    Inst8_IB0: IB
+        port map (I=>datain_3(0), O=>buf_datain_3i0);
+
+    udel_datain_2i4: DELAYC
+        port map (A=>buf_datain_2i4, Z=>datain_2i_t4);
+
+    udel_datain_2i3: DELAYC
+        port map (A=>buf_datain_2i3, Z=>datain_2i_t3);
+
+    udel_datain_2i2: DELAYC
+        port map (A=>buf_datain_2i2, Z=>datain_2i_t2);
+
+    udel_datain_2i1: DELAYC
+        port map (A=>buf_datain_2i1, Z=>datain_2i_t1);
+
+    udel_datain_2i0: DELAYC
+        port map (A=>buf_datain_2i0, Z=>datain_2i_t0);
+
+    Inst7_IB4: IB
+        port map (I=>datain_2(4), O=>buf_datain_2i4);
+
+    Inst7_IB3: IB
+        port map (I=>datain_2(3), O=>buf_datain_2i3);
+
+    Inst7_IB2: IB
+        port map (I=>datain_2(2), O=>buf_datain_2i2);
+
+    Inst7_IB1: IB
+        port map (I=>datain_2(1), O=>buf_datain_2i1);
+
+    Inst7_IB0: IB
+        port map (I=>datain_2(0), O=>buf_datain_2i0);
+
+    udel_datain_1i4: DELAYC
+        port map (A=>buf_datain_1i4, Z=>datain_1i_t4);
+
+    udel_datain_1i3: DELAYC
+        port map (A=>buf_datain_1i3, Z=>datain_1i_t3);
+
+    udel_datain_1i2: DELAYC
+        port map (A=>buf_datain_1i2, Z=>datain_1i_t2);
+
+    udel_datain_1i1: DELAYC
+        port map (A=>buf_datain_1i1, Z=>datain_1i_t1);
+
+    udel_datain_1i0: DELAYC
+        port map (A=>buf_datain_1i0, Z=>datain_1i_t0);
+
+    Inst6_IB4: IB
+        port map (I=>datain_1(4), O=>buf_datain_1i4);
+
+    Inst6_IB3: IB
+        port map (I=>datain_1(3), O=>buf_datain_1i3);
+
+    Inst6_IB2: IB
+        port map (I=>datain_1(2), O=>buf_datain_1i2);
+
+    Inst6_IB1: IB
+        port map (I=>datain_1(1), O=>buf_datain_1i1);
+
+    Inst6_IB0: IB
+        port map (I=>datain_1(0), O=>buf_datain_1i0);
+
+    udel_datain_0i4: DELAYC
+        port map (A=>buf_datain_0i4, Z=>datain_0i_t4);
+
+    udel_datain_0i3: DELAYC
+        port map (A=>buf_datain_0i3, Z=>datain_0i_t3);
+
+    udel_datain_0i2: DELAYC
+        port map (A=>buf_datain_0i2, Z=>datain_0i_t2);
+
+    udel_datain_0i1: DELAYC
+        port map (A=>buf_datain_0i1, Z=>datain_0i_t1);
+
+    udel_datain_0i0: DELAYC
+        port map (A=>buf_datain_0i0, Z=>datain_0i_t0);
+
+    Inst5_IB4: IB
+        port map (I=>datain_0(4), O=>buf_datain_0i4);
+
+    Inst5_IB3: IB
+        port map (I=>datain_0(3), O=>buf_datain_0i3);
+
+    Inst5_IB2: IB
+        port map (I=>datain_0(2), O=>buf_datain_0i2);
+
+    Inst5_IB1: IB
+        port map (I=>datain_0(1), O=>buf_datain_0i1);
+
+    Inst5_IB0: IB
+        port map (I=>datain_0(0), O=>buf_datain_0i0);
+
+    Inst_IDDRX2D_4_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t24, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa024, QB0=>qb024, QA1=>qa124, QB1=>qb124);
+
+    Inst_IDDRX2D_4_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t23, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa023, QB0=>qb023, QA1=>qa123, QB1=>qb123);
+
+    Inst_IDDRX2D_4_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t22, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa022, QB0=>qb022, QA1=>qa122, QB1=>qb122);
+
+    Inst_IDDRX2D_4_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t21, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa021, QB0=>qb021, QA1=>qa121, QB1=>qb121);
+
+    Inst_IDDRX2D_4_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t20, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa020, QB0=>qb020, QA1=>qa120, QB1=>qb120);
+
+    Inst_IDDRX2D_3_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t19, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa019, QB0=>qb019, QA1=>qa119, QB1=>qb119);
+
+    Inst_IDDRX2D_3_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t18, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa018, QB0=>qb018, QA1=>qa118, QB1=>qb118);
+
+    Inst_IDDRX2D_3_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t17, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa017, QB0=>qb017, QA1=>qa117, QB1=>qb117);
+
+    Inst_IDDRX2D_3_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t16, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa016, QB0=>qb016, QA1=>qa116, QB1=>qb116);
+
+    Inst_IDDRX2D_3_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t15, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa015, QB0=>qb015, QA1=>qa115, QB1=>qb115);
+
+    Inst_IDDRX2D_2_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t14, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa014, QB0=>qb014, QA1=>qa114, QB1=>qb114);
+
+    Inst_IDDRX2D_2_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t13, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa013, QB0=>qb013, QA1=>qa113, QB1=>qb113);
+
+    Inst_IDDRX2D_2_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t12, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa012, QB0=>qb012, QA1=>qa112, QB1=>qb112);
+
+    Inst_IDDRX2D_2_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t11, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa011, QB0=>qb011, QA1=>qa111, QB1=>qb111);
+
+    Inst_IDDRX2D_2_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t10, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa010, QB0=>qb010, QA1=>qa110, QB1=>qb110);
+
+    Inst_IDDRX2D_1_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t9, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa09, QB0=>qb09, QA1=>qa19, QB1=>qb19);
+
+    Inst_IDDRX2D_1_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t8, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa08, QB0=>qb08, QA1=>qa18, QB1=>qb18);
+
+    Inst_IDDRX2D_1_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t7, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa07, QB0=>qb07, QA1=>qa17, QB1=>qb17);
+
+    Inst_IDDRX2D_1_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t6, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa06, QB0=>qb06, QA1=>qa16, QB1=>qb16);
+
+    Inst_IDDRX2D_1_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t5, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa05, QB0=>qb05, QA1=>qa15, QB1=>qb15);
+
+    Inst_IDDRX2D_0_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t4, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa04, QB0=>qb04, QA1=>qa14, QB1=>qb14);
+
+    Inst_IDDRX2D_0_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t3, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa03, QB0=>qb03, QA1=>qa13, QB1=>qb13);
+
+    Inst_IDDRX2D_0_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t2, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa02, QB0=>qb02, QA1=>qa12, QB1=>qb12);
+
+    Inst_IDDRX2D_0_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t1, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa01, QB0=>qb01, QA1=>qa11, QB1=>qb11);
+
+    Inst_IDDRX2D_0_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t0, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa00, QB0=>qb00, QA1=>qa10, QB1=>qb10);
+
+    Inst4_DQSBUFD4: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_4, SCLK=>clkok, READ=>reset_4, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_4, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw4, 
+            DDRCLKPOL=>ddrclkpol4, PRMBDET=>prmbdet4, 
+            DATAVALID=>datavalid4, DDRLAT=>ddrlat4, ECLKDQSR=>eclkdqsr4, 
+            DQCLK0=>dqclk04, DQCLK1=>dqclk14);
+
+    Inst4_DQSBUFD3: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_3, SCLK=>clkok, READ=>reset_3, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_3, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw3, 
+            DDRCLKPOL=>ddrclkpol3, PRMBDET=>prmbdet3, 
+            DATAVALID=>datavalid3, DDRLAT=>ddrlat3, ECLKDQSR=>eclkdqsr3, 
+            DQCLK0=>dqclk03, DQCLK1=>dqclk13);
+
+    Inst4_DQSBUFD2: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_2, SCLK=>clkok, READ=>reset_2, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_2, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw2, 
+            DDRCLKPOL=>ddrclkpol2, PRMBDET=>prmbdet2, 
+            DATAVALID=>datavalid2, DDRLAT=>ddrlat2, ECLKDQSR=>eclkdqsr2, 
+            DQCLK0=>dqclk02, DQCLK1=>dqclk12);
+
+    Inst4_DQSBUFD1: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_1, SCLK=>clkok, READ=>reset_1, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_1, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw1, 
+            DDRCLKPOL=>ddrclkpol1, PRMBDET=>prmbdet1, 
+            DATAVALID=>datavalid1, DDRLAT=>ddrlat1, ECLKDQSR=>eclkdqsr1, 
+            DQCLK0=>dqclk01, DQCLK1=>dqclk11);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    Inst4_DQSBUFD0: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_0, SCLK=>clkok, READ=>reset_0, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_0, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw0, 
+            DDRCLKPOL=>ddrclkpol0, PRMBDET=>prmbdet0, 
+            DATAVALID=>datavalid0, DDRLAT=>ddrlat0, ECLKDQSR=>eclkdqsr0, 
+            DQCLK0=>dqclk00, DQCLK1=>dqclk10);
+
+    Inst3_DQSDLLB: DQSDLLB
+        generic map (LOCK_SENSITIVITY=> "LOW")
+        port map (CLK=>clkos, RST=>dqsdll_reset, 
+            UDDCNTLN=>dqsdll_uddcntln, LOCK=>dqsdll_lock, DQSDEL=>dqsdel);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    Inst2_CLKDIVB: CLKDIVB
+        port map (CLKI=>eclk, RST=>clkdiv_reset, RELEASE=>scuba_vhi, 
+            CDIV1=>cdiv1, CDIV2=>clkok, CDIV4=>cdiv4, CDIV8=>cdiv8);
+
+    Inst1_IB4: IB
+        port map (I=>clk_4, O=>buf_clk_4);
+
+    Inst1_IB3: IB
+        port map (I=>clk_3, O=>buf_clk_3);
+
+    Inst1_IB2: IB
+        port map (I=>clk_2, O=>buf_clk_2);
+
+    Inst1_IB1: IB
+        port map (I=>clk_1, O=>buf_clk_1);
+
+    Inst1_IB0: IB
+        port map (I=>clk_0, O=>buf_clk_0);
+
+    q_4(19) <= qb124;
+    q_4(18) <= qb123;
+    q_4(17) <= qb122;
+    q_4(16) <= qb121;
+    q_4(15) <= qb120;
+    q_4(14) <= qa124;
+    q_4(13) <= qa123;
+    q_4(12) <= qa122;
+    q_4(11) <= qa121;
+    q_4(10) <= qa120;
+    q_4(9) <= qb024;
+    q_4(8) <= qb023;
+    q_4(7) <= qb022;
+    q_4(6) <= qb021;
+    q_4(5) <= qb020;
+    q_4(4) <= qa024;
+    q_4(3) <= qa023;
+    q_4(2) <= qa022;
+    q_4(1) <= qa021;
+    q_4(0) <= qa020;
+    datain_t24 <= datain_4i_t4;
+    datain_t23 <= datain_4i_t3;
+    datain_t22 <= datain_4i_t2;
+    datain_t21 <= datain_4i_t1;
+    datain_t20 <= datain_4i_t0;
+    q_3(19) <= qb119;
+    q_3(18) <= qb118;
+    q_3(17) <= qb117;
+    q_3(16) <= qb116;
+    q_3(15) <= qb115;
+    q_3(14) <= qa119;
+    q_3(13) <= qa118;
+    q_3(12) <= qa117;
+    q_3(11) <= qa116;
+    q_3(10) <= qa115;
+    q_3(9) <= qb019;
+    q_3(8) <= qb018;
+    q_3(7) <= qb017;
+    q_3(6) <= qb016;
+    q_3(5) <= qb015;
+    q_3(4) <= qa019;
+    q_3(3) <= qa018;
+    q_3(2) <= qa017;
+    q_3(1) <= qa016;
+    q_3(0) <= qa015;
+    datain_t19 <= datain_3i_t4;
+    datain_t18 <= datain_3i_t3;
+    datain_t17 <= datain_3i_t2;
+    datain_t16 <= datain_3i_t1;
+    datain_t15 <= datain_3i_t0;
+    q_2(19) <= qb114;
+    q_2(18) <= qb113;
+    q_2(17) <= qb112;
+    q_2(16) <= qb111;
+    q_2(15) <= qb110;
+    q_2(14) <= qa114;
+    q_2(13) <= qa113;
+    q_2(12) <= qa112;
+    q_2(11) <= qa111;
+    q_2(10) <= qa110;
+    q_2(9) <= qb014;
+    q_2(8) <= qb013;
+    q_2(7) <= qb012;
+    q_2(6) <= qb011;
+    q_2(5) <= qb010;
+    q_2(4) <= qa014;
+    q_2(3) <= qa013;
+    q_2(2) <= qa012;
+    q_2(1) <= qa011;
+    q_2(0) <= qa010;
+    datain_t14 <= datain_2i_t4;
+    datain_t13 <= datain_2i_t3;
+    datain_t12 <= datain_2i_t2;
+    datain_t11 <= datain_2i_t1;
+    datain_t10 <= datain_2i_t0;
+    q_1(19) <= qb19;
+    q_1(18) <= qb18;
+    q_1(17) <= qb17;
+    q_1(16) <= qb16;
+    q_1(15) <= qb15;
+    q_1(14) <= qa19;
+    q_1(13) <= qa18;
+    q_1(12) <= qa17;
+    q_1(11) <= qa16;
+    q_1(10) <= qa15;
+    q_1(9) <= qb09;
+    q_1(8) <= qb08;
+    q_1(7) <= qb07;
+    q_1(6) <= qb06;
+    q_1(5) <= qb05;
+    q_1(4) <= qa09;
+    q_1(3) <= qa08;
+    q_1(2) <= qa07;
+    q_1(1) <= qa06;
+    q_1(0) <= qa05;
+    datain_t9 <= datain_1i_t4;
+    datain_t8 <= datain_1i_t3;
+    datain_t7 <= datain_1i_t2;
+    datain_t6 <= datain_1i_t1;
+    datain_t5 <= datain_1i_t0;
+    q_0(19) <= qb14;
+    q_0(18) <= qb13;
+    q_0(17) <= qb12;
+    q_0(16) <= qb11;
+    q_0(15) <= qb10;
+    q_0(14) <= qa14;
+    q_0(13) <= qa13;
+    q_0(12) <= qa12;
+    q_0(11) <= qa11;
+    q_0(10) <= qa10;
+    q_0(9) <= qb04;
+    q_0(8) <= qb03;
+    q_0(7) <= qb02;
+    q_0(6) <= qb01;
+    q_0(5) <= qb00;
+    q_0(4) <= qa04;
+    q_0(3) <= qa03;
+    q_0(2) <= qa02;
+    q_0(1) <= qa01;
+    q_0(0) <= qa00;
+    datain_t4 <= datain_0i_t4;
+    datain_t3 <= datain_0i_t3;
+    datain_t2 <= datain_0i_t2;
+    datain_t1 <= datain_0i_t1;
+    datain_t0 <= datain_0i_t0;
+    dqsdll_uddcntln <= scuba_vhi;
+    dqsdll_reset <= scuba_vhi;
+    clkos <= eclk;
+    sclk_t <= clkok;
+    sclk <= sclk_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of dqsinput_5x5 is
+    for Structure
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:IB use entity ecp3.IB(V); end for;
+        for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for;
+        for all:IDDRX2D use entity ecp3.IDDRX2D(V); end for;
+        for all:DQSBUFD use entity ecp3.DQSBUFD(V); end for;
+        for all:DQSDLLB use entity ecp3.DQSDLLB(V); end for;
+        for all:DELAYC use entity ecp3.DELAYC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/base/cores/dqsinput_7x5.ipx b/base/cores/dqsinput_7x5.ipx
new file mode 100644
index 0000000..8480bed
--- /dev/null
+++ b/base/cores/dqsinput_7x5.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="dqsinput_7x5" module="DDR_GENERIC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 02 03 17:40:31.033" version="5.4" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="dqsinput_7x5.lpc" type="lpc" modified="2014 02 03 17:40:27.000"/>
+		<File name="dqsinput_7x5.vhd" type="top_level_vhdl" modified="2014 02 03 17:40:27.000"/>
+		<File name="dqsinput_7x5_tmpl.vhd" type="template_vhdl" modified="2014 02 03 17:40:27.000"/>
+  </Package>
+</DiamondModule>
diff --git a/base/cores/dqsinput_7x5.lpc b/base/cores/dqsinput_7x5.lpc
new file mode 100644
index 0000000..9edb227
--- /dev/null
+++ b/base/cores/dqsinput_7x5.lpc
@@ -0,0 +1,62 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN672C
+SpeedGrade=6
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=5.4
+ModuleName=dqsinput_7x5
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=02/03/2014
+Time=17:40:27
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Receive
+trioddr=0
+io_type=LVDS25
+num_int=7
+width=5
+freq_in=200
+bandwidth=2000
+aligned=Centered
+pre-configuration=DISABLED
+mode2=Receive
+trioddr2=0
+io_type2=LVDS25
+freq_in2=200
+gear=2x
+aligned2=Centered
+num_int2=7
+width2=5
+Interface=GDDRX2_RX.DQS.Centered
+Delay=Bypass
+Number=7
+dqs1=5
+dqs2=5
+dqs3=5
+dqs4=5
+dqs5=5
+dqs6=5
+dqs7=5
+dqs8=
+val=
+Phase=TRDLLB/DLLDELB
+Divider=CLKDIVB
+Multiplier=2
+PllFreq=100
diff --git a/base/cores/dqsinput_7x5.vhd b/base/cores/dqsinput_7x5.vhd
new file mode 100644
index 0000000..0d9cfe0
--- /dev/null
+++ b/base/cores/dqsinput_7x5.vhd
@@ -0,0 +1,1255 @@
+-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
+-- Module  Version: 5.4
+--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n dqsinput_7x5 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 200 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -dqs 3 5 -dqs 4 5 -dqs 5 5 -dqs 6 5 -dqs 7 5 -e 
+
+-- Mon Feb  3 17:40:27 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity dqsinput_7x5 is
+    port (
+        clk_0: in  std_logic; 
+        clk_1: in  std_logic; 
+        clk_2: in  std_logic; 
+        clk_3: in  std_logic; 
+        clk_4: in  std_logic; 
+        clk_5: in  std_logic; 
+        clk_6: in  std_logic; 
+        clkdiv_reset: in  std_logic; 
+        eclk: in  std_logic; 
+        reset_0: in  std_logic; 
+        reset_1: in  std_logic; 
+        reset_2: in  std_logic; 
+        reset_3: in  std_logic; 
+        reset_4: in  std_logic; 
+        reset_5: in  std_logic; 
+        reset_6: in  std_logic; 
+        sclk: out  std_logic; 
+        datain_0: in  std_logic_vector(4 downto 0); 
+        datain_1: in  std_logic_vector(4 downto 0); 
+        datain_2: in  std_logic_vector(4 downto 0); 
+        datain_3: in  std_logic_vector(4 downto 0); 
+        datain_4: in  std_logic_vector(4 downto 0); 
+        datain_5: in  std_logic_vector(4 downto 0); 
+        datain_6: in  std_logic_vector(4 downto 0); 
+        q_0: out  std_logic_vector(19 downto 0); 
+        q_1: out  std_logic_vector(19 downto 0); 
+        q_2: out  std_logic_vector(19 downto 0); 
+        q_3: out  std_logic_vector(19 downto 0); 
+        q_4: out  std_logic_vector(19 downto 0); 
+        q_5: out  std_logic_vector(19 downto 0); 
+        q_6: out  std_logic_vector(19 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of dqsinput_7x5 : entity is true;
+end dqsinput_7x5;
+
+architecture Structure of dqsinput_7x5 is
+
+    -- internal signal declarations
+    signal datain_6i_t4: std_logic;
+    signal datain_6i_t3: std_logic;
+    signal datain_6i_t2: std_logic;
+    signal datain_6i_t1: std_logic;
+    signal datain_6i_t0: std_logic;
+    signal buf_datain_6i4: std_logic;
+    signal buf_datain_6i3: std_logic;
+    signal buf_datain_6i2: std_logic;
+    signal buf_datain_6i1: std_logic;
+    signal buf_datain_6i0: std_logic;
+    signal datain_5i_t4: std_logic;
+    signal datain_5i_t3: std_logic;
+    signal datain_5i_t2: std_logic;
+    signal datain_5i_t1: std_logic;
+    signal datain_5i_t0: std_logic;
+    signal buf_datain_5i4: std_logic;
+    signal buf_datain_5i3: std_logic;
+    signal buf_datain_5i2: std_logic;
+    signal buf_datain_5i1: std_logic;
+    signal buf_datain_5i0: std_logic;
+    signal datain_4i_t4: std_logic;
+    signal datain_4i_t3: std_logic;
+    signal datain_4i_t2: std_logic;
+    signal datain_4i_t1: std_logic;
+    signal datain_4i_t0: std_logic;
+    signal buf_datain_4i4: std_logic;
+    signal buf_datain_4i3: std_logic;
+    signal buf_datain_4i2: std_logic;
+    signal buf_datain_4i1: std_logic;
+    signal buf_datain_4i0: std_logic;
+    signal datain_3i_t4: std_logic;
+    signal datain_3i_t3: std_logic;
+    signal datain_3i_t2: std_logic;
+    signal datain_3i_t1: std_logic;
+    signal datain_3i_t0: std_logic;
+    signal buf_datain_3i4: std_logic;
+    signal buf_datain_3i3: std_logic;
+    signal buf_datain_3i2: std_logic;
+    signal buf_datain_3i1: std_logic;
+    signal buf_datain_3i0: std_logic;
+    signal datain_2i_t4: std_logic;
+    signal datain_2i_t3: std_logic;
+    signal datain_2i_t2: std_logic;
+    signal datain_2i_t1: std_logic;
+    signal datain_2i_t0: std_logic;
+    signal buf_datain_2i4: std_logic;
+    signal buf_datain_2i3: std_logic;
+    signal buf_datain_2i2: std_logic;
+    signal buf_datain_2i1: std_logic;
+    signal buf_datain_2i0: std_logic;
+    signal datain_1i_t4: std_logic;
+    signal datain_1i_t3: std_logic;
+    signal datain_1i_t2: std_logic;
+    signal datain_1i_t1: std_logic;
+    signal datain_1i_t0: std_logic;
+    signal buf_datain_1i4: std_logic;
+    signal buf_datain_1i3: std_logic;
+    signal buf_datain_1i2: std_logic;
+    signal buf_datain_1i1: std_logic;
+    signal buf_datain_1i0: std_logic;
+    signal datain_0i_t4: std_logic;
+    signal datain_0i_t3: std_logic;
+    signal datain_0i_t2: std_logic;
+    signal datain_0i_t1: std_logic;
+    signal datain_0i_t0: std_logic;
+    signal buf_datain_0i4: std_logic;
+    signal buf_datain_0i3: std_logic;
+    signal buf_datain_0i2: std_logic;
+    signal buf_datain_0i1: std_logic;
+    signal buf_datain_0i0: std_logic;
+    signal qb134: std_logic;
+    signal qa134: std_logic;
+    signal qb034: std_logic;
+    signal qa034: std_logic;
+    signal datain_t34: std_logic;
+    signal qb133: std_logic;
+    signal qa133: std_logic;
+    signal qb033: std_logic;
+    signal qa033: std_logic;
+    signal datain_t33: std_logic;
+    signal qb132: std_logic;
+    signal qa132: std_logic;
+    signal qb032: std_logic;
+    signal qa032: std_logic;
+    signal datain_t32: std_logic;
+    signal qb131: std_logic;
+    signal qa131: std_logic;
+    signal qb031: std_logic;
+    signal qa031: std_logic;
+    signal datain_t31: std_logic;
+    signal qb130: std_logic;
+    signal qa130: std_logic;
+    signal qb030: std_logic;
+    signal qa030: std_logic;
+    signal datain_t30: std_logic;
+    signal qb129: std_logic;
+    signal qa129: std_logic;
+    signal qb029: std_logic;
+    signal qa029: std_logic;
+    signal datain_t29: std_logic;
+    signal qb128: std_logic;
+    signal qa128: std_logic;
+    signal qb028: std_logic;
+    signal qa028: std_logic;
+    signal datain_t28: std_logic;
+    signal qb127: std_logic;
+    signal qa127: std_logic;
+    signal qb027: std_logic;
+    signal qa027: std_logic;
+    signal datain_t27: std_logic;
+    signal qb126: std_logic;
+    signal qa126: std_logic;
+    signal qb026: std_logic;
+    signal qa026: std_logic;
+    signal datain_t26: std_logic;
+    signal qb125: std_logic;
+    signal qa125: std_logic;
+    signal qb025: std_logic;
+    signal qa025: std_logic;
+    signal datain_t25: std_logic;
+    signal qb124: std_logic;
+    signal qa124: std_logic;
+    signal qb024: std_logic;
+    signal qa024: std_logic;
+    signal datain_t24: std_logic;
+    signal qb123: std_logic;
+    signal qa123: std_logic;
+    signal qb023: std_logic;
+    signal qa023: std_logic;
+    signal datain_t23: std_logic;
+    signal qb122: std_logic;
+    signal qa122: std_logic;
+    signal qb022: std_logic;
+    signal qa022: std_logic;
+    signal datain_t22: std_logic;
+    signal qb121: std_logic;
+    signal qa121: std_logic;
+    signal qb021: std_logic;
+    signal qa021: std_logic;
+    signal datain_t21: std_logic;
+    signal qb120: std_logic;
+    signal qa120: std_logic;
+    signal qb020: std_logic;
+    signal qa020: std_logic;
+    signal datain_t20: std_logic;
+    signal qb119: std_logic;
+    signal qa119: std_logic;
+    signal qb019: std_logic;
+    signal qa019: std_logic;
+    signal datain_t19: std_logic;
+    signal qb118: std_logic;
+    signal qa118: std_logic;
+    signal qb018: std_logic;
+    signal qa018: std_logic;
+    signal datain_t18: std_logic;
+    signal qb117: std_logic;
+    signal qa117: std_logic;
+    signal qb017: std_logic;
+    signal qa017: std_logic;
+    signal datain_t17: std_logic;
+    signal qb116: std_logic;
+    signal qa116: std_logic;
+    signal qb016: std_logic;
+    signal qa016: std_logic;
+    signal datain_t16: std_logic;
+    signal qb115: std_logic;
+    signal qa115: std_logic;
+    signal qb015: std_logic;
+    signal qa015: std_logic;
+    signal datain_t15: std_logic;
+    signal qb114: std_logic;
+    signal qa114: std_logic;
+    signal qb014: std_logic;
+    signal qa014: std_logic;
+    signal datain_t14: std_logic;
+    signal qb113: std_logic;
+    signal qa113: std_logic;
+    signal qb013: std_logic;
+    signal qa013: std_logic;
+    signal datain_t13: std_logic;
+    signal qb112: std_logic;
+    signal qa112: std_logic;
+    signal qb012: std_logic;
+    signal qa012: std_logic;
+    signal datain_t12: std_logic;
+    signal qb111: std_logic;
+    signal qa111: std_logic;
+    signal qb011: std_logic;
+    signal qa011: std_logic;
+    signal datain_t11: std_logic;
+    signal qb110: std_logic;
+    signal qa110: std_logic;
+    signal qb010: std_logic;
+    signal qa010: std_logic;
+    signal datain_t10: std_logic;
+    signal qb19: std_logic;
+    signal qa19: std_logic;
+    signal qb09: std_logic;
+    signal qa09: std_logic;
+    signal datain_t9: std_logic;
+    signal qb18: std_logic;
+    signal qa18: std_logic;
+    signal qb08: std_logic;
+    signal qa08: std_logic;
+    signal datain_t8: std_logic;
+    signal qb17: std_logic;
+    signal qa17: std_logic;
+    signal qb07: std_logic;
+    signal qa07: std_logic;
+    signal datain_t7: std_logic;
+    signal qb16: std_logic;
+    signal qa16: std_logic;
+    signal qb06: std_logic;
+    signal qa06: std_logic;
+    signal datain_t6: std_logic;
+    signal qb15: std_logic;
+    signal qa15: std_logic;
+    signal qb05: std_logic;
+    signal qa05: std_logic;
+    signal datain_t5: std_logic;
+    signal qb14: std_logic;
+    signal qa14: std_logic;
+    signal qb04: std_logic;
+    signal qa04: std_logic;
+    signal datain_t4: std_logic;
+    signal qb13: std_logic;
+    signal qa13: std_logic;
+    signal qb03: std_logic;
+    signal qa03: std_logic;
+    signal datain_t3: std_logic;
+    signal qb12: std_logic;
+    signal qa12: std_logic;
+    signal qb02: std_logic;
+    signal qa02: std_logic;
+    signal datain_t2: std_logic;
+    signal qb11: std_logic;
+    signal qa11: std_logic;
+    signal qb01: std_logic;
+    signal qa01: std_logic;
+    signal datain_t1: std_logic;
+    signal qb10: std_logic;
+    signal qa10: std_logic;
+    signal qb00: std_logic;
+    signal qa00: std_logic;
+    signal datain_t0: std_logic;
+    signal dqclk16: std_logic;
+    signal dqclk06: std_logic;
+    signal eclkdqsr6: std_logic;
+    signal ddrlat6: std_logic;
+    signal datavalid6: std_logic;
+    signal prmbdet6: std_logic;
+    signal ddrclkpol6: std_logic;
+    signal dqsw6: std_logic;
+    signal dqclk15: std_logic;
+    signal dqclk05: std_logic;
+    signal eclkdqsr5: std_logic;
+    signal ddrlat5: std_logic;
+    signal datavalid5: std_logic;
+    signal prmbdet5: std_logic;
+    signal ddrclkpol5: std_logic;
+    signal dqsw5: std_logic;
+    signal dqclk14: std_logic;
+    signal dqclk04: std_logic;
+    signal eclkdqsr4: std_logic;
+    signal ddrlat4: std_logic;
+    signal datavalid4: std_logic;
+    signal prmbdet4: std_logic;
+    signal ddrclkpol4: std_logic;
+    signal dqsw4: std_logic;
+    signal dqclk13: std_logic;
+    signal dqclk03: std_logic;
+    signal eclkdqsr3: std_logic;
+    signal ddrlat3: std_logic;
+    signal datavalid3: std_logic;
+    signal prmbdet3: std_logic;
+    signal ddrclkpol3: std_logic;
+    signal dqsw3: std_logic;
+    signal dqclk12: std_logic;
+    signal dqclk02: std_logic;
+    signal eclkdqsr2: std_logic;
+    signal ddrlat2: std_logic;
+    signal datavalid2: std_logic;
+    signal prmbdet2: std_logic;
+    signal ddrclkpol2: std_logic;
+    signal dqsw2: std_logic;
+    signal dqclk11: std_logic;
+    signal dqclk01: std_logic;
+    signal eclkdqsr1: std_logic;
+    signal ddrlat1: std_logic;
+    signal datavalid1: std_logic;
+    signal prmbdet1: std_logic;
+    signal ddrclkpol1: std_logic;
+    signal dqsw1: std_logic;
+    signal dqclk10: std_logic;
+    signal dqclk00: std_logic;
+    signal eclkdqsr0: std_logic;
+    signal ddrlat0: std_logic;
+    signal datavalid0: std_logic;
+    signal prmbdet0: std_logic;
+    signal ddrclkpol0: std_logic;
+    signal dqsw0: std_logic;
+    signal scuba_vlo: std_logic;
+    signal dqsdel: std_logic;
+    signal dqsdll_lock: std_logic;
+    signal dqsdll_uddcntln: std_logic;
+    signal dqsdll_reset: std_logic;
+    signal clkos: std_logic;
+    signal cdiv8: std_logic;
+    signal cdiv4: std_logic;
+    signal cdiv1: std_logic;
+    signal scuba_vhi: std_logic;
+    signal clkok: std_logic;
+    signal buf_clk_6: std_logic;
+    signal buf_clk_5: std_logic;
+    signal buf_clk_4: std_logic;
+    signal buf_clk_3: std_logic;
+    signal buf_clk_2: std_logic;
+    signal buf_clk_1: std_logic;
+    signal buf_clk_0: std_logic;
+    signal sclk_t: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component IB
+        port (I: in  std_logic; O: out  std_logic);
+    end component;
+    component CLKDIVB
+        port (CLKI: in  std_logic; RST: in  std_logic; 
+            RELEASE: in  std_logic; CDIV1: out  std_logic; 
+            CDIV2: out  std_logic; CDIV4: out  std_logic; 
+            CDIV8: out  std_logic);
+    end component;
+    component IDDRX2D
+        generic (DELAYMODE : in String; SCLKLATENCY : in Integer);
+        port (D: in  std_logic; SCLK: in  std_logic; ECLK: in  std_logic; 
+            ECLKDQSR: in  std_logic; DDRLAT: in  std_logic; 
+            DDRCLKPOL: in  std_logic; QA0: out  std_logic; 
+            QB0: out  std_logic; QA1: out  std_logic; 
+            QB1: out  std_logic);
+    end component;
+    component DQSBUFD
+        generic (NRZMODE : in String; DYNDEL_CNTL : in String; 
+                DYNDEL_VAL : in Integer; DYNDEL_TYPE : in String);
+        port (DQSI: in  std_logic; SCLK: in  std_logic; 
+            READ: in  std_logic; DQSDEL: in  std_logic; 
+            ECLK: in  std_logic; ECLKW: in  std_logic; 
+            RST: in  std_logic; DYNDELPOL: in  std_logic; 
+            DYNDELAY6: in  std_logic; DYNDELAY5: in  std_logic; 
+            DYNDELAY4: in  std_logic; DYNDELAY3: in  std_logic; 
+            DYNDELAY2: in  std_logic; DYNDELAY1: in  std_logic; 
+            DYNDELAY0: in  std_logic; DQSW: out  std_logic; 
+            DDRCLKPOL: out  std_logic; PRMBDET: out  std_logic; 
+            DATAVALID: out  std_logic; DDRLAT: out  std_logic; 
+            ECLKDQSR: out  std_logic; DQCLK0: out  std_logic; 
+            DQCLK1: out  std_logic);
+    end component;
+    component DQSDLLB
+        generic (LOCK_SENSITIVITY : in String);
+        port (CLK: in  std_logic; RST: in  std_logic; 
+            UDDCNTLN: in  std_logic; LOCK: out  std_logic; 
+            DQSDEL: out  std_logic);
+    end component;
+    component DELAYC
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    attribute IDDRAPPS : string; 
+    attribute IO_TYPE : string; 
+    attribute IO_TYPE of Inst11_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst11_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst11_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst11_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst11_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst10_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst10_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst10_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst10_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst10_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst9_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst8_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst7_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst6_IB0 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst5_IB0 : label is "LVDS25";
+    attribute IDDRAPPS of Inst_IDDRX2D_6_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_6_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_6_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_6_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_6_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_5_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_5_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_5_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_5_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_5_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_4_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_3_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_2_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_1_0 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_4 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_3 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_2 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_1 : label is "DQS_CENTERED";
+    attribute IDDRAPPS of Inst_IDDRX2D_0_0 : label is "DQS_CENTERED";
+    attribute IO_TYPE of Inst1_IB6 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB5 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB4 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB3 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB2 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB1 : label is "LVDS25";
+    attribute IO_TYPE of Inst1_IB0 : label is "LVDS25";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    udel_datain_6i4: DELAYC
+        port map (A=>buf_datain_6i4, Z=>datain_6i_t4);
+
+    udel_datain_6i3: DELAYC
+        port map (A=>buf_datain_6i3, Z=>datain_6i_t3);
+
+    udel_datain_6i2: DELAYC
+        port map (A=>buf_datain_6i2, Z=>datain_6i_t2);
+
+    udel_datain_6i1: DELAYC
+        port map (A=>buf_datain_6i1, Z=>datain_6i_t1);
+
+    udel_datain_6i0: DELAYC
+        port map (A=>buf_datain_6i0, Z=>datain_6i_t0);
+
+    Inst11_IB4: IB
+        port map (I=>datain_6(4), O=>buf_datain_6i4);
+
+    Inst11_IB3: IB
+        port map (I=>datain_6(3), O=>buf_datain_6i3);
+
+    Inst11_IB2: IB
+        port map (I=>datain_6(2), O=>buf_datain_6i2);
+
+    Inst11_IB1: IB
+        port map (I=>datain_6(1), O=>buf_datain_6i1);
+
+    Inst11_IB0: IB
+        port map (I=>datain_6(0), O=>buf_datain_6i0);
+
+    udel_datain_5i4: DELAYC
+        port map (A=>buf_datain_5i4, Z=>datain_5i_t4);
+
+    udel_datain_5i3: DELAYC
+        port map (A=>buf_datain_5i3, Z=>datain_5i_t3);
+
+    udel_datain_5i2: DELAYC
+        port map (A=>buf_datain_5i2, Z=>datain_5i_t2);
+
+    udel_datain_5i1: DELAYC
+        port map (A=>buf_datain_5i1, Z=>datain_5i_t1);
+
+    udel_datain_5i0: DELAYC
+        port map (A=>buf_datain_5i0, Z=>datain_5i_t0);
+
+    Inst10_IB4: IB
+        port map (I=>datain_5(4), O=>buf_datain_5i4);
+
+    Inst10_IB3: IB
+        port map (I=>datain_5(3), O=>buf_datain_5i3);
+
+    Inst10_IB2: IB
+        port map (I=>datain_5(2), O=>buf_datain_5i2);
+
+    Inst10_IB1: IB
+        port map (I=>datain_5(1), O=>buf_datain_5i1);
+
+    Inst10_IB0: IB
+        port map (I=>datain_5(0), O=>buf_datain_5i0);
+
+    udel_datain_4i4: DELAYC
+        port map (A=>buf_datain_4i4, Z=>datain_4i_t4);
+
+    udel_datain_4i3: DELAYC
+        port map (A=>buf_datain_4i3, Z=>datain_4i_t3);
+
+    udel_datain_4i2: DELAYC
+        port map (A=>buf_datain_4i2, Z=>datain_4i_t2);
+
+    udel_datain_4i1: DELAYC
+        port map (A=>buf_datain_4i1, Z=>datain_4i_t1);
+
+    udel_datain_4i0: DELAYC
+        port map (A=>buf_datain_4i0, Z=>datain_4i_t0);
+
+    Inst9_IB4: IB
+        port map (I=>datain_4(4), O=>buf_datain_4i4);
+
+    Inst9_IB3: IB
+        port map (I=>datain_4(3), O=>buf_datain_4i3);
+
+    Inst9_IB2: IB
+        port map (I=>datain_4(2), O=>buf_datain_4i2);
+
+    Inst9_IB1: IB
+        port map (I=>datain_4(1), O=>buf_datain_4i1);
+
+    Inst9_IB0: IB
+        port map (I=>datain_4(0), O=>buf_datain_4i0);
+
+    udel_datain_3i4: DELAYC
+        port map (A=>buf_datain_3i4, Z=>datain_3i_t4);
+
+    udel_datain_3i3: DELAYC
+        port map (A=>buf_datain_3i3, Z=>datain_3i_t3);
+
+    udel_datain_3i2: DELAYC
+        port map (A=>buf_datain_3i2, Z=>datain_3i_t2);
+
+    udel_datain_3i1: DELAYC
+        port map (A=>buf_datain_3i1, Z=>datain_3i_t1);
+
+    udel_datain_3i0: DELAYC
+        port map (A=>buf_datain_3i0, Z=>datain_3i_t0);
+
+    Inst8_IB4: IB
+        port map (I=>datain_3(4), O=>buf_datain_3i4);
+
+    Inst8_IB3: IB
+        port map (I=>datain_3(3), O=>buf_datain_3i3);
+
+    Inst8_IB2: IB
+        port map (I=>datain_3(2), O=>buf_datain_3i2);
+
+    Inst8_IB1: IB
+        port map (I=>datain_3(1), O=>buf_datain_3i1);
+
+    Inst8_IB0: IB
+        port map (I=>datain_3(0), O=>buf_datain_3i0);
+
+    udel_datain_2i4: DELAYC
+        port map (A=>buf_datain_2i4, Z=>datain_2i_t4);
+
+    udel_datain_2i3: DELAYC
+        port map (A=>buf_datain_2i3, Z=>datain_2i_t3);
+
+    udel_datain_2i2: DELAYC
+        port map (A=>buf_datain_2i2, Z=>datain_2i_t2);
+
+    udel_datain_2i1: DELAYC
+        port map (A=>buf_datain_2i1, Z=>datain_2i_t1);
+
+    udel_datain_2i0: DELAYC
+        port map (A=>buf_datain_2i0, Z=>datain_2i_t0);
+
+    Inst7_IB4: IB
+        port map (I=>datain_2(4), O=>buf_datain_2i4);
+
+    Inst7_IB3: IB
+        port map (I=>datain_2(3), O=>buf_datain_2i3);
+
+    Inst7_IB2: IB
+        port map (I=>datain_2(2), O=>buf_datain_2i2);
+
+    Inst7_IB1: IB
+        port map (I=>datain_2(1), O=>buf_datain_2i1);
+
+    Inst7_IB0: IB
+        port map (I=>datain_2(0), O=>buf_datain_2i0);
+
+    udel_datain_1i4: DELAYC
+        port map (A=>buf_datain_1i4, Z=>datain_1i_t4);
+
+    udel_datain_1i3: DELAYC
+        port map (A=>buf_datain_1i3, Z=>datain_1i_t3);
+
+    udel_datain_1i2: DELAYC
+        port map (A=>buf_datain_1i2, Z=>datain_1i_t2);
+
+    udel_datain_1i1: DELAYC
+        port map (A=>buf_datain_1i1, Z=>datain_1i_t1);
+
+    udel_datain_1i0: DELAYC
+        port map (A=>buf_datain_1i0, Z=>datain_1i_t0);
+
+    Inst6_IB4: IB
+        port map (I=>datain_1(4), O=>buf_datain_1i4);
+
+    Inst6_IB3: IB
+        port map (I=>datain_1(3), O=>buf_datain_1i3);
+
+    Inst6_IB2: IB
+        port map (I=>datain_1(2), O=>buf_datain_1i2);
+
+    Inst6_IB1: IB
+        port map (I=>datain_1(1), O=>buf_datain_1i1);
+
+    Inst6_IB0: IB
+        port map (I=>datain_1(0), O=>buf_datain_1i0);
+
+    udel_datain_0i4: DELAYC
+        port map (A=>buf_datain_0i4, Z=>datain_0i_t4);
+
+    udel_datain_0i3: DELAYC
+        port map (A=>buf_datain_0i3, Z=>datain_0i_t3);
+
+    udel_datain_0i2: DELAYC
+        port map (A=>buf_datain_0i2, Z=>datain_0i_t2);
+
+    udel_datain_0i1: DELAYC
+        port map (A=>buf_datain_0i1, Z=>datain_0i_t1);
+
+    udel_datain_0i0: DELAYC
+        port map (A=>buf_datain_0i0, Z=>datain_0i_t0);
+
+    Inst5_IB4: IB
+        port map (I=>datain_0(4), O=>buf_datain_0i4);
+
+    Inst5_IB3: IB
+        port map (I=>datain_0(3), O=>buf_datain_0i3);
+
+    Inst5_IB2: IB
+        port map (I=>datain_0(2), O=>buf_datain_0i2);
+
+    Inst5_IB1: IB
+        port map (I=>datain_0(1), O=>buf_datain_0i1);
+
+    Inst5_IB0: IB
+        port map (I=>datain_0(0), O=>buf_datain_0i0);
+
+    Inst_IDDRX2D_6_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t34, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr6, DDRLAT=>ddrlat6, DDRCLKPOL=>ddrclkpol6, 
+            QA0=>qa034, QB0=>qb034, QA1=>qa134, QB1=>qb134);
+
+    Inst_IDDRX2D_6_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t33, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr6, DDRLAT=>ddrlat6, DDRCLKPOL=>ddrclkpol6, 
+            QA0=>qa033, QB0=>qb033, QA1=>qa133, QB1=>qb133);
+
+    Inst_IDDRX2D_6_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t32, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr6, DDRLAT=>ddrlat6, DDRCLKPOL=>ddrclkpol6, 
+            QA0=>qa032, QB0=>qb032, QA1=>qa132, QB1=>qb132);
+
+    Inst_IDDRX2D_6_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t31, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr6, DDRLAT=>ddrlat6, DDRCLKPOL=>ddrclkpol6, 
+            QA0=>qa031, QB0=>qb031, QA1=>qa131, QB1=>qb131);
+
+    Inst_IDDRX2D_6_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t30, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr6, DDRLAT=>ddrlat6, DDRCLKPOL=>ddrclkpol6, 
+            QA0=>qa030, QB0=>qb030, QA1=>qa130, QB1=>qb130);
+
+    Inst_IDDRX2D_5_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t29, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, 
+            QA0=>qa029, QB0=>qb029, QA1=>qa129, QB1=>qb129);
+
+    Inst_IDDRX2D_5_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t28, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, 
+            QA0=>qa028, QB0=>qb028, QA1=>qa128, QB1=>qb128);
+
+    Inst_IDDRX2D_5_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t27, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, 
+            QA0=>qa027, QB0=>qb027, QA1=>qa127, QB1=>qb127);
+
+    Inst_IDDRX2D_5_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t26, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, 
+            QA0=>qa026, QB0=>qb026, QA1=>qa126, QB1=>qb126);
+
+    Inst_IDDRX2D_5_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t25, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr5, DDRLAT=>ddrlat5, DDRCLKPOL=>ddrclkpol5, 
+            QA0=>qa025, QB0=>qb025, QA1=>qa125, QB1=>qb125);
+
+    Inst_IDDRX2D_4_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t24, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa024, QB0=>qb024, QA1=>qa124, QB1=>qb124);
+
+    Inst_IDDRX2D_4_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t23, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa023, QB0=>qb023, QA1=>qa123, QB1=>qb123);
+
+    Inst_IDDRX2D_4_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t22, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa022, QB0=>qb022, QA1=>qa122, QB1=>qb122);
+
+    Inst_IDDRX2D_4_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t21, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa021, QB0=>qb021, QA1=>qa121, QB1=>qb121);
+
+    Inst_IDDRX2D_4_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t20, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr4, DDRLAT=>ddrlat4, DDRCLKPOL=>ddrclkpol4, 
+            QA0=>qa020, QB0=>qb020, QA1=>qa120, QB1=>qb120);
+
+    Inst_IDDRX2D_3_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t19, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa019, QB0=>qb019, QA1=>qa119, QB1=>qb119);
+
+    Inst_IDDRX2D_3_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t18, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa018, QB0=>qb018, QA1=>qa118, QB1=>qb118);
+
+    Inst_IDDRX2D_3_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t17, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa017, QB0=>qb017, QA1=>qa117, QB1=>qb117);
+
+    Inst_IDDRX2D_3_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t16, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa016, QB0=>qb016, QA1=>qa116, QB1=>qb116);
+
+    Inst_IDDRX2D_3_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t15, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr3, DDRLAT=>ddrlat3, DDRCLKPOL=>ddrclkpol3, 
+            QA0=>qa015, QB0=>qb015, QA1=>qa115, QB1=>qb115);
+
+    Inst_IDDRX2D_2_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t14, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa014, QB0=>qb014, QA1=>qa114, QB1=>qb114);
+
+    Inst_IDDRX2D_2_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t13, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa013, QB0=>qb013, QA1=>qa113, QB1=>qb113);
+
+    Inst_IDDRX2D_2_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t12, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa012, QB0=>qb012, QA1=>qa112, QB1=>qb112);
+
+    Inst_IDDRX2D_2_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t11, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa011, QB0=>qb011, QA1=>qa111, QB1=>qb111);
+
+    Inst_IDDRX2D_2_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t10, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr2, DDRLAT=>ddrlat2, DDRCLKPOL=>ddrclkpol2, 
+            QA0=>qa010, QB0=>qb010, QA1=>qa110, QB1=>qb110);
+
+    Inst_IDDRX2D_1_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t9, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa09, QB0=>qb09, QA1=>qa19, QB1=>qb19);
+
+    Inst_IDDRX2D_1_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t8, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa08, QB0=>qb08, QA1=>qa18, QB1=>qb18);
+
+    Inst_IDDRX2D_1_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t7, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa07, QB0=>qb07, QA1=>qa17, QB1=>qb17);
+
+    Inst_IDDRX2D_1_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t6, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa06, QB0=>qb06, QA1=>qa16, QB1=>qb16);
+
+    Inst_IDDRX2D_1_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t5, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, 
+            QA0=>qa05, QB0=>qb05, QA1=>qa15, QB1=>qb15);
+
+    Inst_IDDRX2D_0_4: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t4, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa04, QB0=>qb04, QA1=>qa14, QB1=>qb14);
+
+    Inst_IDDRX2D_0_3: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t3, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa03, QB0=>qb03, QA1=>qa13, QB1=>qb13);
+
+    Inst_IDDRX2D_0_2: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t2, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa02, QB0=>qb02, QA1=>qa12, QB1=>qb12);
+
+    Inst_IDDRX2D_0_1: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t1, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa01, QB0=>qb01, QA1=>qa11, QB1=>qb11);
+
+    Inst_IDDRX2D_0_0: IDDRX2D
+        generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=>  1)
+        port map (D=>datain_t0, SCLK=>clkok, ECLK=>clkos, 
+            ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, 
+            QA0=>qa00, QB0=>qb00, QA1=>qa10, QB1=>qb10);
+
+    Inst4_DQSBUFD6: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_6, SCLK=>clkok, READ=>reset_6, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_6, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw6, 
+            DDRCLKPOL=>ddrclkpol6, PRMBDET=>prmbdet6, 
+            DATAVALID=>datavalid6, DDRLAT=>ddrlat6, ECLKDQSR=>eclkdqsr6, 
+            DQCLK0=>dqclk06, DQCLK1=>dqclk16);
+
+    Inst4_DQSBUFD5: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_5, SCLK=>clkok, READ=>reset_5, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_5, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw5, 
+            DDRCLKPOL=>ddrclkpol5, PRMBDET=>prmbdet5, 
+            DATAVALID=>datavalid5, DDRLAT=>ddrlat5, ECLKDQSR=>eclkdqsr5, 
+            DQCLK0=>dqclk05, DQCLK1=>dqclk15);
+
+    Inst4_DQSBUFD4: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_4, SCLK=>clkok, READ=>reset_4, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_4, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw4, 
+            DDRCLKPOL=>ddrclkpol4, PRMBDET=>prmbdet4, 
+            DATAVALID=>datavalid4, DDRLAT=>ddrlat4, ECLKDQSR=>eclkdqsr4, 
+            DQCLK0=>dqclk04, DQCLK1=>dqclk14);
+
+    Inst4_DQSBUFD3: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_3, SCLK=>clkok, READ=>reset_3, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_3, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw3, 
+            DDRCLKPOL=>ddrclkpol3, PRMBDET=>prmbdet3, 
+            DATAVALID=>datavalid3, DDRLAT=>ddrlat3, ECLKDQSR=>eclkdqsr3, 
+            DQCLK0=>dqclk03, DQCLK1=>dqclk13);
+
+    Inst4_DQSBUFD2: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_2, SCLK=>clkok, READ=>reset_2, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_2, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw2, 
+            DDRCLKPOL=>ddrclkpol2, PRMBDET=>prmbdet2, 
+            DATAVALID=>datavalid2, DDRLAT=>ddrlat2, ECLKDQSR=>eclkdqsr2, 
+            DQCLK0=>dqclk02, DQCLK1=>dqclk12);
+
+    Inst4_DQSBUFD1: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_1, SCLK=>clkok, READ=>reset_1, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_1, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw1, 
+            DDRCLKPOL=>ddrclkpol1, PRMBDET=>prmbdet1, 
+            DATAVALID=>datavalid1, DDRLAT=>ddrlat1, ECLKDQSR=>eclkdqsr1, 
+            DQCLK0=>dqclk01, DQCLK1=>dqclk11);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    Inst4_DQSBUFD0: DQSBUFD
+        generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=>  0, DYNDEL_CNTL=> "DYNAMIC", 
+        DYNDEL_TYPE=> "NORMAL")
+        port map (DQSI=>buf_clk_0, SCLK=>clkok, READ=>reset_0, 
+            DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_0, 
+            DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, 
+            DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, 
+            DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, 
+            DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw0, 
+            DDRCLKPOL=>ddrclkpol0, PRMBDET=>prmbdet0, 
+            DATAVALID=>datavalid0, DDRLAT=>ddrlat0, ECLKDQSR=>eclkdqsr0, 
+            DQCLK0=>dqclk00, DQCLK1=>dqclk10);
+
+    Inst3_DQSDLLB: DQSDLLB
+        generic map (LOCK_SENSITIVITY=> "LOW")
+        port map (CLK=>clkos, RST=>dqsdll_reset, 
+            UDDCNTLN=>dqsdll_uddcntln, LOCK=>dqsdll_lock, DQSDEL=>dqsdel);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    Inst2_CLKDIVB: CLKDIVB
+        port map (CLKI=>eclk, RST=>clkdiv_reset, RELEASE=>scuba_vhi, 
+            CDIV1=>cdiv1, CDIV2=>clkok, CDIV4=>cdiv4, CDIV8=>cdiv8);
+
+    Inst1_IB6: IB
+        port map (I=>clk_6, O=>buf_clk_6);
+
+    Inst1_IB5: IB
+        port map (I=>clk_5, O=>buf_clk_5);
+
+    Inst1_IB4: IB
+        port map (I=>clk_4, O=>buf_clk_4);
+
+    Inst1_IB3: IB
+        port map (I=>clk_3, O=>buf_clk_3);
+
+    Inst1_IB2: IB
+        port map (I=>clk_2, O=>buf_clk_2);
+
+    Inst1_IB1: IB
+        port map (I=>clk_1, O=>buf_clk_1);
+
+    Inst1_IB0: IB
+        port map (I=>clk_0, O=>buf_clk_0);
+
+    q_6(19) <= qb134;
+    q_6(18) <= qb133;
+    q_6(17) <= qb132;
+    q_6(16) <= qb131;
+    q_6(15) <= qb130;
+    q_6(14) <= qa134;
+    q_6(13) <= qa133;
+    q_6(12) <= qa132;
+    q_6(11) <= qa131;
+    q_6(10) <= qa130;
+    q_6(9) <= qb034;
+    q_6(8) <= qb033;
+    q_6(7) <= qb032;
+    q_6(6) <= qb031;
+    q_6(5) <= qb030;
+    q_6(4) <= qa034;
+    q_6(3) <= qa033;
+    q_6(2) <= qa032;
+    q_6(1) <= qa031;
+    q_6(0) <= qa030;
+    datain_t34 <= datain_6i_t4;
+    datain_t33 <= datain_6i_t3;
+    datain_t32 <= datain_6i_t2;
+    datain_t31 <= datain_6i_t1;
+    datain_t30 <= datain_6i_t0;
+    q_5(19) <= qb129;
+    q_5(18) <= qb128;
+    q_5(17) <= qb127;
+    q_5(16) <= qb126;
+    q_5(15) <= qb125;
+    q_5(14) <= qa129;
+    q_5(13) <= qa128;
+    q_5(12) <= qa127;
+    q_5(11) <= qa126;
+    q_5(10) <= qa125;
+    q_5(9) <= qb029;
+    q_5(8) <= qb028;
+    q_5(7) <= qb027;
+    q_5(6) <= qb026;
+    q_5(5) <= qb025;
+    q_5(4) <= qa029;
+    q_5(3) <= qa028;
+    q_5(2) <= qa027;
+    q_5(1) <= qa026;
+    q_5(0) <= qa025;
+    datain_t29 <= datain_5i_t4;
+    datain_t28 <= datain_5i_t3;
+    datain_t27 <= datain_5i_t2;
+    datain_t26 <= datain_5i_t1;
+    datain_t25 <= datain_5i_t0;
+    q_4(19) <= qb124;
+    q_4(18) <= qb123;
+    q_4(17) <= qb122;
+    q_4(16) <= qb121;
+    q_4(15) <= qb120;
+    q_4(14) <= qa124;
+    q_4(13) <= qa123;
+    q_4(12) <= qa122;
+    q_4(11) <= qa121;
+    q_4(10) <= qa120;
+    q_4(9) <= qb024;
+    q_4(8) <= qb023;
+    q_4(7) <= qb022;
+    q_4(6) <= qb021;
+    q_4(5) <= qb020;
+    q_4(4) <= qa024;
+    q_4(3) <= qa023;
+    q_4(2) <= qa022;
+    q_4(1) <= qa021;
+    q_4(0) <= qa020;
+    datain_t24 <= datain_4i_t4;
+    datain_t23 <= datain_4i_t3;
+    datain_t22 <= datain_4i_t2;
+    datain_t21 <= datain_4i_t1;
+    datain_t20 <= datain_4i_t0;
+    q_3(19) <= qb119;
+    q_3(18) <= qb118;
+    q_3(17) <= qb117;
+    q_3(16) <= qb116;
+    q_3(15) <= qb115;
+    q_3(14) <= qa119;
+    q_3(13) <= qa118;
+    q_3(12) <= qa117;
+    q_3(11) <= qa116;
+    q_3(10) <= qa115;
+    q_3(9) <= qb019;
+    q_3(8) <= qb018;
+    q_3(7) <= qb017;
+    q_3(6) <= qb016;
+    q_3(5) <= qb015;
+    q_3(4) <= qa019;
+    q_3(3) <= qa018;
+    q_3(2) <= qa017;
+    q_3(1) <= qa016;
+    q_3(0) <= qa015;
+    datain_t19 <= datain_3i_t4;
+    datain_t18 <= datain_3i_t3;
+    datain_t17 <= datain_3i_t2;
+    datain_t16 <= datain_3i_t1;
+    datain_t15 <= datain_3i_t0;
+    q_2(19) <= qb114;
+    q_2(18) <= qb113;
+    q_2(17) <= qb112;
+    q_2(16) <= qb111;
+    q_2(15) <= qb110;
+    q_2(14) <= qa114;
+    q_2(13) <= qa113;
+    q_2(12) <= qa112;
+    q_2(11) <= qa111;
+    q_2(10) <= qa110;
+    q_2(9) <= qb014;
+    q_2(8) <= qb013;
+    q_2(7) <= qb012;
+    q_2(6) <= qb011;
+    q_2(5) <= qb010;
+    q_2(4) <= qa014;
+    q_2(3) <= qa013;
+    q_2(2) <= qa012;
+    q_2(1) <= qa011;
+    q_2(0) <= qa010;
+    datain_t14 <= datain_2i_t4;
+    datain_t13 <= datain_2i_t3;
+    datain_t12 <= datain_2i_t2;
+    datain_t11 <= datain_2i_t1;
+    datain_t10 <= datain_2i_t0;
+    q_1(19) <= qb19;
+    q_1(18) <= qb18;
+    q_1(17) <= qb17;
+    q_1(16) <= qb16;
+    q_1(15) <= qb15;
+    q_1(14) <= qa19;
+    q_1(13) <= qa18;
+    q_1(12) <= qa17;
+    q_1(11) <= qa16;
+    q_1(10) <= qa15;
+    q_1(9) <= qb09;
+    q_1(8) <= qb08;
+    q_1(7) <= qb07;
+    q_1(6) <= qb06;
+    q_1(5) <= qb05;
+    q_1(4) <= qa09;
+    q_1(3) <= qa08;
+    q_1(2) <= qa07;
+    q_1(1) <= qa06;
+    q_1(0) <= qa05;
+    datain_t9 <= datain_1i_t4;
+    datain_t8 <= datain_1i_t3;
+    datain_t7 <= datain_1i_t2;
+    datain_t6 <= datain_1i_t1;
+    datain_t5 <= datain_1i_t0;
+    q_0(19) <= qb14;
+    q_0(18) <= qb13;
+    q_0(17) <= qb12;
+    q_0(16) <= qb11;
+    q_0(15) <= qb10;
+    q_0(14) <= qa14;
+    q_0(13) <= qa13;
+    q_0(12) <= qa12;
+    q_0(11) <= qa11;
+    q_0(10) <= qa10;
+    q_0(9) <= qb04;
+    q_0(8) <= qb03;
+    q_0(7) <= qb02;
+    q_0(6) <= qb01;
+    q_0(5) <= qb00;
+    q_0(4) <= qa04;
+    q_0(3) <= qa03;
+    q_0(2) <= qa02;
+    q_0(1) <= qa01;
+    q_0(0) <= qa00;
+    datain_t4 <= datain_0i_t4;
+    datain_t3 <= datain_0i_t3;
+    datain_t2 <= datain_0i_t2;
+    datain_t1 <= datain_0i_t1;
+    datain_t0 <= datain_0i_t0;
+    dqsdll_uddcntln <= scuba_vhi;
+    dqsdll_reset <= scuba_vhi;
+    clkos <= eclk;
+    sclk_t <= clkok;
+    sclk <= sclk_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of dqsinput_7x5 is
+    for Structure
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:IB use entity ecp3.IB(V); end for;
+        for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for;
+        for all:IDDRX2D use entity ecp3.IDDRX2D(V); end for;
+        for all:DQSBUFD use entity ecp3.DQSBUFD(V); end for;
+        for all:DQSDLLB use entity ecp3.DQSDLLB(V); end for;
+        for all:DELAYC use entity ecp3.DELAYC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/base/cores/pll_adc10bit.ipx b/base/cores/pll_adc10bit.ipx
new file mode 100644
index 0000000..aacefcf
--- /dev/null
+++ b/base/cores/pll_adc10bit.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_adc10bit" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 31 19:35:11.856" version="5.4" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+		<File name="pll_adc10bit.lpc" type="lpc" modified="2014 01 31 19:35:08.000"/>
+		<File name="pll_adc10bit.vhd" type="top_level_vhdl" modified="2014 01 31 19:35:08.000"/>
+		<File name="pll_adc10bit_tmpl.vhd" type="template_vhdl" modified="2014 01 31 19:35:08.000"/>
+  </Package>
+</DiamondModule>
diff --git a/base/cores/pll_adc10bit.lpc b/base/cores/pll_adc10bit.lpc
new file mode 100644
index 0000000..5597794
--- /dev/null
+++ b/base/cores/pll_adc10bit.lpc
@@ -0,0 +1,66 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN1156C
+SpeedGrade=6
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.4
+ModuleName=pll_adc10bit
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=01/31/2014
+Time=19:35:08
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=16
+U_OFrq=40
+OP_Tol=0.0
+OFrq=40.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=1
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=6
+U_KFrq=40
+OK_Tol=10.0
+KFrq=33.333333
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.191564
+;DelayControl=No
+EnCLKOS=1
+ClkOSBp=1
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
diff --git a/base/cores/pll_adc10bit.vhd b/base/cores/pll_adc10bit.vhd
new file mode 100644
index 0000000..6f6c93a
--- /dev/null
+++ b/base/cores/pll_adc10bit.vhd
@@ -0,0 +1,103 @@
+-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
+-- Module  Version: 5.4
+--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 40 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -noclkok -norst -noclkok2 -bw -e 
+
+-- Fri Jan 31 19:35:08 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_adc10bit is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        CLKOS: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_adc10bit : entity is true;
+end pll_adc10bit;
+
+architecture Structure of pll_adc10bit is
+
+    -- internal signal declarations
+    signal CLKOS_t: std_logic;
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "40.000000";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", 
+        DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, CLKOS_TRIM_DELAY=>  0, 
+        CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  16, CLKFB_DIV=>  1, CLKI_DIV=>  5, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>CLKOS_t, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>open);
+
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_adc10bit is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/base/trb3_periph_adc.lpf b/base/trb3_periph_adc.lpf
new file mode 100644
index 0000000..26def7a
--- /dev/null
+++ b/base/trb3_periph_adc.lpf
@@ -0,0 +1,200 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+
+#################################################################
+# Basic Settings
+#################################################################
+
+SYSCONFIG MCCLK_FREQ = 20;
+
+FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
+LOCATE COMP  "CLK_GPLL_RIGHT"       SITE "W1";
+LOCATE COMP  "CLK_PCLK_LEFT"        SITE "M4";
+LOCATE COMP  "CLK_PCLK_RIGHT"       SITE "U20";
+LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
+LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
+
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25 ;
+
+#################################################################
+# Trigger I/O
+#################################################################
+
+#Trigger from fan-out
+LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
+IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25; 
+
+LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
+IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25;
+
+#################################################################
+# To central FPGA
+#################################################################
+
+LOCATE COMP  "FPGA5_COMM_0"   SITE "AD4";
+LOCATE COMP  "FPGA5_COMM_1"   SITE "AE3";
+LOCATE COMP  "FPGA5_COMM_2"   SITE "AA7";
+LOCATE COMP  "FPGA5_COMM_3"   SITE "AB7";
+LOCATE COMP  "FPGA5_COMM_4"   SITE "AD3";
+LOCATE COMP  "FPGA5_COMM_5"   SITE "AC4";
+LOCATE COMP  "FPGA5_COMM_6"   SITE "AE2";
+LOCATE COMP  "FPGA5_COMM_7"   SITE "AF3";
+LOCATE COMP  "FPGA5_COMM_8"   SITE "AE4";
+LOCATE COMP  "FPGA5_COMM_9"   SITE "AF4";
+LOCATE COMP  "FPGA5_COMM_10"  SITE "V10";
+LOCATE COMP  "FPGA5_COMM_11"  SITE "W10";
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+LOCATE COMP  "TEST_LINE_0"   SITE "A5";
+LOCATE COMP  "TEST_LINE_1"   SITE "A6";
+LOCATE COMP  "TEST_LINE_2"   SITE "G8";
+LOCATE COMP  "TEST_LINE_3"   SITE "F9";
+LOCATE COMP  "TEST_LINE_4"   SITE "D9";
+LOCATE COMP  "TEST_LINE_5"   SITE "D10";
+LOCATE COMP  "TEST_LINE_6"   SITE "F10";
+LOCATE COMP  "TEST_LINE_7"   SITE "E10";
+LOCATE COMP  "TEST_LINE_8"   SITE "A8";
+LOCATE COMP  "TEST_LINE_9"   SITE "B8";
+LOCATE COMP  "TEST_LINE_10"  SITE "G10";
+LOCATE COMP  "TEST_LINE_11"  SITE "G9";
+LOCATE COMP  "TEST_LINE_12"  SITE "C9";
+LOCATE COMP  "TEST_LINE_13"  SITE "C10";
+LOCATE COMP  "TEST_LINE_14"  SITE "H10";
+LOCATE COMP  "TEST_LINE_15"  SITE "H11";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+
+#################################################################
+# ADC INPUTS
+#################################################################
+
+
+LOCATE COMP  "ADC1_CH_0"              SITE "P1";
+LOCATE COMP  "ADC1_CH_1"              SITE "T2";
+LOCATE COMP  "ADC1_CH_2"              SITE "R1";
+LOCATE COMP  "ADC1_CH_3"              SITE "P5";
+LOCATE COMP  "ADC_DCO_1"              SITE "N3";
+LOCATE COMP  "ADC1_CH_4"              SITE "N5";
+
+LOCATE COMP  "ADC2_CH_0"              SITE "AD1";
+LOCATE COMP  "ADC2_CH_1"              SITE "AB5";
+LOCATE COMP  "ADC2_CH_2"              SITE "AB3";
+LOCATE COMP  "ADC2_CH_3"              SITE "AA3";
+LOCATE COMP  "ADC_DCO_2"              SITE "Y6";
+LOCATE COMP  "ADC2_CH_4"              SITE "W8";
+
+LOCATE COMP  "ADC3_CH_0"              SITE "AC2";
+LOCATE COMP  "ADC3_CH_1"              SITE "AB1";
+LOCATE COMP  "ADC3_CH_2"              SITE "AA1";
+LOCATE COMP  "ADC3_CH_3"              SITE "Y5";
+LOCATE COMP  "ADC_DCO_3"              SITE "W7";
+LOCATE COMP  "ADC3_CH_4"              SITE "V6";
+
+LOCATE COMP  "ADC4_CH_0"              SITE "V1";
+LOCATE COMP  "ADC4_CH_1"              SITE "T1";
+LOCATE COMP  "ADC4_CH_2"              SITE "P4";
+LOCATE COMP  "ADC4_CH_3"              SITE "R5";
+LOCATE COMP  "ADC_DCO_4"              SITE "T3";
+LOCATE COMP  "ADC4_CH_4"              SITE "T7";
+
+LOCATE COMP  "ADC5_CH_0"              SITE "K2";
+LOCATE COMP  "ADC5_CH_1"              SITE "J4";
+LOCATE COMP  "ADC5_CH_2"              SITE "D1";
+LOCATE COMP  "ADC5_CH_3"              SITE "E1";
+LOCATE COMP  "ADC_DCO_5"              SITE "K4";
+LOCATE COMP  "ADC5_CH_4"              SITE "L5";
+
+LOCATE COMP  "ADC6_CH_0"              SITE "B2";
+LOCATE COMP  "ADC6_CH_1"              SITE "D4";
+LOCATE COMP  "ADC6_CH_2"              SITE "C3";
+LOCATE COMP  "ADC6_CH_3"              SITE "E3";
+LOCATE COMP  "ADC_DCO_6"              SITE "G5";
+LOCATE COMP  "ADC6_CH_4"              SITE "H6";
+
+LOCATE COMP  "ADC7_CH_0"              SITE "G2";
+LOCATE COMP  "ADC7_CH_1"              SITE "F2";
+LOCATE COMP  "ADC7_CH_2"              SITE "C2";
+LOCATE COMP  "ADC7_CH_3"              SITE "H5";
+LOCATE COMP  "ADC_DCO_7"              SITE "K7";
+LOCATE COMP  "ADC7_CH_4"              SITE "K8";
+
+LOCATE COMP  "ADC8_CH_0"              SITE "W23";
+LOCATE COMP  "ADC8_CH_1"              SITE "AA25";
+LOCATE COMP  "ADC8_CH_2"              SITE "AA26";
+LOCATE COMP  "ADC8_CH_3"              SITE "AA24";
+LOCATE COMP  "ADC_DCO_8"              SITE "W21";
+LOCATE COMP  "ADC8_CH_4"              SITE "AD26";
+
+LOCATE COMP  "ADC9_CH_0"              SITE "AC26";
+LOCATE COMP  "ADC9_CH_1"              SITE "Y19";
+LOCATE COMP  "ADC9_CH_2"              SITE "AB24";
+LOCATE COMP  "ADC9_CH_3"              SITE "AD24";
+LOCATE COMP  "ADC_DCO_9"              SITE "Y22";
+LOCATE COMP  "ADC9_CH_4"              SITE "AE25";
+
+LOCATE COMP  "ADC10_CH_0"             SITE "H24";
+LOCATE COMP  "ADC10_CH_1"             SITE "L20";
+LOCATE COMP  "ADC10_CH_2"             SITE "K24";
+LOCATE COMP  "ADC10_CH_3"             SITE "L24";
+LOCATE COMP  "ADC_DCO_10"             SITE "M23";
+LOCATE COMP  "ADC10_CH_4"             SITE "M22";
+
+LOCATE COMP  "ADC11_CH_0"             SITE "J26";
+LOCATE COMP  "ADC11_CH_1"             SITE "N23";
+LOCATE COMP  "ADC11_CH_2"             SITE "K19";
+LOCATE COMP  "ADC11_CH_3"             SITE "L25";
+LOCATE COMP  "ADC_DCO_11"             SITE "P23";
+LOCATE COMP  "ADC11_CH_4"             SITE "P21";
+
+LOCATE COMP  "ADC12_CH_0"             SITE "J23";   
+LOCATE COMP  "ADC12_CH_1"             SITE "G26";   
+LOCATE COMP  "ADC12_CH_2"             SITE "H26";   
+LOCATE COMP  "ADC12_CH_3"             SITE "K23";   
+LOCATE COMP  "ADC_DCO_12"             SITE "F24";   
+LOCATE COMP  "ADC12_CH_4"             SITE "F25";   
+
+DEFINE PORT GROUP "ADC_group" "ADC*" ;
+IOBUF GROUP "ADC_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+
+LOCATE COMP  "SPI_ADC_SCK"                 SITE "V22";
+LOCATE COMP  "SPI_ADC_SDIO"                SITE "V21";
+DEFINE PORT GROUP "SPI_ADC_group" "SPI_ADC*" ;
+IOBUF GROUP "SPI_ADC_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+
+LOCATE COMP  "LMK_CLK"                 SITE "M5";
+LOCATE COMP  "LMK_DATA"                SITE "T26";
+LOCATE COMP  "LMK_LE_1"                SITE "M6";
+LOCATE COMP  "LMK_LE_2"                SITE "L2";
+DEFINE PORT GROUP "LMK_group" "LMK*" ;
+IOBUF GROUP "LMK_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+LOCATE COMP  "POWER_ENABLE"            SITE "L1";
+IOBUF  PORT  "POWER_ENABLE" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
+
+LOCATE COMP  "P_CLOCK"                SITE "K3";
+IOBUF  PORT  "P_CLOCK" IO_TYPE=LVDS25  ;
+
+LOCATE COMP  "FPGA_CS_0"             SITE "U23";
+LOCATE COMP  "FPGA_CS_1"             SITE "U22";
+LOCATE COMP  "FPGA_SCK_0"            SITE "U24";
+LOCATE COMP  "FPGA_SCK_1"            SITE "V24";
+LOCATE COMP  "FPGA_SDI_0"            SITE "H2";
+LOCATE COMP  "FPGA_SDI_1"            SITE "G1";
+LOCATE COMP  "FPGA_SDO_0"            SITE "T25";
+LOCATE COMP  "FPGA_SDO_1"            SITE "T24";
+DEFINE PORT GROUP "FPGA_group" "FPGA_*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN;