From: Jan Michel <michel@physik.uni-frankfurt.de>
Date: Fri, 23 May 2025 08:36:30 +0000 (+0200)
Subject: add saving of hits exceeding maxToT
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=91bc4a8a7f054fb165fdc10621622b641edf3c39;p=clocked_tdc.git

add saving of hits exceeding maxToT
fix detection of short spikes between 8 and 16 bins
---

diff --git a/code/Decoder.vhd b/code/Decoder.vhd
index 267869f..eb5050b 100644
--- a/code/Decoder.vhd
+++ b/code/Decoder.vhd
@@ -27,7 +27,7 @@ architecture arch of Decoder is
   signal final_cycle           : std_logic;
   signal final    : std_logic_vector(8 downto 0);
   signal finetime : std_logic_vector(5 downto 0); -- edge, error, fine_4
-  
+  signal final_short           : std_logic;
 
 begin
 
@@ -42,9 +42,11 @@ PROC_SELECT : process begin
   if (TDCregs_slow(8) xor TDCregs_slow(0)) = '1' then
     final <= TDCregs_slow(8 downto 0);
     final_cycle <= '0';
+    final_short <= not (TDCregs_slow(0) xor TDCregs_slow(16));
   else
     final <= TDCregs_slow(16 downto 8);
     final_cycle <= '1';
+    final_short <= '0';
   end if;
 end process;
 
@@ -54,6 +56,7 @@ PROC_DECODE : process begin
   
   
   finetime(3) <= final_cycle; --4th Bit
+  finetime(4) <= final_short; --only valid if valid;
   finetime(5) <= final(8); --Edge
   HIT_VALID <= final(8) xor final(0); --Valid
   
@@ -69,6 +72,7 @@ PROC_DECODE : process begin
     when others => finetime(4) <= '1';  --Error
   end case;
   
+
 end process;      
 
 HIT_OUT <= finetime;
diff --git a/code/HitBuffer.vhd b/code/HitBuffer.vhd
index 97805f4..b035997 100644
--- a/code/HitBuffer.vhd
+++ b/code/HitBuffer.vhd
@@ -20,6 +20,7 @@ entity HitBuffer is
     READOUT_ACTIVE : in std_logic;
     SPIKE_SETTING  : in unsigned(3 downto 0);
     MAXTOT_SETTING : in unsigned(7 downto 0);
+    WRITE_LONG_TOT : in std_logic;
     
     DATA_OUT   : out std_logic_vector(27 downto 0);
     DATA_VALID : out std_logic;
@@ -113,11 +114,20 @@ PROC_BUILD_HIT : process begin
     maxtot_timer <= maxtot_timer - 1;
   else   
     edge_rising_valid <= '0';
-    -- if edge_rising_valid = '1' then
-    --   count_edges3 <= count_edges3 + 1;
-    -- end if;
   end if;  
   
+  if READOUT_ACTIVE = '1' then
+    maxtot_timer <= x"00";
+  end if;
+  
+  if maxtot_timer = x"01" then
+    full_hit <= x"00" & '0' & edge_rising_error & edge_rising(12 downto 0) & std_logic_vector(unsigned(edge_rising(12 downto 0))+("0"&MAXTOT_SETTING&"1111"));
+    if READOUT_ACTIVE = '0' and WRITE_LONG_TOT = '1' and edge_rising_error = '0' and edge_rising_valid = '1' then
+      hit_buffer_write <= '1';
+    end if;
+    edge_rising_valid <= '0';  
+    spike_timer       <= x"0";    
+  end if;
   
   if cdc_valid = '1' and cdc_data(5) = '1' then
     edge_rising  <= '1' & cdc_data(4) & '0' & cdc_data(14 downto 6) & cdc_data(3 downto 0);
@@ -133,6 +143,9 @@ PROC_BUILD_HIT : process begin
     elsif spike_timer /= x"0" then
       count_spike_en <= '1';
     end if;  
+    maxtot_timer <= x"00";
+    spike_timer  <= x"0";
+        
     if cdc_data_error = '1' or edge_rising_error = '1' then
       count_edges4 <= count_edges4 + 1;
     end if;
@@ -140,6 +153,8 @@ PROC_BUILD_HIT : process begin
 
   if cdc_valid = '1' and cdc_data(5) = '0' and edge_rising_valid = '0' then
     count_edges4 <= count_edges4 + 1;
+    maxtot_timer <= x"00";
+    spike_timer  <= x"0";
   end if;
   
 
diff --git a/code/TDC_FF.vhd b/code/TDC_FF.vhd
index 8f48cea..3ad8357 100644
--- a/code/TDC_FF.vhd
+++ b/code/TDC_FF.vhd
@@ -54,6 +54,7 @@ signal hitbuffer_status : status_t;
 signal CONF_enable : std_logic_vector(31 downto 0) := (others => '1');
 signal CONF_configure : std_logic_vector(31 downto 0) := x"01139301";
 alias CONF_externalcalibration : std_logic is CONF_configure(0);
+alias CONF_write_long_tot      : std_logic is CONF_configure(1);
 alias CONF_SPIKE               : std_logic_vector(3 downto 0) is CONF_configure(11 downto 8);
 alias CONF_window              : std_logic_vector(8 downto 0) is CONF_configure(20 downto 12);
 alias CONF_windowafter         : std_logic_vector(7 downto 0) is CONF_configure(31 downto 24);
@@ -132,6 +133,7 @@ gen_CHANNELS : for i in 0 to NUM_CHANNELS-1 generate
       READOUT_ACTIVE => readout_active_i(i/16),
       SPIKE_SETTING  => unsigned(CONF_SPIKE),
       MAXTOT_SETTING => unsigned(CONF_maxTot),
+      WRITE_LONG_TOT => CONF_write_long_tot,
       
       DATA_OUT       => tdc_data(i),
       DATA_VALID     => tdc_data_valid(i),