From: hadeshyp Date: Tue, 20 Mar 2012 12:03:29 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=91d9541c4605269373e715aa26600005301ce6e5;p=daqdocu.git *** empty log message *** --- diff --git a/hubs.tex b/hubs.tex index aec031d..5a7e381 100755 --- a/hubs.tex +++ b/hubs.tex @@ -30,6 +30,8 @@ \item[0x88 - 0x8B: Timeouts $\dagger$] One register for each TrbNet channel. Each bit gives the status of one port: 1 if there was a timeout on this port, 0 otherwise. These registers are cleared after being read. If a bit in these registers is set, it also causes the corresponding link LED to flash (approx. 2 Hz, 25\% off). \item[0x8C - 0x8F: Waiting for ACK] One register for each TrbNet channel. Each bit gives the status of one port: 1 if data transmission on this port is stopped because the receiver did not acknowledge previous EOB words, 0 otherwise. \item[0x90: Link error status] One bit for each port. 0 if normal operation / inactive, 1 in cave of error (e.g. code violation). + \item[0x98 - 0x99: Hub Logic Status] Hub Status register. 16 Bit per channel + \item[0x9F IPU Mismatch] Data channel mismatch (of trigger number, trigger info or trigger count). One bit per port \item[0xA0 -- 0xA3: Error-/Status-Bits $\dagger$] One register for each TrbNet channel. Each register is the last Error-/Status-Bits, combined from all ports. \item[0xA4: Slow Control Error $\dagger$] One bit for each port. 1 if either one of the Errorbits 1,3,6 on the slow control channel have been set before. This register is cleared after being read. \item[0xA5: Endpoint reached] One bit for each port. 1 if this port returned the ``Endpoint reached'' bit in the status word set in the last slow control access, 0 otherwise. This information can be used to track a single board in the network: First a read access using the network address of the selected board has to be done. Immediately afterward this register can be read. To secure this non-atomic operation, the register is only updated if the board also return the ``don't understand' bit, e.g. after a read memory access to register 0. diff --git a/networkaddresses.tex b/networkaddresses.tex index 67e1a75..608a2ef 100755 --- a/networkaddresses.tex +++ b/networkaddresses.tex @@ -25,8 +25,8 @@ On boards with two or more FPGAs each FPGA gets its own address. The FPGA provid 5555 & SEB & Dummy Address used in headers generated by SubEventBuilders \\ 8000 - 80FF & Central Hub & central hub\\ 8100 - 81FF & MDC Hub & Hub for inner MDC (3rd digit 0) or outer MDC (3rd digit 1)\\ -8300 - 83FF & RICH Hubs & Hubs for RICH, last digit: sector divided by 2 \\ -8400 - 84FF & RPC Hubs & Hubs for RPC, last digit: sector divided by 3 \\ +8300 - 83FF & RICH Hubs & Hubs for RICH, 3rd digit: sector divided by 2 \\ +8400 - 84FF & RPC Hubs & Hubs for RPC, 3rd digit: sector divided by 3 \\ 8500 - 85FF & Shower Hub & \\ 8600 - 86FF & TOF Hub & \\ 8700 - 87FF & Forward Wall Hub & \\